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34 Commits

Author SHA1 Message Date
angie
b86964fc4a Fix python releases CI again 2024-12-16 09:17:19 -03:00
angie
d4e5cf1b6d version bump 2024-12-16 08:38:28 -03:00
angie
33cc926a13 version bump 2024-12-15 20:35:14 -03:00
angie
0188913d1b version bump 2024-07-21 19:26:37 -04:00
angie
f28fba1cc5 version bump 2024-07-16 21:15:37 -04:00
Angie
2c5e2cfc26 Implement rfe 2024-07-13 17:30:13 -04:00
angie
ee77a95d5d version bump 2024-07-12 11:45:48 -04:00
angie
b284f11232 version bump 2024-05-22 12:49:08 -04:00
angie
9f3107d812 misc_expandJalr 2024-04-23 11:09:58 -04:00
Anghelo Carvajal
b51b62da45
ALLEGREX support (#60) 
* setup ALLEGREX

* more setup

* clo

* fix

* Implement SPECIAL_RS and SPECIAL_SA instructions

* more table placeholders

* Implement bshfl instructions

* Rename to R4000Allegrex

* Implement SPECIAL instructions

* Add tests

* Remove some duplicated tests

* Implement SPECIAL3 instructions

* fix bug in test

* update

* Implement COPz

* Implement SPECIAL2 instructions

* Implement COP1

* Yeet cop3

* som tests

* bvf, bvfl, bvt, bvtl

* fix bshfl prefix

* need to implement the vfpu registers

* implement vt_7?

* R4000AllegrexVF -> R4000AllegrexVScalar

* Add test suite to compare with the sn toolchain decoding

* more vfpu test cases

* forgor this

* I can't decide how to name these registers

* Prepare tables for all register types

* Fix typo

* Implement vector scalar register operands

* Implement quad registers

* Fix tests?

* svl.q, svr.q

* Implement a bunch of vfpu0 instructions

* implement registers for `.t` and `.p` instructions

* Implement VFPU1 instructions

* bleh

* VFPU1, VFPU3 and `vcmp.`

* Fix wrong register type on some instructions

* start vfpu3

* Implement VFPU3 instructions

* start categorizing VFPU4

* Categorize VFPU5

* VFPU6 identification

* Identify VFPU7

* COP2 is weird

* organize COP2 a bit

* Add test cases for VFPU4 FMT

* VFPU4 FMT2 stuff

* VFPU4 FMT3 stuff

* VFPU5 stuff

* VFPU6 stuff

* VFPU7 stuff

* Implement COP2 instructions

* Implement vmov, vabs and vneg

* VPFU4 FMT0 FMT0 FMT0 implemented

* VFPU FMT0 FMT0 FMT2

* vnrcp, vnsin, vrexp2

* vrnds, vrndi, vrndf1, vrndf2

* Change tests a bit

* vf2h, vh2f, vsbz, vlgb

* vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s

* vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg

* vsrt3, vsrt4, vsgn

* vmfvc and vmtvc placeholders

* vt4444, vt5551, vt5650

* vcst placeholder

* vf2in

* vf2iz

* vf2iu, vf2id, vi2f

* vcmovt, vcmovf

* vwbn.s, viim.s, vfim.s

* vpfxs, vpfxt, vpfxd, vnop, vsync, vflush

* vmmov, vmidt, vmzero, vmone

* vrot

* vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul

* Implement matrix operands

* fix matrix operands

* Fix `illegal` tests

* hack out a way to check the test cases are assemblable

* test-fixing: branches

* fix more test cases

* fix vmfvc and vmtvc

* more test fixing

* vdiv and fix operand R323

* more test fixing

* Fix matrix operands

* implement vcmp comparisons

* fix vsync2

* vsqrt and vrndf1 fixes

* Implement "constant" operand for `vcst`

* Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f

* Add missing vcmovt and vcmovf operands

* Add missing vwbn operand

* Tests cases for vmmul

* Fix vtfm2

* Implement "transpose matrix register"

* Add placeholders for the remaining missing operands

* Implement viim operand

* Implement vrot code operand

* placeholders for rp and wp operands

* test cases for vpfxs, vpfxt and vpfxd

* Properly implement rpx, rpy, rpz and rpw

* Properly implement wpx, wpy, wpz and wpw operands

* Implement vfim

* changelog

* readme

* some cleanup

* Restructure some tables

* more table restructure

* fix tests

* more table yeeting

* more cleanup

* more cleanup

* reanming

* moar

* fmt
 2024-04-22 13:15:58 -04:00
angie
6923a393de version bump 2024-04-03 13:12:41 -03:00
angie
a701f616bf cleanups 2024-03-18 10:16:51 -03:00
angie
ebf82b91d9 version bump 2024-03-17 11:18:13 -03:00
angie
d717d29f0f version bump 2024-03-10 11:06:53 -03:00
angie
2189f99e11 Update cibuildwheel on GHA 2024-02-18 16:50:30 -03:00
angie
59042b2777 version bump 2024-02-18 13:13:05 -03:00
angie
8bb835b8c6 Instruction.getProcessedImmediate now raises an exception if the instruction does not contain an immediate field. 2024-02-11 10:54:56 -03:00
angie
8b17b28683 version bump 2024-01-28 13:52:35 -03:00
angie
e8c9217a82 version bump 2024-01-28 12:24:33 -03:00
angie
3b42e1ca00 version bump 2023-12-25 15:07:58 -03:00
Angie
a4029b7006 version bump 2023-11-12 12:26:37 -03:00
Anghelo Carvajal
8237818ff9
Add R3000GTE instruction set support (#31) 
* initial gte setup

* starting to parse gte instructions

* R3000_GTE -> R3000GTE

* decode all the non-operand instructions

* remove printfs, whoops

* decode gte with operands

* cleanups

* bindings stuffs

* RabbitizerInstrId_isValid

* fix missing include
 2023-04-29 23:07:07 -04:00
angie
7febb68bce docs: simple api usage example 2022-12-23 23:21:54 -03:00
angie
5ca1106392 reorder stuff in readme 2022-12-23 21:41:45 -03:00
angie
b4a8771df1 version bump 2022-12-20 13:03:11 -03:00
Angie
61d30e5aa1 Change treatJAsUnconditionalBranch to true by default 2022-12-18 21:09:14 -03:00
Angie
59f143b21d rust stuff on readme 2022-12-18 18:37:07 -03:00
Anghelo Carvajal
fb8c1edbd7
Rust bindings (#17) 
* Generate bindings for enums

* Add .gitignore Cargo didn't automatically made

* Actually build the files into the library

* `pub` in `mod` to fix warning

* instruction struct

* Instruction rust binding

* Add InstrId::ALL_MAX

* link C library to rust

* Publish crate CI

* test

* config bindings

* add getters for registers

* add names methods for register enums

* get_operand_type

* feedback from simon

* Forgot to add new file to python setup.py

* get_operands_slice

* add stuff to cargo.toml
 2022-12-18 15:15:39 -03:00
angie
4be4f6798d Update references 2022-12-14 15:27:16 -03:00
Anghelo Carvajal
136fb7a09a
Add R5900 support (#5) 
* starting r5900 stuff

* operands of pmaddh

* expose R5900 to python

* fix merge issues

* move to subtables

* mmi0 and mmi3

* the rest of mmi instructions

* normal, special, regimm and cop0

* fpu_s

* cop2 special1

* starting cop2 special2

* the rest of special2

* operands for normal, special, mmi and mmi0

* mmi1 and mmi2

* Fix mmi

* sync.p

* mmi3 and cop1

* add r5900 opcodes to InstrId.pyi

* add invalid bits to unknown instruction comment

* progress on cop2 special1

* kinda finish cop2 special1

* cop2 special2 progress

* Special case for R5900 cvt.w.s -> trunc.w.s

* R5900 c.olt.s and c.ole.s

* Fix a bunch of VU0 instructions

* I'm getting tired of this bullshit

* vlqi, vsqi, vlqd, vsqd

* fix some operands

* fix div1

* lqc2 and sqc2

* sqrt.s and mult

* fix mtsa and bc2

* Remove redundant .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN

* RabbitizerInstrSuffix

* Impleme instr suffix type

* add instr suffix to remaining instructions

* ifdef out xyzw suffix from registers

* format

* fix warnings

* uncomment stuff on InstrId.pyi

* readme
 2022-08-27 12:22:48 -04:00
Anghelo Carvajal
f8979ede3e
Fix RSP instruction decoding (#4) 
* Use the proper registers on RSP GPR instructions

* Add IMM_base operand to RSP instructions

* Use `ra` on RSP GPR registers

* Fix RABBITIZER_OPERAND_TYPE_RSP_rd

* ??

* fix vector register element index

* fix RSP mfc2 and mtc2

* fix vmov and similar instructions

* format

* update readme

* version pump
 2022-08-22 16:27:51 -04:00
angie
274c889241 Some readme work 2022-06-23 00:29:41 -04:00
angie
1b082d4fe8 Initial structure porting 2022-06-03 13:46:51 -04:00
angie
c74c3be0a2 First commit 2022-06-03 01:37:52 -04:00