mirror of
https://github.com/Decompollaborate/rabbitizer.git
synced 2025-04-07 01:20:11 +00:00
ALLEGREX support (#60)
* setup ALLEGREX * more setup * clo * fix * Implement SPECIAL_RS and SPECIAL_SA instructions * more table placeholders * Implement bshfl instructions * Rename to R4000Allegrex * Implement SPECIAL instructions * Add tests * Remove some duplicated tests * Implement SPECIAL3 instructions * fix bug in test * update * Implement COPz * Implement SPECIAL2 instructions * Implement COP1 * Yeet cop3 * som tests * bvf, bvfl, bvt, bvtl * fix bshfl prefix * need to implement the vfpu registers * implement vt_7? * R4000AllegrexVF -> R4000AllegrexVScalar * Add test suite to compare with the sn toolchain decoding * more vfpu test cases * forgor this * I can't decide how to name these registers * Prepare tables for all register types * Fix typo * Implement vector scalar register operands * Implement quad registers * Fix tests? * svl.q, svr.q * Implement a bunch of vfpu0 instructions * implement registers for `.t` and `.p` instructions * Implement VFPU1 instructions * bleh * VFPU1, VFPU3 and `vcmp.` * Fix wrong register type on some instructions * start vfpu3 * Implement VFPU3 instructions * start categorizing VFPU4 * Categorize VFPU5 * VFPU6 identification * Identify VFPU7 * COP2 is weird * organize COP2 a bit * Add test cases for VFPU4 FMT * VFPU4 FMT2 stuff * VFPU4 FMT3 stuff * VFPU5 stuff * VFPU6 stuff * VFPU7 stuff * Implement COP2 instructions * Implement vmov, vabs and vneg * VPFU4 FMT0 FMT0 FMT0 implemented * VFPU FMT0 FMT0 FMT2 * vnrcp, vnsin, vrexp2 * vrnds, vrndi, vrndf1, vrndf2 * Change tests a bit * vf2h, vh2f, vsbz, vlgb * vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s * vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg * vsrt3, vsrt4, vsgn * vmfvc and vmtvc placeholders * vt4444, vt5551, vt5650 * vcst placeholder * vf2in * vf2iz * vf2iu, vf2id, vi2f * vcmovt, vcmovf * vwbn.s, viim.s, vfim.s * vpfxs, vpfxt, vpfxd, vnop, vsync, vflush * vmmov, vmidt, vmzero, vmone * vrot * vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul * Implement matrix operands * fix matrix operands * Fix `illegal` tests * hack out a way to check the test cases are assemblable * test-fixing: branches * fix more test cases * fix vmfvc and vmtvc * more test fixing * vdiv and fix operand R323 * more test fixing * Fix matrix operands * implement vcmp comparisons * fix vsync2 * vsqrt and vrndf1 fixes * Implement "constant" operand for `vcst` * Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f * Add missing vcmovt and vcmovf operands * Add missing vwbn operand * Tests cases for vmmul * Fix vtfm2 * Implement "transpose matrix register" * Add placeholders for the remaining missing operands * Implement viim operand * Implement vrot code operand * placeholders for rp and wp operands * test cases for vpfxs, vpfxt and vpfxd * Properly implement rpx, rpy, rpz and rpw * Properly implement wpx, wpy, wpz and wpw operands * Implement vfim * changelog * readme * some cleanup * Restructure some tables * more table restructure * fix tests * more table yeeting * more cleanup * more cleanup * reanming * moar * fmt
This commit is contained in:
Anghelo Carvajal
GitHub
parent
9bf73dd20b
commit
b51b62da45
42
.github/workflows/make.yml
vendored
42
.github/workflows/make.yml
vendored
@ -149,6 +149,48 @@ jobs:
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- name: Run instruction check - r3000gte_disasm
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run: ./build/tests/c/instruction_checks/r3000gte_disasm.elf
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instruction_checks_r4000allegrex_disasm:
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name: Test - instruction_checks_r4000allegrex_disasm
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needs: [build_repo]
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runs-on: ubuntu-latest
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||||
|
||||
steps:
|
||||
- name: Checkout reposistory
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||||
uses: actions/checkout@v4
|
||||
|
||||
- name: Download build artifacts
|
||||
uses: actions/download-artifact@v4
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||||
with:
|
||||
name: artifact
|
||||
path: build/
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||||
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- name: Make tests executable
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run: chmod --recursive +x build/
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- name: Run instruction check - r4000allegrex_disasm
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run: ./build/tests/c/instruction_checks/r4000allegrex_disasm.elf
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instruction_checks_r4000allegrex_vfpu_disasm:
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name: Test - instruction_checks_r4000allegrex_vfpu_disasm
|
||||
needs: [build_repo]
|
||||
runs-on: ubuntu-latest
|
||||
|
||||
steps:
|
||||
- name: Checkout reposistory
|
||||
uses: actions/checkout@v4
|
||||
|
||||
- name: Download build artifacts
|
||||
uses: actions/download-artifact@v4
|
||||
with:
|
||||
name: artifact
|
||||
path: build/
|
||||
|
||||
- name: Make tests executable
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run: chmod --recursive +x build/
|
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|
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- name: Run instruction check - r4000allegrex_vfpu_disasm
|
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run: ./build/tests/c/instruction_checks/r4000allegrex_vfpu_disasm.elf
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instruction_checks_r5900_trunc_cvt:
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name: Test - instruction_checks_r5900_trunc_cvt
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needs: [build_repo]
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11
CHANGELOG.md
11
CHANGELOG.md
@ -7,6 +7,17 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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## [Unreleased]
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### Added
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- Add PSP's ALLEGREX instruction set support.
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- The global `regNames.r4000AllegrexVfpuControlNamedRegisters` option controls
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if named registers should be used for the VFPU control registers of the R4000
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ALLEGREX.
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- `Utils.floatRepr_32From16` function.
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- Converts a half float to a single precision float.
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- Both the argument and the return value correspond to their hex
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representation instead of an actual float.
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### Changed
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- Cleanups in tests code.
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@ -4,7 +4,7 @@
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[package]
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name = "rabbitizer"
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# Version should be synced with include/common/RabbitizerVersion.h
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version = "1.9.6"
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version = "1.10.0"
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edition = "2021"
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authors = ["Anghelo Carvajal <angheloalf95@gmail.com>"]
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description = "MIPS instruction decoder"
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2
Makefile
2
Makefile
@ -72,7 +72,7 @@ CXX_FILES := $(foreach dir,$(SRCXX_DIRS),$(wildcard $(dir)/*.cpp))
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HXX_FILES := $(foreach dir,$(IINC_XX),$(wildcard $(dir)/**/*.hpp))
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OXX_FILES := $(foreach f,$(CXX_FILES:.cpp=.o),build/$f)
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TESTS_DIRS := $(shell find tests -type d)
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TESTS_DIRS := $(shell find tests -mindepth 1 -type d -not -path "tests/asm*")
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TESTS_C := $(foreach dir,$(TESTS_DIRS),$(wildcard $(dir)/*.c))
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TESTS_CXX := $(foreach dir,$(TESTS_DIRS),$(wildcard $(dir)/*.cpp))
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TESTS_ELFS := $(foreach f,$(TESTS_C:.c=.elf) $(TESTS_CXX:.cpp=.elf),build/$f)
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22
README.md
22
README.md
@ -41,6 +41,8 @@ MIPS instruction decoder API.
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- Main focus on MIPS I, II and III architectures. Partial support for MIPS IV too.
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- N64 RSP instruction decoding support.
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- RSP decoding has been tested to build back to matching assemblies with [armips](https://github.com/Kingcom/armips/).
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- R3000 GTE (PSX's CPU) decoding support.
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- R4000 ALLEGREX (PSP's CPU) decoding support.
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- R5900 (PS2's Emotion Engine processor) decoding support.
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## Non-features
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@ -63,7 +65,7 @@ If you use a `requirements.txt` file in your repository, then you can add this
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library with the following line:
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```txt
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rabbitizer>=1.9.5,<2.0.0
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rabbitizer>=1.10.0,<2.0.0
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```
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### Development version
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@ -72,6 +74,13 @@ The unstable development version is located at the
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[develop](https://github.com/Decompollaborate/rabbitizer/tree/develop)
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branch. PRs should be made into that branch instead of the main one.
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Note that building the Python bindings from source require the Python
|
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development package. Under Ubuntu/Debian based distros it can be installed with:
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```bash
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apt install python3-dev
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```
|
||||
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In case you want to mess with the latest development version without wanting to
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clone the repository, then you could use the following command:
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|
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@ -96,7 +105,7 @@ cargo add rabbitizer
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Or you can add it manually to your `Cargo.toml`:
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|
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```toml
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rabbitizer = "1.9.5"
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rabbitizer = "1.10.0"
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```
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See this crate at <https://crates.io/crates/rabbitizer>.
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@ -118,6 +127,15 @@ See this crate at <https://crates.io/crates/rabbitizer>.
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- no$psx documentation: <http://problemkaputt.de/psx-spx.htm#geometrytransformationenginegte>
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- <http://www.raphnet.net/electronique/psx_adaptor/Playstation.txt>
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- R4000 ALLEGREX:
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- ALLEGREX-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356332/ALLEGREX-Instruction_Manual-English.pdf>
|
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- FPU-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/14950191/FPU-Instruction_Manual-English.pdf>
|
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- VFPU-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356335/VFPU-Instruction_Manual-English.pdf>
|
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- VFPU-Users_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356333/VFPU-Users_Manual-English.pdf>
|
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- yet another PlayStationPortable Documentation <http://hitmen.c02.at/files/yapspd/psp_doc/frames.html>
|
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- Chapter "4.8 Allegrex Instructions" <http://hitmen.c02.at/files/yapspd/psp_doc/chap4.html#sec4.8>
|
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- GNU binutils: <https://github.com/bminor/binutils-gdb/compare/011365b...a0176d8>
|
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|
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- R5900:
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- EmotionEngine instruction decoding: <https://psi-rockin.github.io/ps2tek/#eeinstructiondecoding>
|
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- Official documentation from Toshiba: <https://wiki.qemu.org/images/2/2a/C790.pdf>
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@ -40,6 +40,52 @@ enum class IdType {
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R3000GTE_COP1,
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R3000GTE_COP2,
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R3000GTE_COP2_GTE,
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R4000ALLEGREX_INVALID,
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R4000ALLEGREX_NORMAL,
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R4000ALLEGREX_SPECIAL,
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R4000ALLEGREX_SPECIAL_RS,
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R4000ALLEGREX_SPECIAL_SA,
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R4000ALLEGREX_REGIMM,
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R4000ALLEGREX_SPECIAL2,
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R4000ALLEGREX_SPECIAL3,
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R4000ALLEGREX_SPECIAL3_BSHFL,
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R4000ALLEGREX_COP0,
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R4000ALLEGREX_COP0_BC0,
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R4000ALLEGREX_COP0_TLB,
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R4000ALLEGREX_COP1,
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R4000ALLEGREX_COP1_BC1,
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R4000ALLEGREX_COP1_FPUS,
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R4000ALLEGREX_COP1_FPUW,
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R4000ALLEGREX_COP2,
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R4000ALLEGREX_COP2_BC2,
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R4000ALLEGREX_COP2_MFHC2,
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R4000ALLEGREX_COP2_MFHC2_P,
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R4000ALLEGREX_COP2_MFHC2_P_S,
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R4000ALLEGREX_COP2_MTHC2,
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R4000ALLEGREX_VFPU0,
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R4000ALLEGREX_VFPU1,
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R4000ALLEGREX_VFPU3,
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R4000ALLEGREX_VFPU4,
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R4000ALLEGREX_VFPU4_FMT0,
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R4000ALLEGREX_VFPU4_FMT0_FMT0,
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R4000ALLEGREX_VFPU4_FMT0_FMT2,
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R4000ALLEGREX_VFPU4_FMT0_FMT3,
|
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R4000ALLEGREX_VFPU4_FMT0_RND,
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R4000ALLEGREX_VFPU4_FMT0_CVTFLT,
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R4000ALLEGREX_VFPU4_FMT0_CVTINT,
|
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R4000ALLEGREX_VFPU4_FMT0_FMT8,
|
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R4000ALLEGREX_VFPU4_FMT0_FMT9,
|
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R4000ALLEGREX_VFPU4_FMT0_CONTROL,
|
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R4000ALLEGREX_VFPU4_FMT0_COLOR,
|
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R4000ALLEGREX_VFPU4_FMT0_CST,
|
||||
R4000ALLEGREX_VFPU4_FMT2,
|
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R4000ALLEGREX_VFPU4_FMT2_CNDMOVE,
|
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R4000ALLEGREX_VFPU5,
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R4000ALLEGREX_VFPU6,
|
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R4000ALLEGREX_VFPU6_FMT7,
|
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R4000ALLEGREX_VFPU6_FMT7_FMT0,
|
||||
R4000ALLEGREX_VFPU7,
|
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R4000ALLEGREX_QUADLR,
|
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R5900_INVALID,
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R5900_NORMAL,
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R5900_SPECIAL,
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||||
|
||||
@ -52,6 +52,63 @@ enum class OperandType {
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r3000gte_v,
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r3000gte_cv,
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r3000gte_lm,
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r4000allegrex_s_vs,
|
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r4000allegrex_s_vt,
|
||||
r4000allegrex_s_vd,
|
||||
r4000allegrex_s_vt_imm,
|
||||
r4000allegrex_s_vd_imm,
|
||||
r4000allegrex_p_vs,
|
||||
r4000allegrex_p_vt,
|
||||
r4000allegrex_p_vd,
|
||||
r4000allegrex_t_vs,
|
||||
r4000allegrex_t_vt,
|
||||
r4000allegrex_t_vd,
|
||||
r4000allegrex_q_vs,
|
||||
r4000allegrex_q_vt,
|
||||
r4000allegrex_q_vd,
|
||||
r4000allegrex_q_vt_imm,
|
||||
r4000allegrex_mp_vs,
|
||||
r4000allegrex_mp_vt,
|
||||
r4000allegrex_mp_vd,
|
||||
r4000allegrex_mp_vs_transpose,
|
||||
r4000allegrex_mt_vs,
|
||||
r4000allegrex_mt_vt,
|
||||
r4000allegrex_mt_vd,
|
||||
r4000allegrex_mt_vs_transpose,
|
||||
r4000allegrex_mq_vs,
|
||||
r4000allegrex_mq_vt,
|
||||
r4000allegrex_mq_vd,
|
||||
r4000allegrex_mq_vs_transpose,
|
||||
r4000allegrex_cop2cs,
|
||||
r4000allegrex_cop2cd,
|
||||
r4000allegrex_pos,
|
||||
r4000allegrex_size,
|
||||
r4000allegrex_size_plus_pos,
|
||||
r4000allegrex_imm3,
|
||||
r4000allegrex_offset14_base,
|
||||
r4000allegrex_offset14_base_maybe_wb,
|
||||
r4000allegrex_vcmp_cond,
|
||||
r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vconstant,
|
||||
r4000allegrex_power_of_two,
|
||||
r4000allegrex_vfpu_cc_bit,
|
||||
r4000allegrex_bn,
|
||||
r4000allegrex_int16,
|
||||
r4000allegrex_float16,
|
||||
r4000allegrex_p_vrot_code,
|
||||
r4000allegrex_t_vrot_code,
|
||||
r4000allegrex_q_vrot_code,
|
||||
r4000allegrex_rpx,
|
||||
r4000allegrex_rpy,
|
||||
r4000allegrex_rpz,
|
||||
r4000allegrex_rpw,
|
||||
r4000allegrex_wpx,
|
||||
r4000allegrex_wpy,
|
||||
r4000allegrex_wpz,
|
||||
r4000allegrex_wpw,
|
||||
r5900_I,
|
||||
r5900_Q,
|
||||
r5900_R,
|
||||
|
||||
1076
cplusplus/include/generated/Registers_enum_classes.hpp
generated
1076
cplusplus/include/generated/Registers_enum_classes.hpp
generated
File diff suppressed because it is too large
Load Diff
314
cplusplus/include/generated/UniqueId_enum_class.hpp
generated
314
cplusplus/include/generated/UniqueId_enum_class.hpp
generated
@ -460,6 +460,320 @@ enum class UniqueId {
|
||||
r3000gte_USERDEF_18,
|
||||
r3000gte_USERDEF_19,
|
||||
r3000gte_MAX,
|
||||
r4000allegrex_INVALID,
|
||||
r4000allegrex_lv_s,
|
||||
r4000allegrex_sv_s,
|
||||
r4000allegrex_lv_q,
|
||||
r4000allegrex_sv_q,
|
||||
r4000allegrex_clz,
|
||||
r4000allegrex_clo,
|
||||
r4000allegrex_madd,
|
||||
r4000allegrex_maddu,
|
||||
r4000allegrex_msub,
|
||||
r4000allegrex_msubu,
|
||||
r4000allegrex_max,
|
||||
r4000allegrex_min,
|
||||
r4000allegrex_srl,
|
||||
r4000allegrex_rotr,
|
||||
r4000allegrex_srlv,
|
||||
r4000allegrex_rotrv,
|
||||
r4000allegrex_sleep,
|
||||
r4000allegrex_mfie,
|
||||
r4000allegrex_mtie,
|
||||
r4000allegrex_ext,
|
||||
r4000allegrex_ins,
|
||||
r4000allegrex_wsbh,
|
||||
r4000allegrex_wsbw,
|
||||
r4000allegrex_seb,
|
||||
r4000allegrex_seh,
|
||||
r4000allegrex_bitrev,
|
||||
r4000allegrex_bvf,
|
||||
r4000allegrex_bvt,
|
||||
r4000allegrex_bvfl,
|
||||
r4000allegrex_bvtl,
|
||||
r4000allegrex_mfv,
|
||||
r4000allegrex_mfvc,
|
||||
r4000allegrex_vsync2,
|
||||
r4000allegrex_mtv,
|
||||
r4000allegrex_mtvc,
|
||||
r4000allegrex_vadd_s,
|
||||
r4000allegrex_vadd_p,
|
||||
r4000allegrex_vadd_t,
|
||||
r4000allegrex_vadd_q,
|
||||
r4000allegrex_vsub_s,
|
||||
r4000allegrex_vsub_p,
|
||||
r4000allegrex_vsub_t,
|
||||
r4000allegrex_vsub_q,
|
||||
r4000allegrex_vsbn_s,
|
||||
r4000allegrex_vdiv_s,
|
||||
r4000allegrex_vdiv_p,
|
||||
r4000allegrex_vdiv_t,
|
||||
r4000allegrex_vdiv_q,
|
||||
r4000allegrex_vmul_s,
|
||||
r4000allegrex_vmul_p,
|
||||
r4000allegrex_vmul_t,
|
||||
r4000allegrex_vmul_q,
|
||||
r4000allegrex_vdot_p,
|
||||
r4000allegrex_vdot_t,
|
||||
r4000allegrex_vdot_q,
|
||||
r4000allegrex_vscl_p,
|
||||
r4000allegrex_vscl_t,
|
||||
r4000allegrex_vscl_q,
|
||||
r4000allegrex_vhdp_p,
|
||||
r4000allegrex_vhdp_t,
|
||||
r4000allegrex_vhdp_q,
|
||||
r4000allegrex_vcrs_t,
|
||||
r4000allegrex_vdet_p,
|
||||
r4000allegrex_vcmp_s,
|
||||
r4000allegrex_vcmp_p,
|
||||
r4000allegrex_vcmp_t,
|
||||
r4000allegrex_vcmp_q,
|
||||
r4000allegrex_vmin_s,
|
||||
r4000allegrex_vmin_p,
|
||||
r4000allegrex_vmin_t,
|
||||
r4000allegrex_vmin_q,
|
||||
r4000allegrex_vmax_s,
|
||||
r4000allegrex_vmax_p,
|
||||
r4000allegrex_vmax_t,
|
||||
r4000allegrex_vmax_q,
|
||||
r4000allegrex_vscmp_s,
|
||||
r4000allegrex_vscmp_p,
|
||||
r4000allegrex_vscmp_t,
|
||||
r4000allegrex_vscmp_q,
|
||||
r4000allegrex_vsge_s,
|
||||
r4000allegrex_vsge_p,
|
||||
r4000allegrex_vsge_t,
|
||||
r4000allegrex_vsge_q,
|
||||
r4000allegrex_vslt_s,
|
||||
r4000allegrex_vslt_p,
|
||||
r4000allegrex_vslt_t,
|
||||
r4000allegrex_vslt_q,
|
||||
r4000allegrex_vwbn_s,
|
||||
r4000allegrex_vmov_s,
|
||||
r4000allegrex_vmov_p,
|
||||
r4000allegrex_vmov_t,
|
||||
r4000allegrex_vmov_q,
|
||||
r4000allegrex_vabs_s,
|
||||
r4000allegrex_vabs_p,
|
||||
r4000allegrex_vabs_t,
|
||||
r4000allegrex_vabs_q,
|
||||
r4000allegrex_vneg_s,
|
||||
r4000allegrex_vneg_p,
|
||||
r4000allegrex_vneg_t,
|
||||
r4000allegrex_vneg_q,
|
||||
r4000allegrex_vidt_p,
|
||||
r4000allegrex_vidt_q,
|
||||
r4000allegrex_vsat0_s,
|
||||
r4000allegrex_vsat0_p,
|
||||
r4000allegrex_vsat0_t,
|
||||
r4000allegrex_vsat0_q,
|
||||
r4000allegrex_vsat1_s,
|
||||
r4000allegrex_vsat1_p,
|
||||
r4000allegrex_vsat1_t,
|
||||
r4000allegrex_vsat1_q,
|
||||
r4000allegrex_vzero_s,
|
||||
r4000allegrex_vzero_p,
|
||||
r4000allegrex_vzero_t,
|
||||
r4000allegrex_vzero_q,
|
||||
r4000allegrex_vone_s,
|
||||
r4000allegrex_vone_p,
|
||||
r4000allegrex_vone_t,
|
||||
r4000allegrex_vone_q,
|
||||
r4000allegrex_vrcp_s,
|
||||
r4000allegrex_vrcp_p,
|
||||
r4000allegrex_vrcp_t,
|
||||
r4000allegrex_vrcp_q,
|
||||
r4000allegrex_vrsq_s,
|
||||
r4000allegrex_vrsq_p,
|
||||
r4000allegrex_vrsq_t,
|
||||
r4000allegrex_vrsq_q,
|
||||
r4000allegrex_vsin_s,
|
||||
r4000allegrex_vsin_p,
|
||||
r4000allegrex_vsin_t,
|
||||
r4000allegrex_vsin_q,
|
||||
r4000allegrex_vcos_s,
|
||||
r4000allegrex_vcos_p,
|
||||
r4000allegrex_vcos_t,
|
||||
r4000allegrex_vcos_q,
|
||||
r4000allegrex_vexp2_s,
|
||||
r4000allegrex_vexp2_p,
|
||||
r4000allegrex_vexp2_t,
|
||||
r4000allegrex_vexp2_q,
|
||||
r4000allegrex_vlog2_s,
|
||||
r4000allegrex_vlog2_p,
|
||||
r4000allegrex_vlog2_t,
|
||||
r4000allegrex_vlog2_q,
|
||||
r4000allegrex_vsqrt_s,
|
||||
r4000allegrex_vsqrt_p,
|
||||
r4000allegrex_vsqrt_t,
|
||||
r4000allegrex_vsqrt_q,
|
||||
r4000allegrex_vasin_s,
|
||||
r4000allegrex_vasin_p,
|
||||
r4000allegrex_vasin_t,
|
||||
r4000allegrex_vasin_q,
|
||||
r4000allegrex_vnrcp_s,
|
||||
r4000allegrex_vnrcp_p,
|
||||
r4000allegrex_vnrcp_t,
|
||||
r4000allegrex_vnrcp_q,
|
||||
r4000allegrex_vnsin_s,
|
||||
r4000allegrex_vnsin_p,
|
||||
r4000allegrex_vnsin_t,
|
||||
r4000allegrex_vnsin_q,
|
||||
r4000allegrex_vrexp2_s,
|
||||
r4000allegrex_vrexp2_p,
|
||||
r4000allegrex_vrexp2_t,
|
||||
r4000allegrex_vrexp2_q,
|
||||
r4000allegrex_vrnds_s,
|
||||
r4000allegrex_vrndi_s,
|
||||
r4000allegrex_vrndi_p,
|
||||
r4000allegrex_vrndi_t,
|
||||
r4000allegrex_vrndi_q,
|
||||
r4000allegrex_vrndf1_s,
|
||||
r4000allegrex_vrndf1_p,
|
||||
r4000allegrex_vrndf1_t,
|
||||
r4000allegrex_vrndf1_q,
|
||||
r4000allegrex_vrndf2_s,
|
||||
r4000allegrex_vrndf2_p,
|
||||
r4000allegrex_vrndf2_t,
|
||||
r4000allegrex_vrndf2_q,
|
||||
r4000allegrex_vf2h_p,
|
||||
r4000allegrex_vf2h_q,
|
||||
r4000allegrex_vh2f_s,
|
||||
r4000allegrex_vh2f_p,
|
||||
r4000allegrex_vsbz_s,
|
||||
r4000allegrex_vlgb_s,
|
||||
r4000allegrex_vuc2ifs_s,
|
||||
r4000allegrex_vc2i_s,
|
||||
r4000allegrex_vus2i_s,
|
||||
r4000allegrex_vus2i_p,
|
||||
r4000allegrex_vs2i_s,
|
||||
r4000allegrex_vs2i_p,
|
||||
r4000allegrex_vi2uc_q,
|
||||
r4000allegrex_vi2c_q,
|
||||
r4000allegrex_vi2us_p,
|
||||
r4000allegrex_vi2us_q,
|
||||
r4000allegrex_vi2s_p,
|
||||
r4000allegrex_vi2s_q,
|
||||
r4000allegrex_vsrt1_q,
|
||||
r4000allegrex_vsrt2_q,
|
||||
r4000allegrex_vbfy1_p,
|
||||
r4000allegrex_vbfy1_q,
|
||||
r4000allegrex_vbfy2_q,
|
||||
r4000allegrex_vocp_s,
|
||||
r4000allegrex_vocp_p,
|
||||
r4000allegrex_vocp_t,
|
||||
r4000allegrex_vocp_q,
|
||||
r4000allegrex_vsocp_s,
|
||||
r4000allegrex_vsocp_p,
|
||||
r4000allegrex_vfad_p,
|
||||
r4000allegrex_vfad_t,
|
||||
r4000allegrex_vfad_q,
|
||||
r4000allegrex_vavg_p,
|
||||
r4000allegrex_vavg_t,
|
||||
r4000allegrex_vavg_q,
|
||||
r4000allegrex_vsrt3_q,
|
||||
r4000allegrex_vsrt4_q,
|
||||
r4000allegrex_vsgn_s,
|
||||
r4000allegrex_vsgn_p,
|
||||
r4000allegrex_vsgn_t,
|
||||
r4000allegrex_vsgn_q,
|
||||
r4000allegrex_vmfvc,
|
||||
r4000allegrex_vmtvc,
|
||||
r4000allegrex_vt4444_q,
|
||||
r4000allegrex_vt5551_q,
|
||||
r4000allegrex_vt5650_q,
|
||||
r4000allegrex_vcst_s,
|
||||
r4000allegrex_vcst_p,
|
||||
r4000allegrex_vcst_t,
|
||||
r4000allegrex_vcst_q,
|
||||
r4000allegrex_vf2in_s,
|
||||
r4000allegrex_vf2in_p,
|
||||
r4000allegrex_vf2in_t,
|
||||
r4000allegrex_vf2in_q,
|
||||
r4000allegrex_vf2iz_s,
|
||||
r4000allegrex_vf2iz_p,
|
||||
r4000allegrex_vf2iz_t,
|
||||
r4000allegrex_vf2iz_q,
|
||||
r4000allegrex_vf2iu_s,
|
||||
r4000allegrex_vf2iu_p,
|
||||
r4000allegrex_vf2iu_t,
|
||||
r4000allegrex_vf2iu_q,
|
||||
r4000allegrex_vf2id_s,
|
||||
r4000allegrex_vf2id_p,
|
||||
r4000allegrex_vf2id_t,
|
||||
r4000allegrex_vf2id_q,
|
||||
r4000allegrex_vi2f_s,
|
||||
r4000allegrex_vi2f_p,
|
||||
r4000allegrex_vi2f_t,
|
||||
r4000allegrex_vi2f_q,
|
||||
r4000allegrex_vcmovt_s,
|
||||
r4000allegrex_vcmovt_p,
|
||||
r4000allegrex_vcmovt_t,
|
||||
r4000allegrex_vcmovt_q,
|
||||
r4000allegrex_vcmovf_s,
|
||||
r4000allegrex_vcmovf_p,
|
||||
r4000allegrex_vcmovf_t,
|
||||
r4000allegrex_vcmovf_q,
|
||||
r4000allegrex_vpfxs,
|
||||
r4000allegrex_vpfxt,
|
||||
r4000allegrex_vpfxd,
|
||||
r4000allegrex_viim_s,
|
||||
r4000allegrex_vfim_s,
|
||||
r4000allegrex_vmmul_p,
|
||||
r4000allegrex_vmmul_t,
|
||||
r4000allegrex_vmmul_q,
|
||||
r4000allegrex_vhtfm2_p,
|
||||
r4000allegrex_vtfm2_p,
|
||||
r4000allegrex_vhtfm3_t,
|
||||
r4000allegrex_vtfm3_t,
|
||||
r4000allegrex_vhtfm4_q,
|
||||
r4000allegrex_vtfm4_q,
|
||||
r4000allegrex_vmscl_p,
|
||||
r4000allegrex_vmscl_t,
|
||||
r4000allegrex_vmscl_q,
|
||||
r4000allegrex_vcrsp_t,
|
||||
r4000allegrex_vqmul_q,
|
||||
r4000allegrex_vrot_p,
|
||||
r4000allegrex_vrot_t,
|
||||
r4000allegrex_vrot_q,
|
||||
r4000allegrex_vmmov_p,
|
||||
r4000allegrex_vmmov_t,
|
||||
r4000allegrex_vmmov_q,
|
||||
r4000allegrex_vmidt_p,
|
||||
r4000allegrex_vmidt_t,
|
||||
r4000allegrex_vmidt_q,
|
||||
r4000allegrex_vmzero_p,
|
||||
r4000allegrex_vmzero_t,
|
||||
r4000allegrex_vmzero_q,
|
||||
r4000allegrex_vmone_p,
|
||||
r4000allegrex_vmone_t,
|
||||
r4000allegrex_vmone_q,
|
||||
r4000allegrex_vnop,
|
||||
r4000allegrex_vsync,
|
||||
r4000allegrex_vflush,
|
||||
r4000allegrex_svl_q,
|
||||
r4000allegrex_svr_q,
|
||||
r4000allegrex_USERDEF_00,
|
||||
r4000allegrex_USERDEF_01,
|
||||
r4000allegrex_USERDEF_02,
|
||||
r4000allegrex_USERDEF_03,
|
||||
r4000allegrex_USERDEF_04,
|
||||
r4000allegrex_USERDEF_05,
|
||||
r4000allegrex_USERDEF_06,
|
||||
r4000allegrex_USERDEF_07,
|
||||
r4000allegrex_USERDEF_08,
|
||||
r4000allegrex_USERDEF_09,
|
||||
r4000allegrex_USERDEF_10,
|
||||
r4000allegrex_USERDEF_11,
|
||||
r4000allegrex_USERDEF_12,
|
||||
r4000allegrex_USERDEF_13,
|
||||
r4000allegrex_USERDEF_14,
|
||||
r4000allegrex_USERDEF_15,
|
||||
r4000allegrex_USERDEF_16,
|
||||
r4000allegrex_USERDEF_17,
|
||||
r4000allegrex_USERDEF_18,
|
||||
r4000allegrex_USERDEF_19,
|
||||
r4000allegrex_MAX,
|
||||
r5900_INVALID,
|
||||
r5900_lq,
|
||||
r5900_sq,
|
||||
|
||||
85
cplusplus/include/instructions/InstructionR4000Allegrex.hpp
Normal file
85
cplusplus/include/instructions/InstructionR4000Allegrex.hpp
Normal file
@ -0,0 +1,85 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
#ifndef RABBITIZER_INSTRUCTION_R4000ALLEGREX_HPP
|
||||
#define RABBITIZER_INSTRUCTION_R4000ALLEGREX_HPP
|
||||
#pragma once
|
||||
|
||||
#include "InstructionBase.hpp"
|
||||
|
||||
|
||||
namespace rabbitizer {
|
||||
class InstructionR4000Allegrex : public InstructionBase {
|
||||
public:
|
||||
InstructionR4000Allegrex(uint32_t word, uint32_t vram);
|
||||
virtual ~InstructionR4000Allegrex();
|
||||
|
||||
Registers::R4000Allegrex::S GetR4000Allegrex_s_vs() const;
|
||||
Registers::R4000Allegrex::S GetR4000Allegrex_s_vt() const;
|
||||
Registers::R4000Allegrex::S GetR4000Allegrex_s_vd() const;
|
||||
Registers::R4000Allegrex::S GetR4000Allegrex_s_vt_imm() const;
|
||||
Registers::R4000Allegrex::S GetR4000Allegrex_s_vd_imm() const;
|
||||
|
||||
Registers::R4000Allegrex::V2D GetR4000Allegrex_p_vs() const;
|
||||
Registers::R4000Allegrex::V2D GetR4000Allegrex_p_vt() const;
|
||||
Registers::R4000Allegrex::V2D GetR4000Allegrex_p_vd() const;
|
||||
|
||||
Registers::R4000Allegrex::V3D GetR4000Allegrex_t_vs() const;
|
||||
Registers::R4000Allegrex::V3D GetR4000Allegrex_t_vt() const;
|
||||
Registers::R4000Allegrex::V3D GetR4000Allegrex_t_vd() const;
|
||||
|
||||
Registers::R4000Allegrex::V4D GetR4000Allegrex_q_vs() const;
|
||||
Registers::R4000Allegrex::V4D GetR4000Allegrex_q_vt() const;
|
||||
Registers::R4000Allegrex::V4D GetR4000Allegrex_q_vd() const;
|
||||
Registers::R4000Allegrex::V4D GetR4000Allegrex_q_vt_imm() const;
|
||||
|
||||
Registers::R4000Allegrex::M2x2 GetR4000Allegrex_mp_vs() const;
|
||||
Registers::R4000Allegrex::M2x2 GetR4000Allegrex_mp_vt() const;
|
||||
Registers::R4000Allegrex::M2x2 GetR4000Allegrex_mp_vd() const;
|
||||
Registers::R4000Allegrex::M2x2 GetR4000Allegrex_mp_vs_transpose() const;
|
||||
|
||||
Registers::R4000Allegrex::M3x3 GetR4000Allegrex_mt_vs() const;
|
||||
Registers::R4000Allegrex::M3x3 GetR4000Allegrex_mt_vt() const;
|
||||
Registers::R4000Allegrex::M3x3 GetR4000Allegrex_mt_vd() const;
|
||||
Registers::R4000Allegrex::M3x3 GetR4000Allegrex_mt_vs_transpose() const;
|
||||
|
||||
Registers::R4000Allegrex::M4x4 GetR4000Allegrex_mq_vs() const;
|
||||
Registers::R4000Allegrex::M4x4 GetR4000Allegrex_mq_vt() const;
|
||||
Registers::R4000Allegrex::M4x4 GetR4000Allegrex_mq_vd() const;
|
||||
Registers::R4000Allegrex::M4x4 GetR4000Allegrex_mq_vs_transpose() const;
|
||||
|
||||
Registers::R4000Allegrex::VfpuControl GetR4000Allegrex_cop2cs() const;
|
||||
Registers::R4000Allegrex::VfpuControl GetR4000Allegrex_cop2cd() const;
|
||||
|
||||
uint8_t GetR4000Allegrex_pos() const;
|
||||
uint8_t GetR4000Allegrex_size() const;
|
||||
uint8_t GetR4000Allegrex_size_plus_pos() const;
|
||||
|
||||
uint8_t GetR4000Allegrex_imm3() const;
|
||||
|
||||
uint16_t GetR4000Allegrex_offset14() const;
|
||||
|
||||
uint8_t GetR4000Allegrex_vcmp_cond() const;
|
||||
|
||||
Registers::R4000Allegrex::VConstant GetR4000Allegrex_vconstant() const;
|
||||
|
||||
uint8_t GetR4000Allegrex_power_of_two() const;
|
||||
uint8_t GetR4000Allegrex_vfpu_cc_bit() const;
|
||||
uint8_t GetR4000Allegrex_bn() const;
|
||||
|
||||
uint16_t GetR4000Allegrex_intfloat16() const;
|
||||
uint8_t GetR4000Allegrex_vrot_code() const;
|
||||
|
||||
uint8_t GetR4000Allegrex_rpx() const;
|
||||
uint8_t GetR4000Allegrex_rpy() const;
|
||||
uint8_t GetR4000Allegrex_rpz() const;
|
||||
uint8_t GetR4000Allegrex_rpw() const;
|
||||
|
||||
uint8_t GetR4000Allegrex_wpx() const;
|
||||
uint8_t GetR4000Allegrex_wpy() const;
|
||||
uint8_t GetR4000Allegrex_wpz() const;
|
||||
uint8_t GetR4000Allegrex_wpw() const;
|
||||
};
|
||||
};
|
||||
|
||||
#endif
|
||||
@ -20,6 +20,7 @@
|
||||
#include "instructions/InstructionCpu.hpp"
|
||||
#include "instructions/InstructionRsp.hpp"
|
||||
#include "instructions/InstructionR3000GTE.hpp"
|
||||
#include "instructions/InstructionR4000Allegrex.hpp"
|
||||
#include "instructions/InstructionR5900.hpp"
|
||||
|
||||
#include "analysis/LoPairingInfo.hpp"
|
||||
|
||||
560
cplusplus/src/instructions/InstructionR4000Allegrex.cpp
Normal file
560
cplusplus/src/instructions/InstructionR4000Allegrex.cpp
Normal file
@ -0,0 +1,560 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
#include "instructions/InstructionR4000Allegrex.hpp"
|
||||
|
||||
#include <stdexcept>
|
||||
|
||||
#include "instructions/RabbitizerInstructionR4000Allegrex.h"
|
||||
|
||||
using namespace rabbitizer;
|
||||
|
||||
InstructionR4000Allegrex::InstructionR4000Allegrex(uint32_t word, uint32_t vram) : InstructionBase() {
|
||||
RabbitizerInstructionR4000Allegrex_init(&this->instr, word, vram);
|
||||
RabbitizerInstructionR4000Allegrex_processUniqueId(&this->instr);
|
||||
}
|
||||
|
||||
InstructionR4000Allegrex::~InstructionR4000Allegrex() {
|
||||
RabbitizerInstructionR4000Allegrex_destroy(&this->instr);
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::S InstructionR4000Allegrex::GetR4000Allegrex_s_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_s_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 's_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::S>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::S InstructionR4000Allegrex::GetR4000Allegrex_s_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_s_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 's_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::S>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::S InstructionR4000Allegrex::GetR4000Allegrex_s_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_s_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 's_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::S>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::S InstructionR4000Allegrex::GetR4000Allegrex_s_vt_imm() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_s_vt_imm)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 's_vt_imm' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::S>(RAB_INSTR_R4000ALLEGREX_GET_vt_imm(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::S InstructionR4000Allegrex::GetR4000Allegrex_s_vd_imm() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_s_vd_imm)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 's_vd_imm' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::S>(RAB_INSTR_R4000ALLEGREX_GET_vd_imm(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V2D InstructionR4000Allegrex::GetR4000Allegrex_p_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_p_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'p_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V2D>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V2D InstructionR4000Allegrex::GetR4000Allegrex_p_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_s_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 's_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V2D>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V2D InstructionR4000Allegrex::GetR4000Allegrex_p_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_p_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'p_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V2D>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V3D InstructionR4000Allegrex::GetR4000Allegrex_t_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_t_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 't_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V3D>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V3D InstructionR4000Allegrex::GetR4000Allegrex_t_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_t_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 't_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V3D>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V3D InstructionR4000Allegrex::GetR4000Allegrex_t_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_t_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 't_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V3D>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V4D InstructionR4000Allegrex::GetR4000Allegrex_q_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_q_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'q_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V4D>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V4D InstructionR4000Allegrex::GetR4000Allegrex_q_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_q_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'q_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V4D>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V4D InstructionR4000Allegrex::GetR4000Allegrex_q_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_q_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'q_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V4D>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::V4D InstructionR4000Allegrex::GetR4000Allegrex_q_vt_imm() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_q_vt_imm)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'q_vt_imm' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::V4D>(RAB_INSTR_R4000ALLEGREX_GET_vt_imm(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M2x2 InstructionR4000Allegrex::GetR4000Allegrex_mp_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mp_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mp_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M2x2>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M2x2 InstructionR4000Allegrex::GetR4000Allegrex_mp_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mp_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mp_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M2x2>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M2x2 InstructionR4000Allegrex::GetR4000Allegrex_mp_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mp_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mp_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M2x2>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M2x2 InstructionR4000Allegrex::GetR4000Allegrex_mp_vs_transpose() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mp_vs_transpose)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mp_vs_transpose' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M2x2>(RAB_INSTR_R4000ALLEGREX_GET_vs_transpose(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M3x3 InstructionR4000Allegrex::GetR4000Allegrex_mt_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mt_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mt_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M3x3>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M3x3 InstructionR4000Allegrex::GetR4000Allegrex_mt_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mt_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mt_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M3x3>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M3x3 InstructionR4000Allegrex::GetR4000Allegrex_mt_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mt_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mt_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M3x3>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M3x3 InstructionR4000Allegrex::GetR4000Allegrex_mt_vs_transpose() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mt_vs_transpose)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mt_vs_transpose' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M3x3>(RAB_INSTR_R4000ALLEGREX_GET_vs_transpose(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M4x4 InstructionR4000Allegrex::GetR4000Allegrex_mq_vs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mq_vs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mq_vs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M4x4>(RAB_INSTR_R4000ALLEGREX_GET_vs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M4x4 InstructionR4000Allegrex::GetR4000Allegrex_mq_vt() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mq_vt)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mq_vt' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M4x4>(RAB_INSTR_R4000ALLEGREX_GET_vt(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M4x4 InstructionR4000Allegrex::GetR4000Allegrex_mq_vd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mq_vd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mq_vd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M4x4>(RAB_INSTR_R4000ALLEGREX_GET_vd(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::M4x4 InstructionR4000Allegrex::GetR4000Allegrex_mq_vs_transpose() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_mq_vs_transpose)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'mq_vs_transpose' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::M4x4>(RAB_INSTR_R4000ALLEGREX_GET_vs_transpose(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::VfpuControl InstructionR4000Allegrex::GetR4000Allegrex_cop2cs() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_cop2cs)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'cop2cs' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::VfpuControl>(RAB_INSTR_R4000ALLEGREX_GET_cop2cs(&this->instr));
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::VfpuControl InstructionR4000Allegrex::GetR4000Allegrex_cop2cd() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_cop2cd)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'cop2cd' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::VfpuControl>(RAB_INSTR_R4000ALLEGREX_GET_cop2cd(&this->instr));
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_pos() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_pos)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'pos' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_pos(&this->instr);
|
||||
}
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_size() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_size)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'size' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_size(&this->instr);
|
||||
}
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_size_plus_pos() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_size_plus_pos)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'size_plus_pos' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_size_plus_pos(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_imm3() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_imm3)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'imm3' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_imm3(&this->instr);
|
||||
}
|
||||
|
||||
uint16_t InstructionR4000Allegrex::GetR4000Allegrex_offset14() const {
|
||||
#if 0
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_offset14)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'offset14' operand.");
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_offset14(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_vcmp_cond() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_vcmp_cond)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'vcmp_cond' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_vcmp_cond(&this->instr);
|
||||
}
|
||||
|
||||
Registers::R4000Allegrex::VConstant InstructionR4000Allegrex::GetR4000Allegrex_vconstant() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_vconstant)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'vconstant' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return static_cast<Registers::R4000Allegrex::VConstant>(RAB_INSTR_R4000ALLEGREX_GET_vconstant(&this->instr));
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_power_of_two() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_power_of_two)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'power_of_two' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_power_of_two(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_vfpu_cc_bit() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_vfpu_cc_bit)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'vfpu_cc_bit' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_vfpu_cc_bit(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_bn() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_bn)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'bn' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_bn(&this->instr);
|
||||
}
|
||||
|
||||
uint16_t InstructionR4000Allegrex::GetR4000Allegrex_intfloat16() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_int16) && !hasOperandAlias(OperandType::r4000allegrex_float16)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'intfloat16' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_intfloat16(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_vrot_code() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_p_vrot_code) &&
|
||||
!hasOperandAlias(OperandType::r4000allegrex_t_vrot_code) &&
|
||||
!hasOperandAlias(OperandType::r4000allegrex_q_vrot_code)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'vrot_code' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_vrot_code(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_rpx() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_rpx)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'rpx' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_rpx(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_rpy() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_rpy)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'rpy' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_rpy(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_rpz() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_rpz)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'rpz' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_rpz(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_rpw() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_rpw)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'rpw' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_rpw(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_wpx() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_wpx)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'wpx' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_wpx(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_wpy() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_wpy)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'wpy' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_wpy(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_wpz() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_wpz)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'wpz' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_wpz(&this->instr);
|
||||
}
|
||||
|
||||
uint8_t InstructionR4000Allegrex::GetR4000Allegrex_wpw() const {
|
||||
#ifdef RAB_SANITY_CHECKS
|
||||
if (!hasOperandAlias(OperandType::r4000allegrex_wpw)) {
|
||||
// TODO: make a rabbitizer exception class
|
||||
throw std::runtime_error("Instruction '" + getOpcodeName() + "' does not have 'wpw' operand.");
|
||||
}
|
||||
#endif
|
||||
|
||||
return RAB_INSTR_R4000ALLEGREX_GET_wpw(&this->instr);
|
||||
}
|
||||
@ -23,6 +23,7 @@ typedef struct RabbitizerConfig_RegisterNames {
|
||||
bool userFpcCsr; // Use FpcCsr as register $31 for the FP control/status register
|
||||
bool vr4300Cop0NamedRegisters; // Use named registers for VR4300's coprocessor 0 registers
|
||||
bool vr4300RspCop0NamedRegisters; // Use named registers for VR4300's RSP's coprocessor 0 registers
|
||||
bool r4000AllegrexVfpuControlNamedRegisters; // Use named registers for R4000 Allegrex's VFPU control registers
|
||||
} RabbitizerConfig_RegisterNames;
|
||||
|
||||
typedef struct RabbitizerConfig_PseudoInstr {
|
||||
|
||||
@ -13,8 +13,8 @@ extern "C" {
|
||||
|
||||
// Header version
|
||||
#define RAB_VERSION_MAJOR 1
|
||||
#define RAB_VERSION_MINOR 9
|
||||
#define RAB_VERSION_PATCH 6
|
||||
#define RAB_VERSION_MINOR 10
|
||||
#define RAB_VERSION_PATCH 0
|
||||
|
||||
#define RAB_VERSION_STR RAB_STRINGIFY(RAB_VERSION_MAJOR) "." RAB_STRINGIFY(RAB_VERSION_MINOR) "." RAB_STRINGIFY(RAB_VERSION_PATCH)
|
||||
|
||||
|
||||
@ -61,7 +61,7 @@ typedef enum RabTrinaryValue {
|
||||
#define RAB_STRINGIFY2(x) #x
|
||||
#define RAB_STRINGIFY(x) RAB_STRINGIFY2(x)
|
||||
|
||||
#define MASK(v, w) ((v) & ((1 << (w)) - 1))
|
||||
#define MASK(v, w) ((v) & ((1U << (w)) - 1U))
|
||||
|
||||
/*
|
||||
* the SHIFT macros take a value, a shift amount, and a width.
|
||||
@ -78,7 +78,7 @@ typedef enum RabTrinaryValue {
|
||||
#define SHIFTL(v, s, w) (MASK((v), (w)) << (s))
|
||||
#define SHIFTR(v, s, w) (MASK((v) >> (s), (w)))
|
||||
|
||||
#define BITREPACK(fullword, v, s, w) ((SHIFTR((fullword), (s)+(w), 32-((s)+(w))) << ((s)+(w))) | SHIFTL((v), (s), (w)) | MASK((fullword), (s)))
|
||||
#define BITREPACK(fullword, v, s, w) ((SHIFTR((fullword), (s)+(w), 32U-((s)+(w))) << ((s)+(w))) | SHIFTL((v), (s), (w)) | MASK((fullword), (s)))
|
||||
#define BITREPACK_RIGHT(fullword, v, s, w) (SHIFTL((v), (s), (w)) | MASK((fullword), (s)))
|
||||
|
||||
#define RABUTILS_BUFFER_ADVANCE(buffer, totalSize, expression) \
|
||||
@ -125,6 +125,8 @@ NON_NULL(1)
|
||||
size_t RabbitizerUtils_CharFill(char *dst, int count, char fillchar);
|
||||
NON_NULL(1, 3)
|
||||
size_t RabbitizerUtils_escapeString(char *dst, size_t dstSize, const char *src, size_t srcSize);
|
||||
CONST NODISCARD
|
||||
uint32_t RabbitizerUtils_floatRepr_32From16(uint16_t arg);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
1
include/generated/InstrCategory_Names_array.h
generated
1
include/generated/InstrCategory_Names_array.h
generated
@ -10,6 +10,7 @@ const char *const RabbitizerInstrCategory_Names[] = {
|
||||
[RABBITIZER_INSTRCAT_CPU] = "CPU",
|
||||
[RABBITIZER_INSTRCAT_RSP] = "RSP",
|
||||
[RABBITIZER_INSTRCAT_R3000GTE] = "R3000GTE",
|
||||
[RABBITIZER_INSTRCAT_R4000ALLEGREX] = "R4000ALLEGREX",
|
||||
[RABBITIZER_INSTRCAT_R5900] = "R5900",
|
||||
};
|
||||
|
||||
|
||||
1
include/generated/InstrCategory_enum.h
generated
1
include/generated/InstrCategory_enum.h
generated
@ -10,6 +10,7 @@ typedef enum RabbitizerInstrCategory {
|
||||
RABBITIZER_INSTRCAT_CPU,
|
||||
RABBITIZER_INSTRCAT_RSP,
|
||||
RABBITIZER_INSTRCAT_R3000GTE,
|
||||
RABBITIZER_INSTRCAT_R4000ALLEGREX,
|
||||
RABBITIZER_INSTRCAT_R5900,
|
||||
RABBITIZER_INSTRCAT_MAX,
|
||||
} RabbitizerInstrCategory;
|
||||
|
||||
314
include/generated/InstrDescriptor_Descriptors_array.h
generated
314
include/generated/InstrDescriptor_Descriptors_array.h
generated
@ -460,6 +460,320 @@ const RabbitizerInstrDescriptor RabbitizerInstrDescriptor_Descriptors[] = {
|
||||
[RABBITIZER_INSTR_ID_r3000gte_USERDEF_18] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r3000gte_USERDEF_19] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r3000gte_MAX] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_INVALID] = { .operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_immediate}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_lv_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_sv_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .modifiesRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_lv_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_sv_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb}, .instrType=RABBITIZER_INSTR_TYPE_I, .modifiesRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_clz] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_clo] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_madd] = { .operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRs=true, .readsRt=true, .modifiesHI=true, .modifiesLO=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_maddu] = { .operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRs=true, .readsRt=true, .modifiesHI=true, .modifiesLO=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_msub] = { .operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRs=true, .readsRt=true, .modifiesHI=true, .modifiesLO=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_msubu] = { .operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRs=true, .readsRt=true, .modifiesHI=true, .modifiesLO=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_max] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRs=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_min] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRs=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_srl] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_sa}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_rotr] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_sa}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_srlv] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRs=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_rotrv] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRs=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_sleep] = { .operands={0}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mfie] = { .operands={RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mtie] = { .operands={RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_ext] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs, RAB_OPERAND_r4000allegrex_pos, RAB_OPERAND_r4000allegrex_size}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRt=true, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_ins] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs, RAB_OPERAND_r4000allegrex_pos, RAB_OPERAND_r4000allegrex_size_plus_pos}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRt=true, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_wsbh] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_wsbw] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_seb] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_seh] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bitrev] = { .operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRd=true, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvf] = { .operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN, .isBranch=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvt] = { .operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN, .isBranch=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvfl] = { .operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN, .isBranch=true, .isBranchLikely=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvtl] = { .operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN, .isBranch=true, .isBranchLikely=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mfv] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mfvc] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_cop2cd}, .instrType=RABBITIZER_INSTR_TYPE_R, .modifiesRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsync2] = { .operands={0}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mtv] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mtvc] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_cop2cd}, .instrType=RABBITIZER_INSTR_TYPE_R, .readsRt=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsbn_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdot_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdot_t] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdot_q] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscl_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscl_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscl_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhdp_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhdp_t] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhdp_q] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcrs_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdet_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_s] = { .operands={RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_p] = { .operands={RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_t] = { .operands={RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_q] = { .operands={RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vwbn_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_bn}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vidt_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vidt_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrnds_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2h_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2h_q] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vh2f_s] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vh2f_p] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsbz_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlgb_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vuc2ifs_s] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vc2i_s] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vus2i_s] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vus2i_p] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vs2i_s] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vs2i_p] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2uc_q] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2c_q] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2us_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2us_q] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2s_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2s_q] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt1_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt2_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vbfy1_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vbfy1_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vbfy2_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsocp_s] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsocp_p] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfad_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfad_t] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfad_q] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vavg_p] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vavg_t] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vavg_q] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt3_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt4_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmfvc] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_cop2cs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmtvc] = { .operands={RAB_OPERAND_r4000allegrex_cop2cd, RAB_OPERAND_r4000allegrex_s_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vt4444_q] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vt5551_q] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vt5650_q] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_q_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_vconstant}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_vconstant}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_vconstant}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_vconstant}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_power_of_two}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_p_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_vfpu_cc_bit}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vpfxs] = { .operands={RAB_OPERAND_r4000allegrex_rpx, RAB_OPERAND_r4000allegrex_rpy, RAB_OPERAND_r4000allegrex_rpz, RAB_OPERAND_r4000allegrex_rpw}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vpfxt] = { .operands={RAB_OPERAND_r4000allegrex_rpx, RAB_OPERAND_r4000allegrex_rpy, RAB_OPERAND_r4000allegrex_rpz, RAB_OPERAND_r4000allegrex_rpw}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vpfxd] = { .operands={RAB_OPERAND_r4000allegrex_wpx, RAB_OPERAND_r4000allegrex_wpy, RAB_OPERAND_r4000allegrex_wpz, RAB_OPERAND_r4000allegrex_wpw}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_viim_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vt, RAB_OPERAND_r4000allegrex_int16}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfim_s] = { .operands={RAB_OPERAND_r4000allegrex_s_vt, RAB_OPERAND_r4000allegrex_float16}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmul_p] = { .operands={RAB_OPERAND_r4000allegrex_mp_vd, RAB_OPERAND_r4000allegrex_mp_vs_transpose, RAB_OPERAND_r4000allegrex_mp_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmul_t] = { .operands={RAB_OPERAND_r4000allegrex_mt_vd, RAB_OPERAND_r4000allegrex_mt_vs_transpose, RAB_OPERAND_r4000allegrex_mt_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmul_q] = { .operands={RAB_OPERAND_r4000allegrex_mq_vd, RAB_OPERAND_r4000allegrex_mq_vs_transpose, RAB_OPERAND_r4000allegrex_mq_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhtfm2_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_mp_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vtfm2_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_mp_vs, RAB_OPERAND_r4000allegrex_p_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhtfm3_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_mt_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vtfm3_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_mt_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhtfm4_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_mq_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vtfm4_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_mq_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmscl_p] = { .operands={RAB_OPERAND_r4000allegrex_mp_vd, RAB_OPERAND_r4000allegrex_mp_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmscl_t] = { .operands={RAB_OPERAND_r4000allegrex_mt_vd, RAB_OPERAND_r4000allegrex_mt_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmscl_q] = { .operands={RAB_OPERAND_r4000allegrex_mq_vd, RAB_OPERAND_r4000allegrex_mq_vs, RAB_OPERAND_r4000allegrex_s_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcrsp_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_t_vs, RAB_OPERAND_r4000allegrex_t_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vqmul_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_q_vs, RAB_OPERAND_r4000allegrex_q_vt}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrot_p] = { .operands={RAB_OPERAND_r4000allegrex_p_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_p_vrot_code}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrot_t] = { .operands={RAB_OPERAND_r4000allegrex_t_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_t_vrot_code}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrot_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vd, RAB_OPERAND_r4000allegrex_s_vs, RAB_OPERAND_r4000allegrex_q_vrot_code}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmov_p] = { .operands={RAB_OPERAND_r4000allegrex_mp_vd, RAB_OPERAND_r4000allegrex_mp_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmov_t] = { .operands={RAB_OPERAND_r4000allegrex_mt_vd, RAB_OPERAND_r4000allegrex_mt_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmov_q] = { .operands={RAB_OPERAND_r4000allegrex_mq_vd, RAB_OPERAND_r4000allegrex_mq_vs}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmidt_p] = { .operands={RAB_OPERAND_r4000allegrex_mp_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmidt_t] = { .operands={RAB_OPERAND_r4000allegrex_mt_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmidt_q] = { .operands={RAB_OPERAND_r4000allegrex_mq_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmzero_p] = { .operands={RAB_OPERAND_r4000allegrex_mp_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmzero_t] = { .operands={RAB_OPERAND_r4000allegrex_mt_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmzero_q] = { .operands={RAB_OPERAND_r4000allegrex_mq_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmone_p] = { .operands={RAB_OPERAND_r4000allegrex_mp_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmone_t] = { .operands={RAB_OPERAND_r4000allegrex_mt_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmone_q] = { .operands={RAB_OPERAND_r4000allegrex_mq_vd}, .instrType=RABBITIZER_INSTR_TYPE_R },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnop] = { .operands={0}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsync] = { .operands={0}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vflush] = { .operands={0}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_svl_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_svr_q] = { .operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .readsRs=true },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_00] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_01] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_02] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_03] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_04] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_05] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_06] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_07] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_08] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_09] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_10] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_11] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_12] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_13] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_14] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_15] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_16] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_17] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_18] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_19] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_MAX] = { .operands={0} },
|
||||
[RABBITIZER_INSTR_ID_r5900_INVALID] = { .operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_immediate}, .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN },
|
||||
[RABBITIZER_INSTR_ID_r5900_lq] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_immediate_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .modifiesRt=true, .readsRs=true, .canBeLo=true, .doesDereference=true, .doesLoad=true },
|
||||
[RABBITIZER_INSTR_ID_r5900_sq] = { .operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_immediate_base}, .instrType=RABBITIZER_INSTR_TYPE_I, .readsRs=true, .readsRt=true, .canBeLo=true, .doesDereference=true, .doesStore=true },
|
||||
|
||||
46
include/generated/InstrIdType_Names_array.h
generated
46
include/generated/InstrIdType_Names_array.h
generated
@ -40,6 +40,52 @@ const char *RabInstrIdType_Names[] = {
|
||||
[RAB_INSTR_ID_TYPE_R3000GTE_COP1] = "R3000GTE" "_" "COP1",
|
||||
[RAB_INSTR_ID_TYPE_R3000GTE_COP2] = "R3000GTE" "_" "COP2",
|
||||
[RAB_INSTR_ID_TYPE_R3000GTE_COP2_GTE] = "R3000GTE" "_" "COP2_GTE",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_INVALID] = "R4000ALLEGREX" "_" "INVALID",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_NORMAL] = "R4000ALLEGREX" "_" "NORMAL",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL] = "R4000ALLEGREX" "_" "SPECIAL",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL_RS] = "R4000ALLEGREX" "_" "SPECIAL_RS",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL_SA] = "R4000ALLEGREX" "_" "SPECIAL_SA",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_REGIMM] = "R4000ALLEGREX" "_" "REGIMM",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL2] = "R4000ALLEGREX" "_" "SPECIAL2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL3] = "R4000ALLEGREX" "_" "SPECIAL3",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL3_BSHFL] = "R4000ALLEGREX" "_" "SPECIAL3_BSHFL",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0] = "R4000ALLEGREX" "_" "COP0",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0_BC0] = "R4000ALLEGREX" "_" "COP0_BC0",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0_TLB] = "R4000ALLEGREX" "_" "COP0_TLB",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1] = "R4000ALLEGREX" "_" "COP1",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_BC1] = "R4000ALLEGREX" "_" "COP1_BC1",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUS] = "R4000ALLEGREX" "_" "COP1_FPUS",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUW] = "R4000ALLEGREX" "_" "COP1_FPUW",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2] = "R4000ALLEGREX" "_" "COP2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_BC2] = "R4000ALLEGREX" "_" "COP2_BC2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2] = "R4000ALLEGREX" "_" "COP2_MFHC2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2_P] = "R4000ALLEGREX" "_" "COP2_MFHC2_P",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2_P_S] = "R4000ALLEGREX" "_" "COP2_MFHC2_P_S",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MTHC2] = "R4000ALLEGREX" "_" "COP2_MTHC2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU0] = "R4000ALLEGREX" "_" "VFPU0",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU1] = "R4000ALLEGREX" "_" "VFPU1",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU3] = "R4000ALLEGREX" "_" "VFPU3",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4] = "R4000ALLEGREX" "_" "VFPU4",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0] = "R4000ALLEGREX" "_" "VFPU4_FMT0",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT0] = "R4000ALLEGREX" "_" "VFPU4_FMT0_FMT0",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT2] = "R4000ALLEGREX" "_" "VFPU4_FMT0_FMT2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT3] = "R4000ALLEGREX" "_" "VFPU4_FMT0_FMT3",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_RND] = "R4000ALLEGREX" "_" "VFPU4_FMT0_RND",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CVTFLT] = "R4000ALLEGREX" "_" "VFPU4_FMT0_CVTFLT",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CVTINT] = "R4000ALLEGREX" "_" "VFPU4_FMT0_CVTINT",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT8] = "R4000ALLEGREX" "_" "VFPU4_FMT0_FMT8",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT9] = "R4000ALLEGREX" "_" "VFPU4_FMT0_FMT9",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CONTROL] = "R4000ALLEGREX" "_" "VFPU4_FMT0_CONTROL",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_COLOR] = "R4000ALLEGREX" "_" "VFPU4_FMT0_COLOR",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CST] = "R4000ALLEGREX" "_" "VFPU4_FMT0_CST",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT2] = "R4000ALLEGREX" "_" "VFPU4_FMT2",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT2_CNDMOVE] = "R4000ALLEGREX" "_" "VFPU4_FMT2_CNDMOVE",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU5] = "R4000ALLEGREX" "_" "VFPU5",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6] = "R4000ALLEGREX" "_" "VFPU6",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6_FMT7] = "R4000ALLEGREX" "_" "VFPU6_FMT7",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6_FMT7_FMT0] = "R4000ALLEGREX" "_" "VFPU6_FMT7_FMT0",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU7] = "R4000ALLEGREX" "_" "VFPU7",
|
||||
[RAB_INSTR_ID_TYPE_R4000ALLEGREX_QUADLR] = "R4000ALLEGREX" "_" "QUADLR",
|
||||
[RAB_INSTR_ID_TYPE_R5900_INVALID] = "R5900" "_" "INVALID",
|
||||
[RAB_INSTR_ID_TYPE_R5900_NORMAL] = "R5900" "_" "NORMAL",
|
||||
[RAB_INSTR_ID_TYPE_R5900_SPECIAL] = "R5900" "_" "SPECIAL",
|
||||
|
||||
46
include/generated/InstrIdType_enum.h
generated
46
include/generated/InstrIdType_enum.h
generated
@ -40,6 +40,52 @@ typedef enum RabInstrIdType {
|
||||
RAB_INSTR_ID_TYPE_R3000GTE_COP1,
|
||||
RAB_INSTR_ID_TYPE_R3000GTE_COP2,
|
||||
RAB_INSTR_ID_TYPE_R3000GTE_COP2_GTE,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_INVALID,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_NORMAL,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL_RS,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL_SA,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_REGIMM,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL3,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_SPECIAL3_BSHFL,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0_BC0,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP0_TLB,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_BC1,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUS,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUW,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_BC2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2_P,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MFHC2_P_S,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP2_MTHC2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU0,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU1,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU3,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT0,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT3,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_RND,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CVTFLT,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CVTINT,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT8,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_FMT9,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CONTROL,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_COLOR,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT0_CST,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT2,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU4_FMT2_CNDMOVE,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU5,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6_FMT7,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU6_FMT7_FMT0,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_VFPU7,
|
||||
RAB_INSTR_ID_TYPE_R4000ALLEGREX_QUADLR,
|
||||
RAB_INSTR_ID_TYPE_R5900_INVALID,
|
||||
RAB_INSTR_ID_TYPE_R5900_NORMAL,
|
||||
RAB_INSTR_ID_TYPE_R5900_SPECIAL,
|
||||
|
||||
314
include/generated/InstrId_Names_array.h
generated
314
include/generated/InstrId_Names_array.h
generated
@ -460,6 +460,320 @@ const char *RabbitizerInstrId_Names[] = {
|
||||
[RABBITIZER_INSTR_ID_r3000gte_USERDEF_18] = "USERDEF_18",
|
||||
[RABBITIZER_INSTR_ID_r3000gte_USERDEF_19] = "USERDEF_19",
|
||||
[RABBITIZER_INSTR_ID_r3000gte_MAX] = "MAX",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_INVALID] = "INVALID",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_lv_s] = "lv.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_sv_s] = "sv.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_lv_q] = "lv.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_sv_q] = "sv.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_clz] = "clz",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_clo] = "clo",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_madd] = "madd",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_maddu] = "maddu",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_msub] = "msub",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_msubu] = "msubu",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_max] = "max",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_min] = "min",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_srl] = "srl",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_rotr] = "rotr",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_srlv] = "srlv",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_rotrv] = "rotrv",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_sleep] = "sleep",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mfie] = "mfie",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mtie] = "mtie",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_ext] = "ext",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_ins] = "ins",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_wsbh] = "wsbh",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_wsbw] = "wsbw",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_seb] = "seb",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_seh] = "seh",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bitrev] = "bitrev",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvf] = "bvf",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvt] = "bvt",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvfl] = "bvfl",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_bvtl] = "bvtl",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mfv] = "mfv",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mfvc] = "mfvc",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsync2] = "vsync2",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mtv] = "mtv",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_mtvc] = "mtvc",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_s] = "vadd.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_p] = "vadd.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_t] = "vadd.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vadd_q] = "vadd.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_s] = "vsub.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_p] = "vsub.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_t] = "vsub.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsub_q] = "vsub.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsbn_s] = "vsbn.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_s] = "vdiv.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_p] = "vdiv.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_t] = "vdiv.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdiv_q] = "vdiv.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_s] = "vmul.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_p] = "vmul.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_t] = "vmul.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmul_q] = "vmul.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdot_p] = "vdot.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdot_t] = "vdot.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdot_q] = "vdot.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscl_p] = "vscl.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscl_t] = "vscl.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscl_q] = "vscl.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhdp_p] = "vhdp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhdp_t] = "vhdp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhdp_q] = "vhdp.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcrs_t] = "vcrs.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vdet_p] = "vdet.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_s] = "vcmp.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_p] = "vcmp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_t] = "vcmp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmp_q] = "vcmp.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_s] = "vmin.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_p] = "vmin.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_t] = "vmin.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmin_q] = "vmin.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_s] = "vmax.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_p] = "vmax.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_t] = "vmax.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmax_q] = "vmax.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_s] = "vscmp.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_p] = "vscmp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_t] = "vscmp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vscmp_q] = "vscmp.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_s] = "vsge.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_p] = "vsge.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_t] = "vsge.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsge_q] = "vsge.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_s] = "vslt.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_p] = "vslt.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_t] = "vslt.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vslt_q] = "vslt.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vwbn_s] = "vwbn.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_s] = "vmov.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_p] = "vmov.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_t] = "vmov.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmov_q] = "vmov.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_s] = "vabs.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_p] = "vabs.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_t] = "vabs.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vabs_q] = "vabs.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_s] = "vneg.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_p] = "vneg.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_t] = "vneg.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vneg_q] = "vneg.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vidt_p] = "vidt.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vidt_q] = "vidt.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_s] = "vsat0.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_p] = "vsat0.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_t] = "vsat0.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat0_q] = "vsat0.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_s] = "vsat1.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_p] = "vsat1.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_t] = "vsat1.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsat1_q] = "vsat1.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_s] = "vzero.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_p] = "vzero.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_t] = "vzero.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vzero_q] = "vzero.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_s] = "vone.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_p] = "vone.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_t] = "vone.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vone_q] = "vone.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_s] = "vrcp.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_p] = "vrcp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_t] = "vrcp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrcp_q] = "vrcp.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_s] = "vrsq.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_p] = "vrsq.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_t] = "vrsq.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrsq_q] = "vrsq.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_s] = "vsin.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_p] = "vsin.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_t] = "vsin.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsin_q] = "vsin.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_s] = "vcos.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_p] = "vcos.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_t] = "vcos.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcos_q] = "vcos.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_s] = "vexp2.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_p] = "vexp2.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_t] = "vexp2.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vexp2_q] = "vexp2.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_s] = "vlog2.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_p] = "vlog2.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_t] = "vlog2.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlog2_q] = "vlog2.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_s] = "vsqrt.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_p] = "vsqrt.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_t] = "vsqrt.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_q] = "vsqrt.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_s] = "vasin.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_p] = "vasin.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_t] = "vasin.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vasin_q] = "vasin.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_s] = "vnrcp.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_p] = "vnrcp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_t] = "vnrcp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_q] = "vnrcp.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_s] = "vnsin.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_p] = "vnsin.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_t] = "vnsin.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnsin_q] = "vnsin.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_s] = "vrexp2.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_p] = "vrexp2.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_t] = "vrexp2.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_q] = "vrexp2.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrnds_s] = "vrnds.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_s] = "vrndi.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_p] = "vrndi.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_t] = "vrndi.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndi_q] = "vrndi.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_s] = "vrndf1.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_p] = "vrndf1.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_t] = "vrndf1.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_q] = "vrndf1.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_s] = "vrndf2.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_p] = "vrndf2.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_t] = "vrndf2.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_q] = "vrndf2.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2h_p] = "vf2h.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2h_q] = "vf2h.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vh2f_s] = "vh2f.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vh2f_p] = "vh2f.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsbz_s] = "vsbz.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vlgb_s] = "vlgb.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vuc2ifs_s] = "vuc2ifs.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vc2i_s] = "vc2i.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vus2i_s] = "vus2i.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vus2i_p] = "vus2i.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vs2i_s] = "vs2i.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vs2i_p] = "vs2i.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2uc_q] = "vi2uc.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2c_q] = "vi2c.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2us_p] = "vi2us.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2us_q] = "vi2us.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2s_p] = "vi2s.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2s_q] = "vi2s.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt1_q] = "vsrt1.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt2_q] = "vsrt2.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vbfy1_p] = "vbfy1.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vbfy1_q] = "vbfy1.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vbfy2_q] = "vbfy2.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_s] = "vocp.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_p] = "vocp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_t] = "vocp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vocp_q] = "vocp.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsocp_s] = "vsocp.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsocp_p] = "vsocp.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfad_p] = "vfad.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfad_t] = "vfad.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfad_q] = "vfad.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vavg_p] = "vavg.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vavg_t] = "vavg.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vavg_q] = "vavg.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt3_q] = "vsrt3.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsrt4_q] = "vsrt4.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_s] = "vsgn.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_p] = "vsgn.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_t] = "vsgn.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsgn_q] = "vsgn.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmfvc] = "vmfvc",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmtvc] = "vmtvc",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vt4444_q] = "vt4444.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vt5551_q] = "vt5551.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vt5650_q] = "vt5650.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_s] = "vcst.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_p] = "vcst.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_t] = "vcst.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcst_q] = "vcst.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_s] = "vf2in.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_p] = "vf2in.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_t] = "vf2in.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2in_q] = "vf2in.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_s] = "vf2iz.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_p] = "vf2iz.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_t] = "vf2iz.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_q] = "vf2iz.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_s] = "vf2iu.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_p] = "vf2iu.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_t] = "vf2iu.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_q] = "vf2iu.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_s] = "vf2id.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_p] = "vf2id.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_t] = "vf2id.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vf2id_q] = "vf2id.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_s] = "vi2f.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_p] = "vi2f.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_t] = "vi2f.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vi2f_q] = "vi2f.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_s] = "vcmovt.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_p] = "vcmovt.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_t] = "vcmovt.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_q] = "vcmovt.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_s] = "vcmovf.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_p] = "vcmovf.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_t] = "vcmovf.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_q] = "vcmovf.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vpfxs] = "vpfxs",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vpfxt] = "vpfxt",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vpfxd] = "vpfxd",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_viim_s] = "viim.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vfim_s] = "vfim.s",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmul_p] = "vmmul.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmul_t] = "vmmul.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmul_q] = "vmmul.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhtfm2_p] = "vhtfm2.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vtfm2_p] = "vtfm2.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhtfm3_t] = "vhtfm3.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vtfm3_t] = "vtfm3.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vhtfm4_q] = "vhtfm4.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vtfm4_q] = "vtfm4.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmscl_p] = "vmscl.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmscl_t] = "vmscl.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmscl_q] = "vmscl.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vcrsp_t] = "vcrsp.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vqmul_q] = "vqmul.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrot_p] = "vrot.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrot_t] = "vrot.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vrot_q] = "vrot.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmov_p] = "vmmov.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmov_t] = "vmmov.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmmov_q] = "vmmov.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmidt_p] = "vmidt.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmidt_t] = "vmidt.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmidt_q] = "vmidt.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmzero_p] = "vmzero.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmzero_t] = "vmzero.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmzero_q] = "vmzero.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmone_p] = "vmone.p",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmone_t] = "vmone.t",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vmone_q] = "vmone.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vnop] = "vnop",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vsync] = "vsync",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_vflush] = "vflush",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_svl_q] = "svl.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_svr_q] = "svr.q",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_00] = "USERDEF_00",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_01] = "USERDEF_01",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_02] = "USERDEF_02",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_03] = "USERDEF_03",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_04] = "USERDEF_04",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_05] = "USERDEF_05",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_06] = "USERDEF_06",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_07] = "USERDEF_07",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_08] = "USERDEF_08",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_09] = "USERDEF_09",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_10] = "USERDEF_10",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_11] = "USERDEF_11",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_12] = "USERDEF_12",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_13] = "USERDEF_13",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_14] = "USERDEF_14",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_15] = "USERDEF_15",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_16] = "USERDEF_16",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_17] = "USERDEF_17",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_18] = "USERDEF_18",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_19] = "USERDEF_19",
|
||||
[RABBITIZER_INSTR_ID_r4000allegrex_MAX] = "MAX",
|
||||
[RABBITIZER_INSTR_ID_r5900_INVALID] = "INVALID",
|
||||
[RABBITIZER_INSTR_ID_r5900_lq] = "lq",
|
||||
[RABBITIZER_INSTR_ID_r5900_sq] = "sq",
|
||||
|
||||
317
include/generated/InstrId_enum.h
generated
317
include/generated/InstrId_enum.h
generated
@ -460,6 +460,320 @@ typedef enum RabbitizerInstrId {
|
||||
RABBITIZER_INSTR_ID_r3000gte_USERDEF_18,
|
||||
RABBITIZER_INSTR_ID_r3000gte_USERDEF_19,
|
||||
RABBITIZER_INSTR_ID_r3000gte_MAX,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_INVALID,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_lv_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_sv_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_lv_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_sv_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_clz,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_clo,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_madd,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_maddu,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_msub,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_msubu,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_max,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_min,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_srl,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_rotr,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_srlv,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_rotrv,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_sleep,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_mfie,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_mtie,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_ext,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_ins,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_wsbh,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_wsbw,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_seb,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_seh,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_bitrev,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_bvf,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_bvt,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_bvfl,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_bvtl,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_mfv,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_mfvc,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsync2,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_mtv,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_mtvc,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vadd_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vadd_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vadd_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vadd_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsub_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsub_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsub_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsub_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsbn_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdiv_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdiv_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdiv_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdiv_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmul_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmul_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmul_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmul_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdot_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdot_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdot_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscl_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscl_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscl_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vhdp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vhdp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vhdp_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcrs_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vdet_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmp_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmp_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmin_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmin_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmin_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmin_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmax_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmax_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmax_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmax_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscmp_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscmp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscmp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vscmp_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsge_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsge_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsge_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsge_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vslt_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vslt_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vslt_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vslt_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vwbn_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmov_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmov_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmov_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmov_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vabs_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vabs_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vabs_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vabs_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vneg_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vneg_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vneg_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vneg_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vidt_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vidt_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat0_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat0_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat0_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat0_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat1_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat1_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat1_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsat1_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vzero_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vzero_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vzero_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vzero_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vone_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vone_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vone_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vone_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrcp_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrcp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrcp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrcp_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrsq_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrsq_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrsq_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrsq_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsin_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsin_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsin_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsin_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcos_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcos_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcos_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcos_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vexp2_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vexp2_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vexp2_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vexp2_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vlog2_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vlog2_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vlog2_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vlog2_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsqrt_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vasin_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vasin_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vasin_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vasin_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnrcp_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnsin_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnsin_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnsin_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnsin_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrexp2_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrnds_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndi_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndi_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndi_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndi_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf1_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrndf2_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2h_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2h_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vh2f_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vh2f_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsbz_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vlgb_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vuc2ifs_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vc2i_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vus2i_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vus2i_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vs2i_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vs2i_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2uc_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2c_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2us_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2us_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2s_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2s_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsrt1_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsrt2_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vbfy1_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vbfy1_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vbfy2_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vocp_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vocp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vocp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vocp_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsocp_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsocp_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vfad_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vfad_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vfad_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vavg_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vavg_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vavg_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsrt3_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsrt4_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsgn_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsgn_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsgn_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsgn_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmfvc,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmtvc,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vt4444_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vt5551_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vt5650_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcst_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcst_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcst_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcst_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2in_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2in_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2in_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2in_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iz_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2iu_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2id_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2id_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2id_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vf2id_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2f_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2f_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2f_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vi2f_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovt_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcmovf_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vpfxs,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vpfxt,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vpfxd,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_viim_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vfim_s,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmmul_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmmul_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmmul_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vhtfm2_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vtfm2_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vhtfm3_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vtfm3_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vhtfm4_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vtfm4_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmscl_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmscl_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmscl_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vcrsp_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vqmul_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrot_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrot_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vrot_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmmov_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmmov_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmmov_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmidt_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmidt_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmidt_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmzero_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmzero_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmzero_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmone_p,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmone_t,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vmone_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vnop,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vsync,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_vflush,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_svl_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_svr_q,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_00,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_01,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_02,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_03,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_04,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_05,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_06,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_07,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_08,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_09,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_10,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_11,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_12,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_13,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_14,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_15,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_16,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_17,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_18,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_USERDEF_19,
|
||||
RABBITIZER_INSTR_ID_r4000allegrex_MAX,
|
||||
RABBITIZER_INSTR_ID_r5900_INVALID,
|
||||
RABBITIZER_INSTR_ID_r5900_lq,
|
||||
RABBITIZER_INSTR_ID_r5900_sq,
|
||||
@ -734,7 +1048,8 @@ typedef enum RabbitizerInstrId {
|
||||
RABBITIZER_INSTR_ID_r5900_USERDEF_18,
|
||||
RABBITIZER_INSTR_ID_r5900_USERDEF_19,
|
||||
RABBITIZER_INSTR_ID_r5900_MAX,
|
||||
RABBITIZER_INSTR_ID_ALL_MAX = RABBITIZER_INSTR_ID_r5900_MAX,
|
||||
RABBITIZER_INSTR_ID_ALL_LAST,
|
||||
RABBITIZER_INSTR_ID_ALL_MAX = RABBITIZER_INSTR_ID_ALL_LAST - 1
|
||||
} RabbitizerInstrId;
|
||||
|
||||
#endif
|
||||
|
||||
57
include/generated/OperandType_enum.h
generated
57
include/generated/OperandType_enum.h
generated
@ -52,6 +52,63 @@ typedef enum RabbitizerOperandType {
|
||||
RAB_OPERAND_r3000gte_v,
|
||||
RAB_OPERAND_r3000gte_cv,
|
||||
RAB_OPERAND_r3000gte_lm,
|
||||
RAB_OPERAND_r4000allegrex_s_vs,
|
||||
RAB_OPERAND_r4000allegrex_s_vt,
|
||||
RAB_OPERAND_r4000allegrex_s_vd,
|
||||
RAB_OPERAND_r4000allegrex_s_vt_imm,
|
||||
RAB_OPERAND_r4000allegrex_s_vd_imm,
|
||||
RAB_OPERAND_r4000allegrex_p_vs,
|
||||
RAB_OPERAND_r4000allegrex_p_vt,
|
||||
RAB_OPERAND_r4000allegrex_p_vd,
|
||||
RAB_OPERAND_r4000allegrex_t_vs,
|
||||
RAB_OPERAND_r4000allegrex_t_vt,
|
||||
RAB_OPERAND_r4000allegrex_t_vd,
|
||||
RAB_OPERAND_r4000allegrex_q_vs,
|
||||
RAB_OPERAND_r4000allegrex_q_vt,
|
||||
RAB_OPERAND_r4000allegrex_q_vd,
|
||||
RAB_OPERAND_r4000allegrex_q_vt_imm,
|
||||
RAB_OPERAND_r4000allegrex_mp_vs,
|
||||
RAB_OPERAND_r4000allegrex_mp_vt,
|
||||
RAB_OPERAND_r4000allegrex_mp_vd,
|
||||
RAB_OPERAND_r4000allegrex_mp_vs_transpose,
|
||||
RAB_OPERAND_r4000allegrex_mt_vs,
|
||||
RAB_OPERAND_r4000allegrex_mt_vt,
|
||||
RAB_OPERAND_r4000allegrex_mt_vd,
|
||||
RAB_OPERAND_r4000allegrex_mt_vs_transpose,
|
||||
RAB_OPERAND_r4000allegrex_mq_vs,
|
||||
RAB_OPERAND_r4000allegrex_mq_vt,
|
||||
RAB_OPERAND_r4000allegrex_mq_vd,
|
||||
RAB_OPERAND_r4000allegrex_mq_vs_transpose,
|
||||
RAB_OPERAND_r4000allegrex_cop2cs,
|
||||
RAB_OPERAND_r4000allegrex_cop2cd,
|
||||
RAB_OPERAND_r4000allegrex_pos,
|
||||
RAB_OPERAND_r4000allegrex_size,
|
||||
RAB_OPERAND_r4000allegrex_size_plus_pos,
|
||||
RAB_OPERAND_r4000allegrex_imm3,
|
||||
RAB_OPERAND_r4000allegrex_offset14_base,
|
||||
RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt,
|
||||
RAB_OPERAND_r4000allegrex_vconstant,
|
||||
RAB_OPERAND_r4000allegrex_power_of_two,
|
||||
RAB_OPERAND_r4000allegrex_vfpu_cc_bit,
|
||||
RAB_OPERAND_r4000allegrex_bn,
|
||||
RAB_OPERAND_r4000allegrex_int16,
|
||||
RAB_OPERAND_r4000allegrex_float16,
|
||||
RAB_OPERAND_r4000allegrex_p_vrot_code,
|
||||
RAB_OPERAND_r4000allegrex_t_vrot_code,
|
||||
RAB_OPERAND_r4000allegrex_q_vrot_code,
|
||||
RAB_OPERAND_r4000allegrex_rpx,
|
||||
RAB_OPERAND_r4000allegrex_rpy,
|
||||
RAB_OPERAND_r4000allegrex_rpz,
|
||||
RAB_OPERAND_r4000allegrex_rpw,
|
||||
RAB_OPERAND_r4000allegrex_wpx,
|
||||
RAB_OPERAND_r4000allegrex_wpy,
|
||||
RAB_OPERAND_r4000allegrex_wpz,
|
||||
RAB_OPERAND_r4000allegrex_wpw,
|
||||
RAB_OPERAND_r5900_I,
|
||||
RAB_OPERAND_r5900_Q,
|
||||
RAB_OPERAND_r5900_R,
|
||||
|
||||
@ -50,6 +50,63 @@
|
||||
size_t RabbitizerOperandType_process_r3000gte_v (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r3000gte_cv (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r3000gte_lm (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_s_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_s_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_s_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_s_vt_imm (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_s_vd_imm (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_p_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_p_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_p_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_t_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_t_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_t_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_q_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_q_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_q_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_q_vt_imm (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mp_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mp_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mp_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mp_vs_transpose (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mt_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mt_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mt_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mt_vs_transpose (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mq_vs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mq_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mq_vd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_mq_vs_transpose (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_cop2cs (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_cop2cd (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_pos (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_size (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_size_plus_pos (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_imm3 (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_offset14_base (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_offset14_base_maybe_wb (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vcmp_cond (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vconstant (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_power_of_two (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_vfpu_cc_bit (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_bn (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_int16 (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_float16 (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_p_vrot_code (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_t_vrot_code (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_q_vrot_code (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_rpx (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_rpy (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_rpz (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_rpw (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_wpx (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_wpy (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_wpz (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r4000allegrex_wpw (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r5900_I (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r5900_Q (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
size_t RabbitizerOperandType_process_r5900_R (const struct RabbitizerInstruction *self, char *dst, const char *immOverride, size_t immOverrideLength);
|
||||
|
||||
1074
include/generated/RegisterDescriptor_Descriptors_arrays.h
generated
1074
include/generated/RegisterDescriptor_Descriptors_arrays.h
generated
File diff suppressed because it is too large
Load Diff
1074
include/generated/Registers_Names_arrays.h
generated
1074
include/generated/Registers_Names_arrays.h
generated
File diff suppressed because it is too large
Load Diff
1074
include/generated/Registers_enums.h
generated
1074
include/generated/Registers_enums.h
generated
File diff suppressed because it is too large
Load Diff
57
include/generated/instrOpercandCallbacks_array.h
generated
57
include/generated/instrOpercandCallbacks_array.h
generated
@ -51,6 +51,63 @@ const OperandCallback instrOpercandCallbacks[] = {
|
||||
[RAB_OPERAND_r3000gte_v] = RabbitizerOperandType_process_r3000gte_v,
|
||||
[RAB_OPERAND_r3000gte_cv] = RabbitizerOperandType_process_r3000gte_cv,
|
||||
[RAB_OPERAND_r3000gte_lm] = RabbitizerOperandType_process_r3000gte_lm,
|
||||
[RAB_OPERAND_r4000allegrex_s_vs] = RabbitizerOperandType_process_r4000allegrex_s_vs,
|
||||
[RAB_OPERAND_r4000allegrex_s_vt] = RabbitizerOperandType_process_r4000allegrex_s_vt,
|
||||
[RAB_OPERAND_r4000allegrex_s_vd] = RabbitizerOperandType_process_r4000allegrex_s_vd,
|
||||
[RAB_OPERAND_r4000allegrex_s_vt_imm] = RabbitizerOperandType_process_r4000allegrex_s_vt_imm,
|
||||
[RAB_OPERAND_r4000allegrex_s_vd_imm] = RabbitizerOperandType_process_r4000allegrex_s_vd_imm,
|
||||
[RAB_OPERAND_r4000allegrex_p_vs] = RabbitizerOperandType_process_r4000allegrex_p_vs,
|
||||
[RAB_OPERAND_r4000allegrex_p_vt] = RabbitizerOperandType_process_r4000allegrex_p_vt,
|
||||
[RAB_OPERAND_r4000allegrex_p_vd] = RabbitizerOperandType_process_r4000allegrex_p_vd,
|
||||
[RAB_OPERAND_r4000allegrex_t_vs] = RabbitizerOperandType_process_r4000allegrex_t_vs,
|
||||
[RAB_OPERAND_r4000allegrex_t_vt] = RabbitizerOperandType_process_r4000allegrex_t_vt,
|
||||
[RAB_OPERAND_r4000allegrex_t_vd] = RabbitizerOperandType_process_r4000allegrex_t_vd,
|
||||
[RAB_OPERAND_r4000allegrex_q_vs] = RabbitizerOperandType_process_r4000allegrex_q_vs,
|
||||
[RAB_OPERAND_r4000allegrex_q_vt] = RabbitizerOperandType_process_r4000allegrex_q_vt,
|
||||
[RAB_OPERAND_r4000allegrex_q_vd] = RabbitizerOperandType_process_r4000allegrex_q_vd,
|
||||
[RAB_OPERAND_r4000allegrex_q_vt_imm] = RabbitizerOperandType_process_r4000allegrex_q_vt_imm,
|
||||
[RAB_OPERAND_r4000allegrex_mp_vs] = RabbitizerOperandType_process_r4000allegrex_mp_vs,
|
||||
[RAB_OPERAND_r4000allegrex_mp_vt] = RabbitizerOperandType_process_r4000allegrex_mp_vt,
|
||||
[RAB_OPERAND_r4000allegrex_mp_vd] = RabbitizerOperandType_process_r4000allegrex_mp_vd,
|
||||
[RAB_OPERAND_r4000allegrex_mp_vs_transpose] = RabbitizerOperandType_process_r4000allegrex_mp_vs_transpose,
|
||||
[RAB_OPERAND_r4000allegrex_mt_vs] = RabbitizerOperandType_process_r4000allegrex_mt_vs,
|
||||
[RAB_OPERAND_r4000allegrex_mt_vt] = RabbitizerOperandType_process_r4000allegrex_mt_vt,
|
||||
[RAB_OPERAND_r4000allegrex_mt_vd] = RabbitizerOperandType_process_r4000allegrex_mt_vd,
|
||||
[RAB_OPERAND_r4000allegrex_mt_vs_transpose] = RabbitizerOperandType_process_r4000allegrex_mt_vs_transpose,
|
||||
[RAB_OPERAND_r4000allegrex_mq_vs] = RabbitizerOperandType_process_r4000allegrex_mq_vs,
|
||||
[RAB_OPERAND_r4000allegrex_mq_vt] = RabbitizerOperandType_process_r4000allegrex_mq_vt,
|
||||
[RAB_OPERAND_r4000allegrex_mq_vd] = RabbitizerOperandType_process_r4000allegrex_mq_vd,
|
||||
[RAB_OPERAND_r4000allegrex_mq_vs_transpose] = RabbitizerOperandType_process_r4000allegrex_mq_vs_transpose,
|
||||
[RAB_OPERAND_r4000allegrex_cop2cs] = RabbitizerOperandType_process_r4000allegrex_cop2cs,
|
||||
[RAB_OPERAND_r4000allegrex_cop2cd] = RabbitizerOperandType_process_r4000allegrex_cop2cd,
|
||||
[RAB_OPERAND_r4000allegrex_pos] = RabbitizerOperandType_process_r4000allegrex_pos,
|
||||
[RAB_OPERAND_r4000allegrex_size] = RabbitizerOperandType_process_r4000allegrex_size,
|
||||
[RAB_OPERAND_r4000allegrex_size_plus_pos] = RabbitizerOperandType_process_r4000allegrex_size_plus_pos,
|
||||
[RAB_OPERAND_r4000allegrex_imm3] = RabbitizerOperandType_process_r4000allegrex_imm3,
|
||||
[RAB_OPERAND_r4000allegrex_offset14_base] = RabbitizerOperandType_process_r4000allegrex_offset14_base,
|
||||
[RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb] = RabbitizerOperandType_process_r4000allegrex_offset14_base_maybe_wb,
|
||||
[RAB_OPERAND_r4000allegrex_vcmp_cond] = RabbitizerOperandType_process_r4000allegrex_vcmp_cond,
|
||||
[RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt] = RabbitizerOperandType_process_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt,
|
||||
[RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt] = RabbitizerOperandType_process_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt,
|
||||
[RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt] = RabbitizerOperandType_process_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt,
|
||||
[RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt] = RabbitizerOperandType_process_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt,
|
||||
[RAB_OPERAND_r4000allegrex_vconstant] = RabbitizerOperandType_process_r4000allegrex_vconstant,
|
||||
[RAB_OPERAND_r4000allegrex_power_of_two] = RabbitizerOperandType_process_r4000allegrex_power_of_two,
|
||||
[RAB_OPERAND_r4000allegrex_vfpu_cc_bit] = RabbitizerOperandType_process_r4000allegrex_vfpu_cc_bit,
|
||||
[RAB_OPERAND_r4000allegrex_bn] = RabbitizerOperandType_process_r4000allegrex_bn,
|
||||
[RAB_OPERAND_r4000allegrex_int16] = RabbitizerOperandType_process_r4000allegrex_int16,
|
||||
[RAB_OPERAND_r4000allegrex_float16] = RabbitizerOperandType_process_r4000allegrex_float16,
|
||||
[RAB_OPERAND_r4000allegrex_p_vrot_code] = RabbitizerOperandType_process_r4000allegrex_p_vrot_code,
|
||||
[RAB_OPERAND_r4000allegrex_t_vrot_code] = RabbitizerOperandType_process_r4000allegrex_t_vrot_code,
|
||||
[RAB_OPERAND_r4000allegrex_q_vrot_code] = RabbitizerOperandType_process_r4000allegrex_q_vrot_code,
|
||||
[RAB_OPERAND_r4000allegrex_rpx] = RabbitizerOperandType_process_r4000allegrex_rpx,
|
||||
[RAB_OPERAND_r4000allegrex_rpy] = RabbitizerOperandType_process_r4000allegrex_rpy,
|
||||
[RAB_OPERAND_r4000allegrex_rpz] = RabbitizerOperandType_process_r4000allegrex_rpz,
|
||||
[RAB_OPERAND_r4000allegrex_rpw] = RabbitizerOperandType_process_r4000allegrex_rpw,
|
||||
[RAB_OPERAND_r4000allegrex_wpx] = RabbitizerOperandType_process_r4000allegrex_wpx,
|
||||
[RAB_OPERAND_r4000allegrex_wpy] = RabbitizerOperandType_process_r4000allegrex_wpy,
|
||||
[RAB_OPERAND_r4000allegrex_wpz] = RabbitizerOperandType_process_r4000allegrex_wpz,
|
||||
[RAB_OPERAND_r4000allegrex_wpw] = RabbitizerOperandType_process_r4000allegrex_wpw,
|
||||
[RAB_OPERAND_r5900_I] = RabbitizerOperandType_process_r5900_I,
|
||||
[RAB_OPERAND_r5900_Q] = RabbitizerOperandType_process_r5900_Q,
|
||||
[RAB_OPERAND_r5900_R] = RabbitizerOperandType_process_r5900_R,
|
||||
|
||||
248
include/instructions/RabbitizerInstructionR4000Allegrex.h
Normal file
248
include/instructions/RabbitizerInstructionR4000Allegrex.h
Normal file
@ -0,0 +1,248 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
#ifndef RABBITIZER_INSTRUCTION_R4000ALLEGREX_H
|
||||
#define RABBITIZER_INSTRUCTION_R4000ALLEGREX_H
|
||||
#pragma once
|
||||
|
||||
#include "RabbitizerInstruction.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vt(self) (SHIFTR((self)->word, 16, 7))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vs(self) (SHIFTR((self)->word, 8, 7))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vd(self) (SHIFTR((self)->word, 0, 7))
|
||||
// For whatever reason the transpose just toggles bit 5, no clue why.
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vs_transpose(self) (SHIFTR((self)->word, 8, 7) ^ 0x20)
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vt_imm(self) ((SHIFTR((self)->word, 0, 2) << 5) | (SHIFTR((self)->word, 16, 5)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vd_imm(self) (SHIFTR((self)->word, 16, 7))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vt_6_imm(self) ((SHIFTR((self)->word, 0, 1) << 5) | (SHIFTR((self)->word, 16, 5)))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_cop2cs(self) (SHIFTR((self)->word, 8, 7))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_cop2cd(self) (SHIFTR((self)->word, 0, 7))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_pos(self) (SHIFTR((self)->word, 6, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_size(self) (SHIFTR((self)->word, 11, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_size_plus_pos(self) (SHIFTR((self)->word, 11, 5))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_bc2_fmt(self) (SHIFTR((self)->word, 16, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_mxhc2(self) (SHIFTR((self)->word, 7, 1))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_mfhc2_p_fmt(self) (SHIFTR((self)->word, 4, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_mfhc2_p_s_fmt(self) (SHIFTR((self)->word, 0, 4))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_imm3(self) (SHIFTR((self)->word, 18, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_offset14(self) (SHIFTR((self)->word, 2, 14))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_wb(self) (SHIFTR((self)->word, 1, 1))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_tp(self) ((SHIFTR((self)->word, 15, 1) << 1) | (SHIFTR((self)->word, 7, 1)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu0_fmt(self) ((SHIFTR((self)->word, 23, 3) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu4_fmt(self) ((SHIFTR((self)->word, 24, 2) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu4_fmt0_fmt(self) (SHIFTR((self)->word, 19, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu4_fmt0_fmt0_fmt(self) ((SHIFTR((self)->word, 16, 3) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu4_fmt2_fmt(self) ((SHIFTR((self)->word, 21, 3) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu4_fmt2_cndmove_fmt(self) ((SHIFTR((self)->word, 19, 2) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu5_fmt(self) (SHIFTR((self)->word, 23, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu6_fmt(self) ((SHIFTR((self)->word, 23, 3) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu6_fmt7_fmt(self) ((SHIFTR((self)->word, 21, 2) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu6_fmt7_fmt0_fmt(self) ((SHIFTR((self)->word, 16, 3) << 2) | RAB_INSTR_R4000ALLEGREX_GET_tp(self))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu7_fmt(self) (SHIFTR((self)->word, 0, 26))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vcmp_cond(self) (SHIFTR((self)->word, 0, 4))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vconstant(self) (SHIFTR((self)->word, 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_power_of_two(self) (SHIFTR((self)->word, 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vfpu_cc_bit(self) (SHIFTR((self)->word, 16, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_bn(self) (SHIFTR((self)->word, 16, 8))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_intfloat16(self) (SHIFTR((self)->word, 0, 16))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_vrot_code(self) (SHIFTR((self)->word, 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_rpx(self) ((SHIFTR((self)->word, 16, 1) << 4) | (SHIFTR((self)->word, 12, 1) << 3) | (SHIFTR((self)->word, 8, 1) << 2) | (SHIFTR((self)->word, 0, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_rpy(self) ((SHIFTR((self)->word, 17, 1) << 4) | (SHIFTR((self)->word, 13, 1) << 3) | (SHIFTR((self)->word, 9, 1) << 2) | (SHIFTR((self)->word, 2, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_rpz(self) ((SHIFTR((self)->word, 18, 1) << 4) | (SHIFTR((self)->word, 14, 1) << 3) | (SHIFTR((self)->word, 10, 1) << 2) | (SHIFTR((self)->word, 4, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_rpw(self) ((SHIFTR((self)->word, 19, 1) << 4) | (SHIFTR((self)->word, 15, 1) << 3) | (SHIFTR((self)->word, 11, 1) << 2) | (SHIFTR((self)->word, 6, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_wpx(self) ((SHIFTR((self)->word, 8, 1) << 2) | (SHIFTR((self)->word, 0, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_wpy(self) ((SHIFTR((self)->word, 9, 1) << 2) | (SHIFTR((self)->word, 2, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_wpz(self) ((SHIFTR((self)->word, 10, 1) << 2) | (SHIFTR((self)->word, 4, 2) << 0))
|
||||
#define RAB_INSTR_R4000ALLEGREX_GET_wpw(self) ((SHIFTR((self)->word, 11, 1) << 2) | (SHIFTR((self)->word, 6, 2) << 0))
|
||||
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vt(word, value) (BITREPACK((word), (value), 16, 7))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vs(word, value) (BITREPACK((word), (value), 8, 7))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vd(word, value) (BITREPACK((word), (value), 0, 7))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vt_imm(word, value) (BITREPACK(BITREPACK((word), (value) >> 5, 0, 2), (value), 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vd_imm(word, value) (BITREPACK((word), (value), 16, 7))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vt_6_imm(word, value) (BITREPACK(BITREPACK((word), (value) >> 5, 0, 1), (value), 16, 5))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_cop2cs(word, value) (BITREPACK((word), (value), 8, 7))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_cop2cd(word, value) (BITREPACK((word), (value), 0, 7))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_pos(word, value) (BITREPACK((word), (value), 6, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_size(word, value) (BITREPACK((word), (value), 11, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_size_plus_pos(word, value) (BITREPACK((word), (value), 11, 5))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_bc2_fmt(word, value) (BITREPACK((word), (value), 16, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_mxhc2(word, value) (BITREPACK((word), (value), 7, 1))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_mfhc2_p_fmt(word, value) (BITREPACK((word), (value), 4, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_mfhc2_p_s_fmt(word, value) (BITREPACK((word), (value), 0, 4))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_imm3(word, value) (BITREPACK((word), (value), 18, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_offset14(word, value) (BITREPACK((word), (value), 2, 14))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_wb(word, value) (BITREPACK((word), (value), 1, 1))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_tp(word, value) (BITREPACK(BITREPACK((word), (value) >> 1, 15, 1), (value), 7, 1))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu0_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 23, 3), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu4_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 24, 2), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu4_fmt0_fmt(word, value) (BITREPACK((word), (value), 19, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu4_fmt0_fmt0_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 16, 3), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu4_fmt2_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 21, 3), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu4_fmt2_cndmove_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 19, 2), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu5_fmt(word, value) (BITREPACK((word), (value), 23, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu6_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 23, 3), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu6_fmt7_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 21, 2), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu6_fmt7_fmt0_fmt(word, value) (RAB_INSTR_R4000ALLEGREX_PACK_tp(BITREPACK((word), (value) >> 2, 16, 3), (value)))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu7_fmt(word, value) (BITREPACK((word), (value), 0, 26))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vcmp_cond(word, value) (BITREPACK((word), (value), 0, 4))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vconstant(word, value) (BITREPACK((word), (value), 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_power_of_two(word, value) (BITREPACK((word), (value), 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vfpu_cc_bit(word, value) (BITREPACK((word), (value), 16, 3))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_bn(word, value) (BITREPACK((word), (value), 16, 8))
|
||||
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_intfloat16(word, value) (BITREPACK((word), (value), 0, 16))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_vrot_code(word, value) (BITREPACK((word), (value), 16, 5))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_rpx(word, value) (BITREPACK(BITREPACK(BITREPACK(BITREPACK((word), (value) >> 4, 16, 1), (value) >> 3, 12, 1), (value) >> 2, 8, 1), (value), 0, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_rpy(word, value) (BITREPACK(BITREPACK(BITREPACK(BITREPACK((word), (value) >> 4, 17, 1), (value) >> 3, 13, 1), (value) >> 2, 9, 1), (value), 2, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_rpz(word, value) (BITREPACK(BITREPACK(BITREPACK(BITREPACK((word), (value) >> 4, 18, 1), (value) >> 3, 14, 1), (value) >> 2, 10, 1), (value), 4, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_rpw(word, value) (BITREPACK(BITREPACK(BITREPACK(BITREPACK((word), (value) >> 4, 19, 1), (value) >> 3, 15, 1), (value) >> 2, 11, 1), (value), 6, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_wpx(word, value) (BITREPACK(BITREPACK((word), (value) >> 2, 8, 1), (value), 0, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_wpy(word, value) (BITREPACK(BITREPACK((word), (value) >> 2, 9, 1), (value), 2, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_wpz(word, value) (BITREPACK(BITREPACK((word), (value) >> 2, 10, 1), (value), 4, 2))
|
||||
#define RAB_INSTR_R4000ALLEGREX_PACK_wpw(word, value) (BITREPACK(BITREPACK((word), (value) >> 2, 11, 1), (value), 6, 2))
|
||||
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_init(RabbitizerInstruction *self, uint32_t word, uint32_t vram);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_destroy(RabbitizerInstruction *self);
|
||||
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Normal(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Special(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Special_Rs(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Special_Sa(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Regimm(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Special2(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Special3(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Special3_Bshfl(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor0(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor0_BC0(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor0_Tlb(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_BC1(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuS(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuW(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2_BC2(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2_MFHC2(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2_MFHC2_p(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2_MFHC2_p_s(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2_MTHC2(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu0(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu1(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu3(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Fmt0(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Fmt2(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Fmt3(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Rnd(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_CvtFlt(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_CvtInt(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Fmt8(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Fmt9(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Control(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Color(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt0_Cst(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt2(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu4_Fmt2_CndMove(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu5(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu6(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu6_Fmt7(RabbitizerInstruction *self);
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu6_Fmt7_Fmt0(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Vfpu7(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId_Quadlr(RabbitizerInstruction *self);
|
||||
|
||||
NON_NULL(1)
|
||||
void RabbitizerInstructionR4000Allegrex_processUniqueId(RabbitizerInstruction *self);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -31,6 +31,7 @@ extern const char *RabbitizerRegister_RspCop0_Names[][2];
|
||||
extern const char *RabbitizerRegister_RspCop2_Names[][2];
|
||||
extern const char *RabbitizerRegister_RspCop2Control_Names[][2];
|
||||
extern const char *RabbitizerRegister_RspVector_Names[][2];
|
||||
extern const char *RabbitizerRegister_R4000AllegrexS_Names[][2];
|
||||
extern const char *RabbitizerRegister_R5900VF_Names[][2];
|
||||
extern const char *RabbitizerRegister_R5900VI_Names[][2];
|
||||
|
||||
@ -57,6 +58,25 @@ const char *RabbitizerRegister_getNameRspCop2Control(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameRspVector(uint8_t regValue);
|
||||
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexS(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexV2D(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexV3D(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexV4D(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexM2x2(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexM3x3(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexM4x4(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexVfpuControl(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexVConstant(uint8_t regValue);
|
||||
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const char *RabbitizerRegister_getNameR5900VF(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
@ -86,6 +106,25 @@ const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_RspCop2Cont
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_RspVector(uint8_t regValue);
|
||||
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexS(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexV2D(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexV3D(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexV4D(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexM2x2(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexM3x3(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexM4x4(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexVfpuControl(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexVConstant(uint8_t regValue);
|
||||
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R5900VF(uint8_t regValue);
|
||||
NODISCARD PURE RETURNS_NON_NULL
|
||||
|
||||
@ -51,6 +51,20 @@ extern const RabbitizerRegisterDescriptor RabbitizerRegister_RspVector_Descripto
|
||||
|
||||
/* RSP */
|
||||
|
||||
/* R4000ALLEGREX */
|
||||
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexS_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexV2D_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexV3D_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexV4D_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexM2x2_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexM3x3_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexM4x4_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexVfpuControl_Descriptors[];
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R4000AllegrexVConstant_Descriptors[];
|
||||
|
||||
/* R4000ALLEGREX */
|
||||
|
||||
/* R5900 */
|
||||
|
||||
extern const RabbitizerRegisterDescriptor RabbitizerRegister_R5900VF_Descriptors[];
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#include "instructions/RabbitizerInstruction.h"
|
||||
#include "instructions/RabbitizerInstructionRsp.h"
|
||||
#include "instructions/RabbitizerInstructionR3000GTE.h"
|
||||
#include "instructions/RabbitizerInstructionR4000Allegrex.h"
|
||||
#include "instructions/RabbitizerInstructionR5900.h"
|
||||
|
||||
#include "analysis/RabbitizerTrackedRegisterState.h"
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
[project]
|
||||
name = "rabbitizer"
|
||||
# Version should be synced with include/common/RabbitizerVersion.h
|
||||
version = "1.9.6"
|
||||
version = "1.10.0"
|
||||
description = "MIPS instruction decoder"
|
||||
# license = "MIT"
|
||||
readme = "README.md"
|
||||
|
||||
@ -15,6 +15,7 @@ class _RabbitizerConfig:
|
||||
regNames_userFpcCsr: bool = True
|
||||
regNames_vr4300Cop0NamedRegisters: bool = True
|
||||
regNames_vr4300RspCop0NamedRegisters: bool = True
|
||||
regNames_r4000AllegrexVfpuControlNamedRegisters: bool = False
|
||||
|
||||
pseudos_enablePseudos: bool = True
|
||||
pseudos_pseudoBeqz: bool = True
|
||||
|
||||
1
rabbitizer/InstrCategory.pyi
generated
1
rabbitizer/InstrCategory.pyi
generated
@ -11,6 +11,7 @@ class InstrCategory:
|
||||
CPU: Enum
|
||||
RSP: Enum
|
||||
R3000GTE: Enum
|
||||
R4000ALLEGREX: Enum
|
||||
R5900: Enum
|
||||
MAX: Enum
|
||||
@staticmethod
|
||||
|
||||
294
rabbitizer/InstrId.pyi
generated
294
rabbitizer/InstrId.pyi
generated
@ -401,6 +401,300 @@ class InstrId:
|
||||
r3000gte_GPF: Enum
|
||||
r3000gte_GPL: Enum
|
||||
r3000gte_MAX: Enum
|
||||
r4000allegrex_INVALID: Enum
|
||||
r4000allegrex_lv_s: Enum
|
||||
r4000allegrex_sv_s: Enum
|
||||
r4000allegrex_lv_q: Enum
|
||||
r4000allegrex_sv_q: Enum
|
||||
r4000allegrex_clz: Enum
|
||||
r4000allegrex_clo: Enum
|
||||
r4000allegrex_madd: Enum
|
||||
r4000allegrex_maddu: Enum
|
||||
r4000allegrex_msub: Enum
|
||||
r4000allegrex_msubu: Enum
|
||||
r4000allegrex_max: Enum
|
||||
r4000allegrex_min: Enum
|
||||
r4000allegrex_srl: Enum
|
||||
r4000allegrex_rotr: Enum
|
||||
r4000allegrex_srlv: Enum
|
||||
r4000allegrex_rotrv: Enum
|
||||
r4000allegrex_sleep: Enum
|
||||
r4000allegrex_mfie: Enum
|
||||
r4000allegrex_mtie: Enum
|
||||
r4000allegrex_ext: Enum
|
||||
r4000allegrex_ins: Enum
|
||||
r4000allegrex_wsbh: Enum
|
||||
r4000allegrex_wsbw: Enum
|
||||
r4000allegrex_seb: Enum
|
||||
r4000allegrex_seh: Enum
|
||||
r4000allegrex_bitrev: Enum
|
||||
r4000allegrex_bvf: Enum
|
||||
r4000allegrex_bvt: Enum
|
||||
r4000allegrex_bvfl: Enum
|
||||
r4000allegrex_bvtl: Enum
|
||||
r4000allegrex_mfv: Enum
|
||||
r4000allegrex_mfvc: Enum
|
||||
r4000allegrex_vsync2: Enum
|
||||
r4000allegrex_mtv: Enum
|
||||
r4000allegrex_mtvc: Enum
|
||||
r4000allegrex_vadd_s: Enum
|
||||
r4000allegrex_vadd_p: Enum
|
||||
r4000allegrex_vadd_t: Enum
|
||||
r4000allegrex_vadd_q: Enum
|
||||
r4000allegrex_vsub_s: Enum
|
||||
r4000allegrex_vsub_p: Enum
|
||||
r4000allegrex_vsub_t: Enum
|
||||
r4000allegrex_vsub_q: Enum
|
||||
r4000allegrex_vsbn_s: Enum
|
||||
r4000allegrex_vdiv_s: Enum
|
||||
r4000allegrex_vdiv_p: Enum
|
||||
r4000allegrex_vdiv_t: Enum
|
||||
r4000allegrex_vdiv_q: Enum
|
||||
r4000allegrex_vmul_s: Enum
|
||||
r4000allegrex_vmul_p: Enum
|
||||
r4000allegrex_vmul_t: Enum
|
||||
r4000allegrex_vmul_q: Enum
|
||||
r4000allegrex_vdot_p: Enum
|
||||
r4000allegrex_vdot_t: Enum
|
||||
r4000allegrex_vdot_q: Enum
|
||||
r4000allegrex_vscl_p: Enum
|
||||
r4000allegrex_vscl_t: Enum
|
||||
r4000allegrex_vscl_q: Enum
|
||||
r4000allegrex_vhdp_p: Enum
|
||||
r4000allegrex_vhdp_t: Enum
|
||||
r4000allegrex_vhdp_q: Enum
|
||||
r4000allegrex_vcrs_t: Enum
|
||||
r4000allegrex_vdet_p: Enum
|
||||
r4000allegrex_vcmp_s: Enum
|
||||
r4000allegrex_vcmp_p: Enum
|
||||
r4000allegrex_vcmp_t: Enum
|
||||
r4000allegrex_vcmp_q: Enum
|
||||
r4000allegrex_vmin_s: Enum
|
||||
r4000allegrex_vmin_p: Enum
|
||||
r4000allegrex_vmin_t: Enum
|
||||
r4000allegrex_vmin_q: Enum
|
||||
r4000allegrex_vmax_s: Enum
|
||||
r4000allegrex_vmax_p: Enum
|
||||
r4000allegrex_vmax_t: Enum
|
||||
r4000allegrex_vmax_q: Enum
|
||||
r4000allegrex_vscmp_s: Enum
|
||||
r4000allegrex_vscmp_p: Enum
|
||||
r4000allegrex_vscmp_t: Enum
|
||||
r4000allegrex_vscmp_q: Enum
|
||||
r4000allegrex_vsge_s: Enum
|
||||
r4000allegrex_vsge_p: Enum
|
||||
r4000allegrex_vsge_t: Enum
|
||||
r4000allegrex_vsge_q: Enum
|
||||
r4000allegrex_vslt_s: Enum
|
||||
r4000allegrex_vslt_p: Enum
|
||||
r4000allegrex_vslt_t: Enum
|
||||
r4000allegrex_vslt_q: Enum
|
||||
r4000allegrex_vwbn_s: Enum
|
||||
r4000allegrex_vmov_s: Enum
|
||||
r4000allegrex_vmov_p: Enum
|
||||
r4000allegrex_vmov_t: Enum
|
||||
r4000allegrex_vmov_q: Enum
|
||||
r4000allegrex_vabs_s: Enum
|
||||
r4000allegrex_vabs_p: Enum
|
||||
r4000allegrex_vabs_t: Enum
|
||||
r4000allegrex_vabs_q: Enum
|
||||
r4000allegrex_vneg_s: Enum
|
||||
r4000allegrex_vneg_p: Enum
|
||||
r4000allegrex_vneg_t: Enum
|
||||
r4000allegrex_vneg_q: Enum
|
||||
r4000allegrex_vidt_p: Enum
|
||||
r4000allegrex_vidt_q: Enum
|
||||
r4000allegrex_vsat0_s: Enum
|
||||
r4000allegrex_vsat0_p: Enum
|
||||
r4000allegrex_vsat0_t: Enum
|
||||
r4000allegrex_vsat0_q: Enum
|
||||
r4000allegrex_vsat1_s: Enum
|
||||
r4000allegrex_vsat1_p: Enum
|
||||
r4000allegrex_vsat1_t: Enum
|
||||
r4000allegrex_vsat1_q: Enum
|
||||
r4000allegrex_vzero_s: Enum
|
||||
r4000allegrex_vzero_p: Enum
|
||||
r4000allegrex_vzero_t: Enum
|
||||
r4000allegrex_vzero_q: Enum
|
||||
r4000allegrex_vone_s: Enum
|
||||
r4000allegrex_vone_p: Enum
|
||||
r4000allegrex_vone_t: Enum
|
||||
r4000allegrex_vone_q: Enum
|
||||
r4000allegrex_vrcp_s: Enum
|
||||
r4000allegrex_vrcp_p: Enum
|
||||
r4000allegrex_vrcp_t: Enum
|
||||
r4000allegrex_vrcp_q: Enum
|
||||
r4000allegrex_vrsq_s: Enum
|
||||
r4000allegrex_vrsq_p: Enum
|
||||
r4000allegrex_vrsq_t: Enum
|
||||
r4000allegrex_vrsq_q: Enum
|
||||
r4000allegrex_vsin_s: Enum
|
||||
r4000allegrex_vsin_p: Enum
|
||||
r4000allegrex_vsin_t: Enum
|
||||
r4000allegrex_vsin_q: Enum
|
||||
r4000allegrex_vcos_s: Enum
|
||||
r4000allegrex_vcos_p: Enum
|
||||
r4000allegrex_vcos_t: Enum
|
||||
r4000allegrex_vcos_q: Enum
|
||||
r4000allegrex_vexp2_s: Enum
|
||||
r4000allegrex_vexp2_p: Enum
|
||||
r4000allegrex_vexp2_t: Enum
|
||||
r4000allegrex_vexp2_q: Enum
|
||||
r4000allegrex_vlog2_s: Enum
|
||||
r4000allegrex_vlog2_p: Enum
|
||||
r4000allegrex_vlog2_t: Enum
|
||||
r4000allegrex_vlog2_q: Enum
|
||||
r4000allegrex_vsqrt_s: Enum
|
||||
r4000allegrex_vsqrt_p: Enum
|
||||
r4000allegrex_vsqrt_t: Enum
|
||||
r4000allegrex_vsqrt_q: Enum
|
||||
r4000allegrex_vasin_s: Enum
|
||||
r4000allegrex_vasin_p: Enum
|
||||
r4000allegrex_vasin_t: Enum
|
||||
r4000allegrex_vasin_q: Enum
|
||||
r4000allegrex_vnrcp_s: Enum
|
||||
r4000allegrex_vnrcp_p: Enum
|
||||
r4000allegrex_vnrcp_t: Enum
|
||||
r4000allegrex_vnrcp_q: Enum
|
||||
r4000allegrex_vnsin_s: Enum
|
||||
r4000allegrex_vnsin_p: Enum
|
||||
r4000allegrex_vnsin_t: Enum
|
||||
r4000allegrex_vnsin_q: Enum
|
||||
r4000allegrex_vrexp2_s: Enum
|
||||
r4000allegrex_vrexp2_p: Enum
|
||||
r4000allegrex_vrexp2_t: Enum
|
||||
r4000allegrex_vrexp2_q: Enum
|
||||
r4000allegrex_vrnds_s: Enum
|
||||
r4000allegrex_vrndi_s: Enum
|
||||
r4000allegrex_vrndi_p: Enum
|
||||
r4000allegrex_vrndi_t: Enum
|
||||
r4000allegrex_vrndi_q: Enum
|
||||
r4000allegrex_vrndf1_s: Enum
|
||||
r4000allegrex_vrndf1_p: Enum
|
||||
r4000allegrex_vrndf1_t: Enum
|
||||
r4000allegrex_vrndf1_q: Enum
|
||||
r4000allegrex_vrndf2_s: Enum
|
||||
r4000allegrex_vrndf2_p: Enum
|
||||
r4000allegrex_vrndf2_t: Enum
|
||||
r4000allegrex_vrndf2_q: Enum
|
||||
r4000allegrex_vf2h_p: Enum
|
||||
r4000allegrex_vf2h_q: Enum
|
||||
r4000allegrex_vh2f_s: Enum
|
||||
r4000allegrex_vh2f_p: Enum
|
||||
r4000allegrex_vsbz_s: Enum
|
||||
r4000allegrex_vlgb_s: Enum
|
||||
r4000allegrex_vuc2ifs_s: Enum
|
||||
r4000allegrex_vc2i_s: Enum
|
||||
r4000allegrex_vus2i_s: Enum
|
||||
r4000allegrex_vus2i_p: Enum
|
||||
r4000allegrex_vs2i_s: Enum
|
||||
r4000allegrex_vs2i_p: Enum
|
||||
r4000allegrex_vi2uc_q: Enum
|
||||
r4000allegrex_vi2c_q: Enum
|
||||
r4000allegrex_vi2us_p: Enum
|
||||
r4000allegrex_vi2us_q: Enum
|
||||
r4000allegrex_vi2s_p: Enum
|
||||
r4000allegrex_vi2s_q: Enum
|
||||
r4000allegrex_vsrt1_q: Enum
|
||||
r4000allegrex_vsrt2_q: Enum
|
||||
r4000allegrex_vbfy1_p: Enum
|
||||
r4000allegrex_vbfy1_q: Enum
|
||||
r4000allegrex_vbfy2_q: Enum
|
||||
r4000allegrex_vocp_s: Enum
|
||||
r4000allegrex_vocp_p: Enum
|
||||
r4000allegrex_vocp_t: Enum
|
||||
r4000allegrex_vocp_q: Enum
|
||||
r4000allegrex_vsocp_s: Enum
|
||||
r4000allegrex_vsocp_p: Enum
|
||||
r4000allegrex_vfad_p: Enum
|
||||
r4000allegrex_vfad_t: Enum
|
||||
r4000allegrex_vfad_q: Enum
|
||||
r4000allegrex_vavg_p: Enum
|
||||
r4000allegrex_vavg_t: Enum
|
||||
r4000allegrex_vavg_q: Enum
|
||||
r4000allegrex_vsrt3_q: Enum
|
||||
r4000allegrex_vsrt4_q: Enum
|
||||
r4000allegrex_vsgn_s: Enum
|
||||
r4000allegrex_vsgn_p: Enum
|
||||
r4000allegrex_vsgn_t: Enum
|
||||
r4000allegrex_vsgn_q: Enum
|
||||
r4000allegrex_vmfvc: Enum
|
||||
r4000allegrex_vmtvc: Enum
|
||||
r4000allegrex_vt4444_q: Enum
|
||||
r4000allegrex_vt5551_q: Enum
|
||||
r4000allegrex_vt5650_q: Enum
|
||||
r4000allegrex_vcst_s: Enum
|
||||
r4000allegrex_vcst_p: Enum
|
||||
r4000allegrex_vcst_t: Enum
|
||||
r4000allegrex_vcst_q: Enum
|
||||
r4000allegrex_vf2in_s: Enum
|
||||
r4000allegrex_vf2in_p: Enum
|
||||
r4000allegrex_vf2in_t: Enum
|
||||
r4000allegrex_vf2in_q: Enum
|
||||
r4000allegrex_vf2iz_s: Enum
|
||||
r4000allegrex_vf2iz_p: Enum
|
||||
r4000allegrex_vf2iz_t: Enum
|
||||
r4000allegrex_vf2iz_q: Enum
|
||||
r4000allegrex_vf2iu_s: Enum
|
||||
r4000allegrex_vf2iu_p: Enum
|
||||
r4000allegrex_vf2iu_t: Enum
|
||||
r4000allegrex_vf2iu_q: Enum
|
||||
r4000allegrex_vf2id_s: Enum
|
||||
r4000allegrex_vf2id_p: Enum
|
||||
r4000allegrex_vf2id_t: Enum
|
||||
r4000allegrex_vf2id_q: Enum
|
||||
r4000allegrex_vi2f_s: Enum
|
||||
r4000allegrex_vi2f_p: Enum
|
||||
r4000allegrex_vi2f_t: Enum
|
||||
r4000allegrex_vi2f_q: Enum
|
||||
r4000allegrex_vcmovt_s: Enum
|
||||
r4000allegrex_vcmovt_p: Enum
|
||||
r4000allegrex_vcmovt_t: Enum
|
||||
r4000allegrex_vcmovt_q: Enum
|
||||
r4000allegrex_vcmovf_s: Enum
|
||||
r4000allegrex_vcmovf_p: Enum
|
||||
r4000allegrex_vcmovf_t: Enum
|
||||
r4000allegrex_vcmovf_q: Enum
|
||||
r4000allegrex_vpfxs: Enum
|
||||
r4000allegrex_vpfxt: Enum
|
||||
r4000allegrex_vpfxd: Enum
|
||||
r4000allegrex_viim_s: Enum
|
||||
r4000allegrex_vfim_s: Enum
|
||||
r4000allegrex_vmmul_p: Enum
|
||||
r4000allegrex_vmmul_t: Enum
|
||||
r4000allegrex_vmmul_q: Enum
|
||||
r4000allegrex_vhtfm2_p: Enum
|
||||
r4000allegrex_vtfm2_p: Enum
|
||||
r4000allegrex_vhtfm3_t: Enum
|
||||
r4000allegrex_vtfm3_t: Enum
|
||||
r4000allegrex_vhtfm4_q: Enum
|
||||
r4000allegrex_vtfm4_q: Enum
|
||||
r4000allegrex_vmscl_p: Enum
|
||||
r4000allegrex_vmscl_t: Enum
|
||||
r4000allegrex_vmscl_q: Enum
|
||||
r4000allegrex_vcrsp_t: Enum
|
||||
r4000allegrex_vqmul_q: Enum
|
||||
r4000allegrex_vrot_p: Enum
|
||||
r4000allegrex_vrot_t: Enum
|
||||
r4000allegrex_vrot_q: Enum
|
||||
r4000allegrex_vmmov_p: Enum
|
||||
r4000allegrex_vmmov_t: Enum
|
||||
r4000allegrex_vmmov_q: Enum
|
||||
r4000allegrex_vmidt_p: Enum
|
||||
r4000allegrex_vmidt_t: Enum
|
||||
r4000allegrex_vmidt_q: Enum
|
||||
r4000allegrex_vmzero_p: Enum
|
||||
r4000allegrex_vmzero_t: Enum
|
||||
r4000allegrex_vmzero_q: Enum
|
||||
r4000allegrex_vmone_p: Enum
|
||||
r4000allegrex_vmone_t: Enum
|
||||
r4000allegrex_vmone_q: Enum
|
||||
r4000allegrex_vnop: Enum
|
||||
r4000allegrex_vsync: Enum
|
||||
r4000allegrex_vflush: Enum
|
||||
r4000allegrex_svl_q: Enum
|
||||
r4000allegrex_svr_q: Enum
|
||||
r4000allegrex_MAX: Enum
|
||||
r5900_INVALID: Enum
|
||||
r5900_lq: Enum
|
||||
r5900_sq: Enum
|
||||
|
||||
46
rabbitizer/InstrIdType.pyi
generated
46
rabbitizer/InstrIdType.pyi
generated
@ -41,6 +41,52 @@ class InstrIdType:
|
||||
R3000GTE_COP1: Enum
|
||||
R3000GTE_COP2: Enum
|
||||
R3000GTE_COP2_GTE: Enum
|
||||
R4000ALLEGREX_INVALID: Enum
|
||||
R4000ALLEGREX_NORMAL: Enum
|
||||
R4000ALLEGREX_SPECIAL: Enum
|
||||
R4000ALLEGREX_SPECIAL_RS: Enum
|
||||
R4000ALLEGREX_SPECIAL_SA: Enum
|
||||
R4000ALLEGREX_REGIMM: Enum
|
||||
R4000ALLEGREX_SPECIAL2: Enum
|
||||
R4000ALLEGREX_SPECIAL3: Enum
|
||||
R4000ALLEGREX_SPECIAL3_BSHFL: Enum
|
||||
R4000ALLEGREX_COP0: Enum
|
||||
R4000ALLEGREX_COP0_BC0: Enum
|
||||
R4000ALLEGREX_COP0_TLB: Enum
|
||||
R4000ALLEGREX_COP1: Enum
|
||||
R4000ALLEGREX_COP1_BC1: Enum
|
||||
R4000ALLEGREX_COP1_FPUS: Enum
|
||||
R4000ALLEGREX_COP1_FPUW: Enum
|
||||
R4000ALLEGREX_COP2: Enum
|
||||
R4000ALLEGREX_COP2_BC2: Enum
|
||||
R4000ALLEGREX_COP2_MFHC2: Enum
|
||||
R4000ALLEGREX_COP2_MFHC2_P: Enum
|
||||
R4000ALLEGREX_COP2_MFHC2_P_S: Enum
|
||||
R4000ALLEGREX_COP2_MTHC2: Enum
|
||||
R4000ALLEGREX_VFPU0: Enum
|
||||
R4000ALLEGREX_VFPU1: Enum
|
||||
R4000ALLEGREX_VFPU3: Enum
|
||||
R4000ALLEGREX_VFPU4: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT0: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT2: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT3: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_RND: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_CVTFLT: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_CVTINT: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT8: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT9: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_CONTROL: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_COLOR: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT0_CST: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT2: Enum
|
||||
R4000ALLEGREX_VFPU4_FMT2_CNDMOVE: Enum
|
||||
R4000ALLEGREX_VFPU5: Enum
|
||||
R4000ALLEGREX_VFPU6: Enum
|
||||
R4000ALLEGREX_VFPU6_FMT7: Enum
|
||||
R4000ALLEGREX_VFPU6_FMT7_FMT0: Enum
|
||||
R4000ALLEGREX_VFPU7: Enum
|
||||
R4000ALLEGREX_QUADLR: Enum
|
||||
R5900_INVALID: Enum
|
||||
R5900_NORMAL: Enum
|
||||
R5900_SPECIAL: Enum
|
||||
|
||||
57
rabbitizer/OperandType.pyi
generated
57
rabbitizer/OperandType.pyi
generated
@ -53,6 +53,63 @@ class OperandType:
|
||||
r3000gte_v: Enum
|
||||
r3000gte_cv: Enum
|
||||
r3000gte_lm: Enum
|
||||
r4000allegrex_s_vs: Enum
|
||||
r4000allegrex_s_vt: Enum
|
||||
r4000allegrex_s_vd: Enum
|
||||
r4000allegrex_s_vt_imm: Enum
|
||||
r4000allegrex_s_vd_imm: Enum
|
||||
r4000allegrex_p_vs: Enum
|
||||
r4000allegrex_p_vt: Enum
|
||||
r4000allegrex_p_vd: Enum
|
||||
r4000allegrex_t_vs: Enum
|
||||
r4000allegrex_t_vt: Enum
|
||||
r4000allegrex_t_vd: Enum
|
||||
r4000allegrex_q_vs: Enum
|
||||
r4000allegrex_q_vt: Enum
|
||||
r4000allegrex_q_vd: Enum
|
||||
r4000allegrex_q_vt_imm: Enum
|
||||
r4000allegrex_mp_vs: Enum
|
||||
r4000allegrex_mp_vt: Enum
|
||||
r4000allegrex_mp_vd: Enum
|
||||
r4000allegrex_mp_vs_transpose: Enum
|
||||
r4000allegrex_mt_vs: Enum
|
||||
r4000allegrex_mt_vt: Enum
|
||||
r4000allegrex_mt_vd: Enum
|
||||
r4000allegrex_mt_vs_transpose: Enum
|
||||
r4000allegrex_mq_vs: Enum
|
||||
r4000allegrex_mq_vt: Enum
|
||||
r4000allegrex_mq_vd: Enum
|
||||
r4000allegrex_mq_vs_transpose: Enum
|
||||
r4000allegrex_cop2cs: Enum
|
||||
r4000allegrex_cop2cd: Enum
|
||||
r4000allegrex_pos: Enum
|
||||
r4000allegrex_size: Enum
|
||||
r4000allegrex_size_plus_pos: Enum
|
||||
r4000allegrex_imm3: Enum
|
||||
r4000allegrex_offset14_base: Enum
|
||||
r4000allegrex_offset14_base_maybe_wb: Enum
|
||||
r4000allegrex_vcmp_cond: Enum
|
||||
r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt: Enum
|
||||
r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt: Enum
|
||||
r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt: Enum
|
||||
r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt: Enum
|
||||
r4000allegrex_vconstant: Enum
|
||||
r4000allegrex_power_of_two: Enum
|
||||
r4000allegrex_vfpu_cc_bit: Enum
|
||||
r4000allegrex_bn: Enum
|
||||
r4000allegrex_int16: Enum
|
||||
r4000allegrex_float16: Enum
|
||||
r4000allegrex_p_vrot_code: Enum
|
||||
r4000allegrex_t_vrot_code: Enum
|
||||
r4000allegrex_q_vrot_code: Enum
|
||||
r4000allegrex_rpx: Enum
|
||||
r4000allegrex_rpy: Enum
|
||||
r4000allegrex_rpz: Enum
|
||||
r4000allegrex_rpw: Enum
|
||||
r4000allegrex_wpx: Enum
|
||||
r4000allegrex_wpy: Enum
|
||||
r4000allegrex_wpz: Enum
|
||||
r4000allegrex_wpw: Enum
|
||||
r5900_I: Enum
|
||||
r5900_Q: Enum
|
||||
r5900_R: Enum
|
||||
|
||||
@ -12,3 +12,11 @@ class Utils:
|
||||
|
||||
@staticmethod
|
||||
def escapeString(src: str) -> str: ...
|
||||
|
||||
@staticmethod
|
||||
def floatRepr_32From16(hex_repr: int) -> int:
|
||||
"""
|
||||
Converts an unsigned 16 bits value representing a half precision
|
||||
float to a unsigned 32 bits value representing a single precision
|
||||
float.
|
||||
"""
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
{ "RegCop1N32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
|
||||
#define RABBITIZER_DEF_REG_NODOLLAR(prefix, name, numeric, ...) \
|
||||
{ "RegCop1N32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
RABBITIZER_DEF_REG(prefix, name, numeric, __VARGS__)
|
||||
|
||||
RabbitizerEnumMetadata rabbitizer_enum_RegCop1N32_enumvalues[] = {
|
||||
#include "tables/registers/RabbitizerRegister_Cop1N32.inc"
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
{ "RegCop1N64", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
|
||||
#define RABBITIZER_DEF_REG_NODOLLAR(prefix, name, numeric, ...) \
|
||||
{ "RegCop1N64", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
RABBITIZER_DEF_REG(prefix, name, numeric, __VARGS__)
|
||||
|
||||
RabbitizerEnumMetadata rabbitizer_enum_RegCop1N64_enumvalues[] = {
|
||||
#include "tables/registers/RabbitizerRegister_Cop1N64.inc"
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
{ "RegCop1O32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
|
||||
#define RABBITIZER_DEF_REG_NODOLLAR(prefix, name, numeric, ...) \
|
||||
{ "RegCop1O32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
RABBITIZER_DEF_REG(prefix, name, numeric, __VARGS__)
|
||||
|
||||
RabbitizerEnumMetadata rabbitizer_enum_RegCop1O32_enumvalues[] = {
|
||||
#include "tables/registers/RabbitizerRegister_Cop1O32.inc"
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
{ "RegGprN32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
|
||||
#define RABBITIZER_DEF_REG_NODOLLAR(prefix, name, numeric, ...) \
|
||||
{ "RegGprN32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
RABBITIZER_DEF_REG(prefix, name, numeric, __VARGS__)
|
||||
|
||||
RabbitizerEnumMetadata rabbitizer_enum_RegGprN32_enumvalues[] = {
|
||||
#include "tables/registers/RabbitizerRegister_GprN32.inc"
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
{ "RegGprO32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
|
||||
#define RABBITIZER_DEF_REG_NODOLLAR(prefix, name, numeric, ...) \
|
||||
{ "RegGprO32", #name, RABBITIZER_REG_##prefix##_##name, false, NULL },
|
||||
RABBITIZER_DEF_REG(prefix, name, numeric, __VARGS__)
|
||||
|
||||
RabbitizerEnumMetadata rabbitizer_enum_RegGprO32_enumvalues[] = {
|
||||
#include "tables/registers/RabbitizerRegister_GprO32.inc"
|
||||
|
||||
@ -106,6 +106,7 @@ DEF_MEMBER_GET_SET_ABI(regNames, fprAbiNames)
|
||||
DEF_MEMBER_GET_SET_BOOL(regNames, userFpcCsr)
|
||||
DEF_MEMBER_GET_SET_BOOL(regNames, vr4300Cop0NamedRegisters)
|
||||
DEF_MEMBER_GET_SET_BOOL(regNames, vr4300RspCop0NamedRegisters)
|
||||
DEF_MEMBER_GET_SET_BOOL(regNames, r4000AllegrexVfpuControlNamedRegisters)
|
||||
|
||||
DEF_MEMBER_GET_SET_BOOL(pseudos, enablePseudos)
|
||||
DEF_MEMBER_GET_SET_BOOL(pseudos, pseudoBeqz)
|
||||
@ -134,6 +135,7 @@ static PyGetSetDef rabbitizer_global_config_GetSets[] = {
|
||||
MEMBER_GET_SET(regNames, userFpcCsr, "", NULL),
|
||||
MEMBER_GET_SET(regNames, vr4300Cop0NamedRegisters, "", NULL),
|
||||
MEMBER_GET_SET(regNames, vr4300RspCop0NamedRegisters, "", NULL),
|
||||
MEMBER_GET_SET(regNames, r4000AllegrexVfpuControlNamedRegisters, "", NULL),
|
||||
|
||||
MEMBER_GET_SET(pseudos, enablePseudos, "", NULL),
|
||||
MEMBER_GET_SET(pseudos, pseudoBeqz, "", NULL),
|
||||
|
||||
@ -49,6 +49,17 @@ static PyObject *rabbitizer_submodule_Utils_escapeString(UNUSED PyObject *self,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static PyObject *rabbitizer_submodule_Utils_floatRepr_32From16(UNUSED PyObject *self, PyObject *args, PyObject *kwds) {
|
||||
static char *kwlist[] = { "hex_repr", NULL };
|
||||
uint16_t hex_repr = 0;
|
||||
|
||||
if (!PyArg_ParseTupleAndKeywords(args, kwds, "H", kwlist, &hex_repr)) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return PyLong_FromLong(RabbitizerUtils_floatRepr_32From16(hex_repr));
|
||||
}
|
||||
|
||||
|
||||
#define METHOD_NO_ARGS(name, docs) { #name, (PyCFunction) (void *) rabbitizer_submodule_Utils_##name, METH_NOARGS, PyDoc_STR(docs) }
|
||||
#define METHOD_ARGS(name, docs) { #name, (PyCFunction) (void *) rabbitizer_submodule_Utils_##name, METH_VARARGS | METH_KEYWORDS, PyDoc_STR(docs) }
|
||||
@ -56,6 +67,7 @@ static PyObject *rabbitizer_submodule_Utils_escapeString(UNUSED PyObject *self,
|
||||
static PyMethodDef rabbitizer_submodule_Utils_methods[] = {
|
||||
METHOD_ARGS(from2Complement, ""),
|
||||
METHOD_ARGS(escapeString, ""),
|
||||
METHOD_ARGS(floatRepr_32From16, ""),
|
||||
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
|
||||
#include "instructions/RabbitizerInstructionRsp.h"
|
||||
#include "instructions/RabbitizerInstructionR3000GTE.h"
|
||||
#include "instructions/RabbitizerInstructionR4000Allegrex.h"
|
||||
#include "instructions/RabbitizerInstructionR5900.h"
|
||||
#include "common/RabbitizerConfig.h"
|
||||
|
||||
@ -55,6 +56,11 @@ static int rabbitizer_type_Instruction_init(PyRabbitizerInstruction *self, PyObj
|
||||
RabbitizerInstructionR5900_processUniqueId(&self->instr);
|
||||
break;
|
||||
|
||||
case RABBITIZER_INSTRCAT_R4000ALLEGREX:
|
||||
RabbitizerInstructionR4000Allegrex_init(&self->instr, word, vram);
|
||||
RabbitizerInstructionR4000Allegrex_processUniqueId(&self->instr);
|
||||
break;
|
||||
|
||||
case RABBITIZER_INSTRCAT_CPU:
|
||||
case RABBITIZER_INSTRCAT_MAX:
|
||||
RabbitizerInstruction_init(&self->instr, word, vram);
|
||||
|
||||
1
rust/src/instr_category_enum.rs
generated
1
rust/src/instr_category_enum.rs
generated
@ -10,6 +10,7 @@ pub enum InstrCategory {
|
||||
CPU,
|
||||
RSP,
|
||||
R3000GTE,
|
||||
R4000ALLEGREX,
|
||||
R5900,
|
||||
MAX,
|
||||
}
|
||||
|
||||
314
rust/src/instr_id_enum.rs
generated
314
rust/src/instr_id_enum.rs
generated
@ -460,6 +460,320 @@ pub enum InstrId {
|
||||
r3000gte_USERDEF_18,
|
||||
r3000gte_USERDEF_19,
|
||||
r3000gte_MAX,
|
||||
r4000allegrex_INVALID,
|
||||
r4000allegrex_lv_s,
|
||||
r4000allegrex_sv_s,
|
||||
r4000allegrex_lv_q,
|
||||
r4000allegrex_sv_q,
|
||||
r4000allegrex_clz,
|
||||
r4000allegrex_clo,
|
||||
r4000allegrex_madd,
|
||||
r4000allegrex_maddu,
|
||||
r4000allegrex_msub,
|
||||
r4000allegrex_msubu,
|
||||
r4000allegrex_max,
|
||||
r4000allegrex_min,
|
||||
r4000allegrex_srl,
|
||||
r4000allegrex_rotr,
|
||||
r4000allegrex_srlv,
|
||||
r4000allegrex_rotrv,
|
||||
r4000allegrex_sleep,
|
||||
r4000allegrex_mfie,
|
||||
r4000allegrex_mtie,
|
||||
r4000allegrex_ext,
|
||||
r4000allegrex_ins,
|
||||
r4000allegrex_wsbh,
|
||||
r4000allegrex_wsbw,
|
||||
r4000allegrex_seb,
|
||||
r4000allegrex_seh,
|
||||
r4000allegrex_bitrev,
|
||||
r4000allegrex_bvf,
|
||||
r4000allegrex_bvt,
|
||||
r4000allegrex_bvfl,
|
||||
r4000allegrex_bvtl,
|
||||
r4000allegrex_mfv,
|
||||
r4000allegrex_mfvc,
|
||||
r4000allegrex_vsync2,
|
||||
r4000allegrex_mtv,
|
||||
r4000allegrex_mtvc,
|
||||
r4000allegrex_vadd_s,
|
||||
r4000allegrex_vadd_p,
|
||||
r4000allegrex_vadd_t,
|
||||
r4000allegrex_vadd_q,
|
||||
r4000allegrex_vsub_s,
|
||||
r4000allegrex_vsub_p,
|
||||
r4000allegrex_vsub_t,
|
||||
r4000allegrex_vsub_q,
|
||||
r4000allegrex_vsbn_s,
|
||||
r4000allegrex_vdiv_s,
|
||||
r4000allegrex_vdiv_p,
|
||||
r4000allegrex_vdiv_t,
|
||||
r4000allegrex_vdiv_q,
|
||||
r4000allegrex_vmul_s,
|
||||
r4000allegrex_vmul_p,
|
||||
r4000allegrex_vmul_t,
|
||||
r4000allegrex_vmul_q,
|
||||
r4000allegrex_vdot_p,
|
||||
r4000allegrex_vdot_t,
|
||||
r4000allegrex_vdot_q,
|
||||
r4000allegrex_vscl_p,
|
||||
r4000allegrex_vscl_t,
|
||||
r4000allegrex_vscl_q,
|
||||
r4000allegrex_vhdp_p,
|
||||
r4000allegrex_vhdp_t,
|
||||
r4000allegrex_vhdp_q,
|
||||
r4000allegrex_vcrs_t,
|
||||
r4000allegrex_vdet_p,
|
||||
r4000allegrex_vcmp_s,
|
||||
r4000allegrex_vcmp_p,
|
||||
r4000allegrex_vcmp_t,
|
||||
r4000allegrex_vcmp_q,
|
||||
r4000allegrex_vmin_s,
|
||||
r4000allegrex_vmin_p,
|
||||
r4000allegrex_vmin_t,
|
||||
r4000allegrex_vmin_q,
|
||||
r4000allegrex_vmax_s,
|
||||
r4000allegrex_vmax_p,
|
||||
r4000allegrex_vmax_t,
|
||||
r4000allegrex_vmax_q,
|
||||
r4000allegrex_vscmp_s,
|
||||
r4000allegrex_vscmp_p,
|
||||
r4000allegrex_vscmp_t,
|
||||
r4000allegrex_vscmp_q,
|
||||
r4000allegrex_vsge_s,
|
||||
r4000allegrex_vsge_p,
|
||||
r4000allegrex_vsge_t,
|
||||
r4000allegrex_vsge_q,
|
||||
r4000allegrex_vslt_s,
|
||||
r4000allegrex_vslt_p,
|
||||
r4000allegrex_vslt_t,
|
||||
r4000allegrex_vslt_q,
|
||||
r4000allegrex_vwbn_s,
|
||||
r4000allegrex_vmov_s,
|
||||
r4000allegrex_vmov_p,
|
||||
r4000allegrex_vmov_t,
|
||||
r4000allegrex_vmov_q,
|
||||
r4000allegrex_vabs_s,
|
||||
r4000allegrex_vabs_p,
|
||||
r4000allegrex_vabs_t,
|
||||
r4000allegrex_vabs_q,
|
||||
r4000allegrex_vneg_s,
|
||||
r4000allegrex_vneg_p,
|
||||
r4000allegrex_vneg_t,
|
||||
r4000allegrex_vneg_q,
|
||||
r4000allegrex_vidt_p,
|
||||
r4000allegrex_vidt_q,
|
||||
r4000allegrex_vsat0_s,
|
||||
r4000allegrex_vsat0_p,
|
||||
r4000allegrex_vsat0_t,
|
||||
r4000allegrex_vsat0_q,
|
||||
r4000allegrex_vsat1_s,
|
||||
r4000allegrex_vsat1_p,
|
||||
r4000allegrex_vsat1_t,
|
||||
r4000allegrex_vsat1_q,
|
||||
r4000allegrex_vzero_s,
|
||||
r4000allegrex_vzero_p,
|
||||
r4000allegrex_vzero_t,
|
||||
r4000allegrex_vzero_q,
|
||||
r4000allegrex_vone_s,
|
||||
r4000allegrex_vone_p,
|
||||
r4000allegrex_vone_t,
|
||||
r4000allegrex_vone_q,
|
||||
r4000allegrex_vrcp_s,
|
||||
r4000allegrex_vrcp_p,
|
||||
r4000allegrex_vrcp_t,
|
||||
r4000allegrex_vrcp_q,
|
||||
r4000allegrex_vrsq_s,
|
||||
r4000allegrex_vrsq_p,
|
||||
r4000allegrex_vrsq_t,
|
||||
r4000allegrex_vrsq_q,
|
||||
r4000allegrex_vsin_s,
|
||||
r4000allegrex_vsin_p,
|
||||
r4000allegrex_vsin_t,
|
||||
r4000allegrex_vsin_q,
|
||||
r4000allegrex_vcos_s,
|
||||
r4000allegrex_vcos_p,
|
||||
r4000allegrex_vcos_t,
|
||||
r4000allegrex_vcos_q,
|
||||
r4000allegrex_vexp2_s,
|
||||
r4000allegrex_vexp2_p,
|
||||
r4000allegrex_vexp2_t,
|
||||
r4000allegrex_vexp2_q,
|
||||
r4000allegrex_vlog2_s,
|
||||
r4000allegrex_vlog2_p,
|
||||
r4000allegrex_vlog2_t,
|
||||
r4000allegrex_vlog2_q,
|
||||
r4000allegrex_vsqrt_s,
|
||||
r4000allegrex_vsqrt_p,
|
||||
r4000allegrex_vsqrt_t,
|
||||
r4000allegrex_vsqrt_q,
|
||||
r4000allegrex_vasin_s,
|
||||
r4000allegrex_vasin_p,
|
||||
r4000allegrex_vasin_t,
|
||||
r4000allegrex_vasin_q,
|
||||
r4000allegrex_vnrcp_s,
|
||||
r4000allegrex_vnrcp_p,
|
||||
r4000allegrex_vnrcp_t,
|
||||
r4000allegrex_vnrcp_q,
|
||||
r4000allegrex_vnsin_s,
|
||||
r4000allegrex_vnsin_p,
|
||||
r4000allegrex_vnsin_t,
|
||||
r4000allegrex_vnsin_q,
|
||||
r4000allegrex_vrexp2_s,
|
||||
r4000allegrex_vrexp2_p,
|
||||
r4000allegrex_vrexp2_t,
|
||||
r4000allegrex_vrexp2_q,
|
||||
r4000allegrex_vrnds_s,
|
||||
r4000allegrex_vrndi_s,
|
||||
r4000allegrex_vrndi_p,
|
||||
r4000allegrex_vrndi_t,
|
||||
r4000allegrex_vrndi_q,
|
||||
r4000allegrex_vrndf1_s,
|
||||
r4000allegrex_vrndf1_p,
|
||||
r4000allegrex_vrndf1_t,
|
||||
r4000allegrex_vrndf1_q,
|
||||
r4000allegrex_vrndf2_s,
|
||||
r4000allegrex_vrndf2_p,
|
||||
r4000allegrex_vrndf2_t,
|
||||
r4000allegrex_vrndf2_q,
|
||||
r4000allegrex_vf2h_p,
|
||||
r4000allegrex_vf2h_q,
|
||||
r4000allegrex_vh2f_s,
|
||||
r4000allegrex_vh2f_p,
|
||||
r4000allegrex_vsbz_s,
|
||||
r4000allegrex_vlgb_s,
|
||||
r4000allegrex_vuc2ifs_s,
|
||||
r4000allegrex_vc2i_s,
|
||||
r4000allegrex_vus2i_s,
|
||||
r4000allegrex_vus2i_p,
|
||||
r4000allegrex_vs2i_s,
|
||||
r4000allegrex_vs2i_p,
|
||||
r4000allegrex_vi2uc_q,
|
||||
r4000allegrex_vi2c_q,
|
||||
r4000allegrex_vi2us_p,
|
||||
r4000allegrex_vi2us_q,
|
||||
r4000allegrex_vi2s_p,
|
||||
r4000allegrex_vi2s_q,
|
||||
r4000allegrex_vsrt1_q,
|
||||
r4000allegrex_vsrt2_q,
|
||||
r4000allegrex_vbfy1_p,
|
||||
r4000allegrex_vbfy1_q,
|
||||
r4000allegrex_vbfy2_q,
|
||||
r4000allegrex_vocp_s,
|
||||
r4000allegrex_vocp_p,
|
||||
r4000allegrex_vocp_t,
|
||||
r4000allegrex_vocp_q,
|
||||
r4000allegrex_vsocp_s,
|
||||
r4000allegrex_vsocp_p,
|
||||
r4000allegrex_vfad_p,
|
||||
r4000allegrex_vfad_t,
|
||||
r4000allegrex_vfad_q,
|
||||
r4000allegrex_vavg_p,
|
||||
r4000allegrex_vavg_t,
|
||||
r4000allegrex_vavg_q,
|
||||
r4000allegrex_vsrt3_q,
|
||||
r4000allegrex_vsrt4_q,
|
||||
r4000allegrex_vsgn_s,
|
||||
r4000allegrex_vsgn_p,
|
||||
r4000allegrex_vsgn_t,
|
||||
r4000allegrex_vsgn_q,
|
||||
r4000allegrex_vmfvc,
|
||||
r4000allegrex_vmtvc,
|
||||
r4000allegrex_vt4444_q,
|
||||
r4000allegrex_vt5551_q,
|
||||
r4000allegrex_vt5650_q,
|
||||
r4000allegrex_vcst_s,
|
||||
r4000allegrex_vcst_p,
|
||||
r4000allegrex_vcst_t,
|
||||
r4000allegrex_vcst_q,
|
||||
r4000allegrex_vf2in_s,
|
||||
r4000allegrex_vf2in_p,
|
||||
r4000allegrex_vf2in_t,
|
||||
r4000allegrex_vf2in_q,
|
||||
r4000allegrex_vf2iz_s,
|
||||
r4000allegrex_vf2iz_p,
|
||||
r4000allegrex_vf2iz_t,
|
||||
r4000allegrex_vf2iz_q,
|
||||
r4000allegrex_vf2iu_s,
|
||||
r4000allegrex_vf2iu_p,
|
||||
r4000allegrex_vf2iu_t,
|
||||
r4000allegrex_vf2iu_q,
|
||||
r4000allegrex_vf2id_s,
|
||||
r4000allegrex_vf2id_p,
|
||||
r4000allegrex_vf2id_t,
|
||||
r4000allegrex_vf2id_q,
|
||||
r4000allegrex_vi2f_s,
|
||||
r4000allegrex_vi2f_p,
|
||||
r4000allegrex_vi2f_t,
|
||||
r4000allegrex_vi2f_q,
|
||||
r4000allegrex_vcmovt_s,
|
||||
r4000allegrex_vcmovt_p,
|
||||
r4000allegrex_vcmovt_t,
|
||||
r4000allegrex_vcmovt_q,
|
||||
r4000allegrex_vcmovf_s,
|
||||
r4000allegrex_vcmovf_p,
|
||||
r4000allegrex_vcmovf_t,
|
||||
r4000allegrex_vcmovf_q,
|
||||
r4000allegrex_vpfxs,
|
||||
r4000allegrex_vpfxt,
|
||||
r4000allegrex_vpfxd,
|
||||
r4000allegrex_viim_s,
|
||||
r4000allegrex_vfim_s,
|
||||
r4000allegrex_vmmul_p,
|
||||
r4000allegrex_vmmul_t,
|
||||
r4000allegrex_vmmul_q,
|
||||
r4000allegrex_vhtfm2_p,
|
||||
r4000allegrex_vtfm2_p,
|
||||
r4000allegrex_vhtfm3_t,
|
||||
r4000allegrex_vtfm3_t,
|
||||
r4000allegrex_vhtfm4_q,
|
||||
r4000allegrex_vtfm4_q,
|
||||
r4000allegrex_vmscl_p,
|
||||
r4000allegrex_vmscl_t,
|
||||
r4000allegrex_vmscl_q,
|
||||
r4000allegrex_vcrsp_t,
|
||||
r4000allegrex_vqmul_q,
|
||||
r4000allegrex_vrot_p,
|
||||
r4000allegrex_vrot_t,
|
||||
r4000allegrex_vrot_q,
|
||||
r4000allegrex_vmmov_p,
|
||||
r4000allegrex_vmmov_t,
|
||||
r4000allegrex_vmmov_q,
|
||||
r4000allegrex_vmidt_p,
|
||||
r4000allegrex_vmidt_t,
|
||||
r4000allegrex_vmidt_q,
|
||||
r4000allegrex_vmzero_p,
|
||||
r4000allegrex_vmzero_t,
|
||||
r4000allegrex_vmzero_q,
|
||||
r4000allegrex_vmone_p,
|
||||
r4000allegrex_vmone_t,
|
||||
r4000allegrex_vmone_q,
|
||||
r4000allegrex_vnop,
|
||||
r4000allegrex_vsync,
|
||||
r4000allegrex_vflush,
|
||||
r4000allegrex_svl_q,
|
||||
r4000allegrex_svr_q,
|
||||
r4000allegrex_USERDEF_00,
|
||||
r4000allegrex_USERDEF_01,
|
||||
r4000allegrex_USERDEF_02,
|
||||
r4000allegrex_USERDEF_03,
|
||||
r4000allegrex_USERDEF_04,
|
||||
r4000allegrex_USERDEF_05,
|
||||
r4000allegrex_USERDEF_06,
|
||||
r4000allegrex_USERDEF_07,
|
||||
r4000allegrex_USERDEF_08,
|
||||
r4000allegrex_USERDEF_09,
|
||||
r4000allegrex_USERDEF_10,
|
||||
r4000allegrex_USERDEF_11,
|
||||
r4000allegrex_USERDEF_12,
|
||||
r4000allegrex_USERDEF_13,
|
||||
r4000allegrex_USERDEF_14,
|
||||
r4000allegrex_USERDEF_15,
|
||||
r4000allegrex_USERDEF_16,
|
||||
r4000allegrex_USERDEF_17,
|
||||
r4000allegrex_USERDEF_18,
|
||||
r4000allegrex_USERDEF_19,
|
||||
r4000allegrex_MAX,
|
||||
r5900_INVALID,
|
||||
r5900_lq,
|
||||
r5900_sq,
|
||||
|
||||
46
rust/src/instr_id_type_enum.rs
generated
46
rust/src/instr_id_type_enum.rs
generated
@ -40,6 +40,52 @@ pub enum InstrIdType {
|
||||
R3000GTE_COP1,
|
||||
R3000GTE_COP2,
|
||||
R3000GTE_COP2_GTE,
|
||||
R4000ALLEGREX_INVALID,
|
||||
R4000ALLEGREX_NORMAL,
|
||||
R4000ALLEGREX_SPECIAL,
|
||||
R4000ALLEGREX_SPECIAL_RS,
|
||||
R4000ALLEGREX_SPECIAL_SA,
|
||||
R4000ALLEGREX_REGIMM,
|
||||
R4000ALLEGREX_SPECIAL2,
|
||||
R4000ALLEGREX_SPECIAL3,
|
||||
R4000ALLEGREX_SPECIAL3_BSHFL,
|
||||
R4000ALLEGREX_COP0,
|
||||
R4000ALLEGREX_COP0_BC0,
|
||||
R4000ALLEGREX_COP0_TLB,
|
||||
R4000ALLEGREX_COP1,
|
||||
R4000ALLEGREX_COP1_BC1,
|
||||
R4000ALLEGREX_COP1_FPUS,
|
||||
R4000ALLEGREX_COP1_FPUW,
|
||||
R4000ALLEGREX_COP2,
|
||||
R4000ALLEGREX_COP2_BC2,
|
||||
R4000ALLEGREX_COP2_MFHC2,
|
||||
R4000ALLEGREX_COP2_MFHC2_P,
|
||||
R4000ALLEGREX_COP2_MFHC2_P_S,
|
||||
R4000ALLEGREX_COP2_MTHC2,
|
||||
R4000ALLEGREX_VFPU0,
|
||||
R4000ALLEGREX_VFPU1,
|
||||
R4000ALLEGREX_VFPU3,
|
||||
R4000ALLEGREX_VFPU4,
|
||||
R4000ALLEGREX_VFPU4_FMT0,
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT0,
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT2,
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT3,
|
||||
R4000ALLEGREX_VFPU4_FMT0_RND,
|
||||
R4000ALLEGREX_VFPU4_FMT0_CVTFLT,
|
||||
R4000ALLEGREX_VFPU4_FMT0_CVTINT,
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT8,
|
||||
R4000ALLEGREX_VFPU4_FMT0_FMT9,
|
||||
R4000ALLEGREX_VFPU4_FMT0_CONTROL,
|
||||
R4000ALLEGREX_VFPU4_FMT0_COLOR,
|
||||
R4000ALLEGREX_VFPU4_FMT0_CST,
|
||||
R4000ALLEGREX_VFPU4_FMT2,
|
||||
R4000ALLEGREX_VFPU4_FMT2_CNDMOVE,
|
||||
R4000ALLEGREX_VFPU5,
|
||||
R4000ALLEGREX_VFPU6,
|
||||
R4000ALLEGREX_VFPU6_FMT7,
|
||||
R4000ALLEGREX_VFPU6_FMT7_FMT0,
|
||||
R4000ALLEGREX_VFPU7,
|
||||
R4000ALLEGREX_QUADLR,
|
||||
R5900_INVALID,
|
||||
R5900_NORMAL,
|
||||
R5900_SPECIAL,
|
||||
|
||||
@ -62,6 +62,13 @@ extern "C" {
|
||||
fn RabbitizerInstructionR5900_processUniqueId(self_: *mut Instruction);
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
fn RabbitizerInstructionR4000Allegrex_init(self_: *mut Instruction, word: u32, vram: u32);
|
||||
fn RabbitizerInstructionR4000Allegrex_destroy(self_: *mut Instruction);
|
||||
|
||||
fn RabbitizerInstructionR4000Allegrex_processUniqueId(self_: *mut Instruction);
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
fn RabbitizerInstruction_getRaw(self_: *const Instruction) -> u32;
|
||||
fn RabbitizerInstruction_getProcessedImmediate(self_: *const Instruction) -> i32;
|
||||
@ -209,6 +216,9 @@ impl Drop for Instruction {
|
||||
instr_category_enum::InstrCategory::R5900 => {
|
||||
RabbitizerInstructionR5900_destroy(self);
|
||||
}
|
||||
instr_category_enum::InstrCategory::R4000ALLEGREX => {
|
||||
RabbitizerInstructionR4000Allegrex_destroy(self);
|
||||
}
|
||||
instr_category_enum::InstrCategory::MAX => {
|
||||
core::panic!();
|
||||
}
|
||||
@ -238,6 +248,10 @@ impl Instruction {
|
||||
RabbitizerInstructionR5900_init(instr.as_mut_ptr(), word, vram);
|
||||
RabbitizerInstructionR5900_processUniqueId(instr.as_mut_ptr());
|
||||
}
|
||||
instr_category_enum::InstrCategory::R4000ALLEGREX => {
|
||||
RabbitizerInstructionR4000Allegrex_init(instr.as_mut_ptr(), word, vram);
|
||||
RabbitizerInstructionR4000Allegrex_processUniqueId(instr.as_mut_ptr());
|
||||
}
|
||||
instr_category_enum::InstrCategory::MAX => {
|
||||
core::panic!();
|
||||
} // _ => not used in purpose
|
||||
|
||||
57
rust/src/operand_type_enum.rs
generated
57
rust/src/operand_type_enum.rs
generated
@ -52,6 +52,63 @@ pub enum OperandType {
|
||||
r3000gte_v,
|
||||
r3000gte_cv,
|
||||
r3000gte_lm,
|
||||
r4000allegrex_s_vs,
|
||||
r4000allegrex_s_vt,
|
||||
r4000allegrex_s_vd,
|
||||
r4000allegrex_s_vt_imm,
|
||||
r4000allegrex_s_vd_imm,
|
||||
r4000allegrex_p_vs,
|
||||
r4000allegrex_p_vt,
|
||||
r4000allegrex_p_vd,
|
||||
r4000allegrex_t_vs,
|
||||
r4000allegrex_t_vt,
|
||||
r4000allegrex_t_vd,
|
||||
r4000allegrex_q_vs,
|
||||
r4000allegrex_q_vt,
|
||||
r4000allegrex_q_vd,
|
||||
r4000allegrex_q_vt_imm,
|
||||
r4000allegrex_mp_vs,
|
||||
r4000allegrex_mp_vt,
|
||||
r4000allegrex_mp_vd,
|
||||
r4000allegrex_mp_vs_transpose,
|
||||
r4000allegrex_mt_vs,
|
||||
r4000allegrex_mt_vt,
|
||||
r4000allegrex_mt_vd,
|
||||
r4000allegrex_mt_vs_transpose,
|
||||
r4000allegrex_mq_vs,
|
||||
r4000allegrex_mq_vt,
|
||||
r4000allegrex_mq_vd,
|
||||
r4000allegrex_mq_vs_transpose,
|
||||
r4000allegrex_cop2cs,
|
||||
r4000allegrex_cop2cd,
|
||||
r4000allegrex_pos,
|
||||
r4000allegrex_size,
|
||||
r4000allegrex_size_plus_pos,
|
||||
r4000allegrex_imm3,
|
||||
r4000allegrex_offset14_base,
|
||||
r4000allegrex_offset14_base_maybe_wb,
|
||||
r4000allegrex_vcmp_cond,
|
||||
r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt,
|
||||
r4000allegrex_vconstant,
|
||||
r4000allegrex_power_of_two,
|
||||
r4000allegrex_vfpu_cc_bit,
|
||||
r4000allegrex_bn,
|
||||
r4000allegrex_int16,
|
||||
r4000allegrex_float16,
|
||||
r4000allegrex_p_vrot_code,
|
||||
r4000allegrex_t_vrot_code,
|
||||
r4000allegrex_q_vrot_code,
|
||||
r4000allegrex_rpx,
|
||||
r4000allegrex_rpy,
|
||||
r4000allegrex_rpz,
|
||||
r4000allegrex_rpw,
|
||||
r4000allegrex_wpx,
|
||||
r4000allegrex_wpy,
|
||||
r4000allegrex_wpz,
|
||||
r4000allegrex_wpw,
|
||||
r5900_I,
|
||||
r5900_Q,
|
||||
r5900_R,
|
||||
|
||||
1110
rust/src/registers_enum.rs
generated
1110
rust/src/registers_enum.rs
generated
File diff suppressed because it is too large
Load Diff
@ -19,6 +19,24 @@ extern "C" {
|
||||
pub static mut RabbitizerRegister_RspCop2Control_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_RspVector_Names: [[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexS_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexV2D_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexV3D_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexV4D_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexM2x2_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexM3x3_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexM4x4_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexVfpuControl_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexVConstant_Names:
|
||||
[[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R5900VF_Names: [[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
pub static mut RabbitizerRegister_R5900VI_Names: [[*const core::ffi::c_char; 2usize]; 0usize];
|
||||
|
||||
@ -58,6 +76,18 @@ extern "C" {
|
||||
|
||||
/* RSP */
|
||||
|
||||
pub static mut RabbitizerRegister_R4000AllegrexS_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexV2D_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexV3D_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexV4D_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexM2x2_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexM3x3_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexM4x4_Descriptors: [RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexVfpuControl_Descriptors:
|
||||
[RegisterDescriptor; 0usize];
|
||||
pub static mut RabbitizerRegister_R4000AllegrexVConstant_Descriptors:
|
||||
[RegisterDescriptor; 0usize];
|
||||
|
||||
/* R5900 */
|
||||
|
||||
pub static mut RabbitizerRegister_R5900VF_Descriptors: [RegisterDescriptor; 0usize];
|
||||
@ -300,6 +330,195 @@ impl registers_enum::registers::RspVector {
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexS {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(RabbitizerRegister_R4000AllegrexS_Names[reg_value as usize][1])
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe { RabbitizerRegister_R4000AllegrexS_Descriptors.get_unchecked(reg_value as usize) }
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexV2D {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexV2D_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe { RabbitizerRegister_R4000AllegrexV2D_Descriptors.get_unchecked(reg_value as usize) }
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexV3D {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexV3D_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe { RabbitizerRegister_R4000AllegrexV3D_Descriptors.get_unchecked(reg_value as usize) }
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexV4D {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexV4D_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe { RabbitizerRegister_R4000AllegrexV4D_Descriptors.get_unchecked(reg_value as usize) }
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexM2x2 {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexM2x2_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe {
|
||||
RabbitizerRegister_R4000AllegrexM2x2_Descriptors.get_unchecked(reg_value as usize)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexM3x3 {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexM3x3_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe {
|
||||
RabbitizerRegister_R4000AllegrexM3x3_Descriptors.get_unchecked(reg_value as usize)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexM4x4 {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexM4x4_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe {
|
||||
RabbitizerRegister_R4000AllegrexM4x4_Descriptors.get_unchecked(reg_value as usize)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexVfpuControl {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexVfpuControl_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe {
|
||||
RabbitizerRegister_R4000AllegrexVfpuControl_Descriptors
|
||||
.get_unchecked(reg_value as usize)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R4000AllegrexVConstant {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
unsafe {
|
||||
std::ffi::CStr::from_ptr(
|
||||
RabbitizerRegister_R4000AllegrexVConstant_Names[reg_value as usize][1],
|
||||
)
|
||||
.to_str()
|
||||
.unwrap()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn descriptor(&self) -> &RegisterDescriptor {
|
||||
let reg_value: u32 = (*self).into();
|
||||
|
||||
unsafe {
|
||||
RabbitizerRegister_R4000AllegrexVConstant_Descriptors.get_unchecked(reg_value as usize)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl registers_enum::registers::R5900VF {
|
||||
pub fn name(self) -> &'static str {
|
||||
let reg_value: u32 = self.into();
|
||||
|
||||
@ -26,6 +26,7 @@ RabbitizerConfig RabbitizerConfig_Cfg = {
|
||||
.userFpcCsr = true,
|
||||
.vr4300Cop0NamedRegisters = true,
|
||||
.vr4300RspCop0NamedRegisters = true,
|
||||
.r4000AllegrexVfpuControlNamedRegisters = false,
|
||||
},
|
||||
.pseudos = {
|
||||
.enablePseudos = true,
|
||||
|
||||
@ -76,3 +76,79 @@ size_t RabbitizerUtils_escapeString(char *dst, size_t dstSize, const char *src,
|
||||
|
||||
return dstpos;
|
||||
}
|
||||
|
||||
uint32_t RabbitizerUtils_floatRepr_32From16(uint16_t arg) {
|
||||
// IEEE754 16-bit floats are encoded in 16 bits as follows:
|
||||
// Sign bit: 1 bit (bit 15)
|
||||
// Encoded exponent: 5 bits (bits 10 ~ 15)
|
||||
// Fraction/Mantissa: 10 bits (bits 0 ~ 9)
|
||||
|
||||
uint32_t ret;
|
||||
int32_t sign;
|
||||
int32_t encodedExponent;
|
||||
int32_t realExponent;
|
||||
bool mantissaIsZero;
|
||||
|
||||
// arg.d = a;
|
||||
|
||||
ret = 0;
|
||||
|
||||
sign = arg >> 15;
|
||||
|
||||
// If parameter is zero, then return zero
|
||||
if ((arg & ~(1ULL << 15)) == 0) {
|
||||
// Preserve the sign
|
||||
ret |= (sign << 31);
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Clear up the sign
|
||||
arg &= ~(1ULL << 15);
|
||||
|
||||
encodedExponent = arg >> 10;
|
||||
// Clear up the encoded exponent
|
||||
arg &= ~0x7C00ULL;
|
||||
|
||||
// Exponent bias: 0xF
|
||||
realExponent = encodedExponent - 0xF;
|
||||
|
||||
mantissaIsZero = (arg == 0);
|
||||
|
||||
if (encodedExponent == 0) {
|
||||
// subnormals
|
||||
|
||||
ret |= ((uint32_t)sign) << 31;
|
||||
// no need to set the exponent part since it was already zero'd
|
||||
|
||||
// Set the mantissa
|
||||
ret |= arg >> (23 - 10);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (encodedExponent == 0x1F) {
|
||||
// Infinity and NaN
|
||||
|
||||
ret |= ((uint32_t)sign) << 31;
|
||||
ret |= 0x7F800000ULL;
|
||||
|
||||
if (!mantissaIsZero) {
|
||||
// NaN
|
||||
|
||||
// Set the mantissa to any non-zero value
|
||||
ret |= arg << (23 - 10);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret |= ((uint32_t)sign) << 31;
|
||||
|
||||
// re-encode the exponent
|
||||
ret |= ((uint32_t)(realExponent + 0x7F)) << 23;
|
||||
|
||||
// Set the mantissa
|
||||
ret |= arg << (23 - 10);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -43,6 +43,12 @@ bool RabbitizerInstrDescriptor_hasOperandAlias(const RabbitizerInstrDescriptor *
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_rsp_maybe_rd_rs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_offset14_base)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_cpu_immediate:
|
||||
@ -264,6 +270,149 @@ bool RabbitizerInstrDescriptor_hasOperandAlias(const RabbitizerInstrDescriptor *
|
||||
break;
|
||||
/* r3000gte */
|
||||
|
||||
/* r4000allegrex */
|
||||
case RAB_OPERAND_r4000allegrex_s_vs:
|
||||
case RAB_OPERAND_r4000allegrex_s_vt:
|
||||
case RAB_OPERAND_r4000allegrex_s_vd:
|
||||
case RAB_OPERAND_r4000allegrex_s_vt_imm:
|
||||
case RAB_OPERAND_r4000allegrex_s_vd_imm:
|
||||
case RAB_OPERAND_r4000allegrex_p_vs:
|
||||
case RAB_OPERAND_r4000allegrex_p_vt:
|
||||
case RAB_OPERAND_r4000allegrex_p_vd:
|
||||
case RAB_OPERAND_r4000allegrex_t_vs:
|
||||
case RAB_OPERAND_r4000allegrex_t_vt:
|
||||
case RAB_OPERAND_r4000allegrex_t_vd:
|
||||
case RAB_OPERAND_r4000allegrex_q_vs:
|
||||
case RAB_OPERAND_r4000allegrex_q_vt:
|
||||
case RAB_OPERAND_r4000allegrex_q_vd:
|
||||
case RAB_OPERAND_r4000allegrex_q_vt_imm:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_cop2cs:
|
||||
case RAB_OPERAND_r4000allegrex_cop2cd:
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_pos:
|
||||
case RAB_OPERAND_r4000allegrex_size:
|
||||
case RAB_OPERAND_r4000allegrex_size_plus_pos:
|
||||
case RAB_OPERAND_r4000allegrex_imm3:
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_offset14_base:
|
||||
if (RabbitizerInstrDescriptor_hasOperandAlias(self, RAB_OPERAND_cpu_rs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb:
|
||||
if (RabbitizerInstrDescriptor_hasOperandAlias(self, RAB_OPERAND_cpu_rs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_offset14_base)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond:
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self,
|
||||
RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt:
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_vcmp_cond)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_s_vs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_s_vt)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt:
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_vcmp_cond)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_p_vs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_p_vt)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt:
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_vcmp_cond)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_t_vs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_t_vt)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt:
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_vcmp_cond)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_q_vs)) {
|
||||
return true;
|
||||
}
|
||||
if (RabbitizerInstrDescriptor_hasSpecificOperand(self, RAB_OPERAND_r4000allegrex_q_vt)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vconstant:
|
||||
case RAB_OPERAND_r4000allegrex_power_of_two:
|
||||
case RAB_OPERAND_r4000allegrex_vfpu_cc_bit:
|
||||
case RAB_OPERAND_r4000allegrex_bn:
|
||||
case RAB_OPERAND_r4000allegrex_int16:
|
||||
case RAB_OPERAND_r4000allegrex_float16:
|
||||
case RAB_OPERAND_r4000allegrex_p_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_t_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_q_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_rpx:
|
||||
case RAB_OPERAND_r4000allegrex_rpy:
|
||||
case RAB_OPERAND_r4000allegrex_rpz:
|
||||
case RAB_OPERAND_r4000allegrex_rpw:
|
||||
case RAB_OPERAND_r4000allegrex_wpx:
|
||||
case RAB_OPERAND_r4000allegrex_wpy:
|
||||
case RAB_OPERAND_r4000allegrex_wpz:
|
||||
case RAB_OPERAND_r4000allegrex_wpw:
|
||||
break;
|
||||
/* r4000allegrex */
|
||||
|
||||
/* r5900 */
|
||||
case RAB_OPERAND_r5900_I:
|
||||
case RAB_OPERAND_r5900_Q:
|
||||
|
||||
@ -16,10 +16,12 @@ bool RabbitizerInstrId_isValid(RabbitizerInstrId uniqueId) {
|
||||
case RABBITIZER_INSTR_ID_rsp_INVALID:
|
||||
case RABBITIZER_INSTR_ID_r3000gte_INVALID:
|
||||
case RABBITIZER_INSTR_ID_r5900_INVALID:
|
||||
case RABBITIZER_INSTR_ID_r4000allegrex_INVALID:
|
||||
case RABBITIZER_INSTR_ID_cpu_MAX:
|
||||
case RABBITIZER_INSTR_ID_rsp_MAX:
|
||||
case RABBITIZER_INSTR_ID_r3000gte_MAX:
|
||||
case RABBITIZER_INSTR_ID_r5900_MAX:
|
||||
case RABBITIZER_INSTR_ID_r4000allegrex_MAX:
|
||||
// case RABBITIZER_INSTR_ID_ALL_MAX: Same as last MAX
|
||||
return false;
|
||||
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
#include "instructions/RabbitizerRegister.h"
|
||||
#include "instructions/RabbitizerInstructionRsp.h"
|
||||
#include "instructions/RabbitizerInstructionR3000GTE.h"
|
||||
#include "instructions/RabbitizerInstructionR4000Allegrex.h"
|
||||
#include "instructions/RabbitizerInstructionR5900.h"
|
||||
|
||||
void RabbitizerInstruction_init(RabbitizerInstruction *self, uint32_t word, uint32_t vram) {
|
||||
@ -355,6 +356,155 @@ void RabbitizerInstruction_blankOut(RabbitizerInstruction *self) {
|
||||
break;
|
||||
/* r3000gte */
|
||||
|
||||
/* r4000allegrex */
|
||||
case RAB_OPERAND_r4000allegrex_s_vs:
|
||||
case RAB_OPERAND_r4000allegrex_p_vs:
|
||||
case RAB_OPERAND_r4000allegrex_t_vs:
|
||||
case RAB_OPERAND_r4000allegrex_q_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vs_transpose:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vs(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vt:
|
||||
case RAB_OPERAND_r4000allegrex_p_vt:
|
||||
case RAB_OPERAND_r4000allegrex_t_vt:
|
||||
case RAB_OPERAND_r4000allegrex_q_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vt:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vt(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vd:
|
||||
case RAB_OPERAND_r4000allegrex_p_vd:
|
||||
case RAB_OPERAND_r4000allegrex_t_vd:
|
||||
case RAB_OPERAND_r4000allegrex_q_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vd:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vd(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vt_imm:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vt_imm(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vd_imm:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vd_imm(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_q_vt_imm:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vt_6_imm(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_cop2cd:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_cop2cd(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_cop2cs:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_cop2cs(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_pos:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_pos(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_size:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_size(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_size_plus_pos:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_size_plus_pos(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_imm3:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_imm3(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_wb(self->word, 0);
|
||||
FALLTHROUGH;
|
||||
case RAB_OPERAND_r4000allegrex_offset14_base:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_offset14(self->word, 0);
|
||||
self->word = RAB_INSTR_PACK_rs(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt:
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt:
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt:
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vs(self->word, 0);
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vt(self->word, 0);
|
||||
FALLTHROUGH;
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vcmp_cond(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vconstant:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vconstant(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_power_of_two:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_power_of_two(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vfpu_cc_bit:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vfpu_cc_bit(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_bn:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_bn(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_int16:
|
||||
case RAB_OPERAND_r4000allegrex_float16:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_intfloat16(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_p_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_t_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_q_vrot_code:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_vrot_code(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpx:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_rpx(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpy:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_rpy(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpz:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_rpz(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpw:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_rpw(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpx:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_wpx(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpy:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_wpy(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpz:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_wpz(self->word, 0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpw:
|
||||
self->word = RAB_INSTR_R4000ALLEGREX_PACK_wpw(self->word, 0);
|
||||
break;
|
||||
/* r4000allegrex */
|
||||
|
||||
/* r5900 */
|
||||
case RAB_OPERAND_r5900_I:
|
||||
case RAB_OPERAND_r5900_Q:
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#include "common/RabbitizerConfig.h"
|
||||
#include "instructions/RabbitizerInstructionRsp.h"
|
||||
#include "instructions/RabbitizerInstructionR3000GTE.h"
|
||||
#include "instructions/RabbitizerInstructionR4000Allegrex.h"
|
||||
#include "instructions/RabbitizerInstructionR5900.h"
|
||||
#include "instructions/RabbitizerRegister.h"
|
||||
|
||||
@ -401,6 +402,155 @@ uint32_t RabbitizerInstruction_getValidBits(const RabbitizerInstruction *self) {
|
||||
break;
|
||||
/* r3000gte */
|
||||
|
||||
/* r4000allegrex */
|
||||
case RAB_OPERAND_r4000allegrex_s_vs:
|
||||
case RAB_OPERAND_r4000allegrex_p_vs:
|
||||
case RAB_OPERAND_r4000allegrex_t_vs:
|
||||
case RAB_OPERAND_r4000allegrex_q_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vs:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vs_transpose:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vs_transpose:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vs(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vt:
|
||||
case RAB_OPERAND_r4000allegrex_p_vt:
|
||||
case RAB_OPERAND_r4000allegrex_t_vt:
|
||||
case RAB_OPERAND_r4000allegrex_q_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vt:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vt:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vt(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vd:
|
||||
case RAB_OPERAND_r4000allegrex_p_vd:
|
||||
case RAB_OPERAND_r4000allegrex_t_vd:
|
||||
case RAB_OPERAND_r4000allegrex_q_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mp_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mt_vd:
|
||||
case RAB_OPERAND_r4000allegrex_mq_vd:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vd(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vt_imm:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vt_imm(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_s_vd_imm:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vd_imm(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_q_vt_imm:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vt_6_imm(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_cop2cs:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_cop2cs(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_cop2cd:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_cop2cd(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_pos:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_pos(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_size:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_size(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_size_plus_pos:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_size_plus_pos(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_imm3:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_imm3(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_wb(validbits, ~0);
|
||||
FALLTHROUGH;
|
||||
case RAB_OPERAND_r4000allegrex_offset14_base:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_offset14(validbits, ~0);
|
||||
validbits = RAB_INSTR_PACK_rs(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_s_maybe_vs_maybe_vt:
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_p_maybe_vs_maybe_vt:
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_t_maybe_vs_maybe_vt:
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond_q_maybe_vs_maybe_vt:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vs(validbits, ~0);
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vt(validbits, ~0);
|
||||
FALLTHROUGH;
|
||||
case RAB_OPERAND_r4000allegrex_vcmp_cond:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vcmp_cond(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vconstant:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vconstant(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_power_of_two:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_power_of_two(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_vfpu_cc_bit:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vfpu_cc_bit(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_bn:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_bn(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_int16:
|
||||
case RAB_OPERAND_r4000allegrex_float16:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_intfloat16(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_p_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_t_vrot_code:
|
||||
case RAB_OPERAND_r4000allegrex_q_vrot_code:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_vrot_code(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpx:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_rpx(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpy:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_rpy(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpz:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_rpz(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_rpw:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_rpw(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpx:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_wpx(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpy:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_wpy(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpz:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_wpz(validbits, ~0);
|
||||
break;
|
||||
|
||||
case RAB_OPERAND_r4000allegrex_wpw:
|
||||
validbits = RAB_INSTR_R4000ALLEGREX_PACK_wpw(validbits, ~0);
|
||||
break;
|
||||
/* r4000allegrex */
|
||||
|
||||
/* r5900 */
|
||||
case RAB_OPERAND_r5900_I:
|
||||
case RAB_OPERAND_r5900_Q:
|
||||
|
||||
@ -166,6 +166,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor0_BC0(RabbitizerInstructio
|
||||
switch (fmt) {
|
||||
#include "tables/instr_id/cpu/cpu_cop0_bc0.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor0_Tlb(RabbitizerInstruction *self) {
|
||||
@ -177,6 +179,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor0_Tlb(RabbitizerInstructio
|
||||
switch (function) {
|
||||
#include "tables/instr_id/cpu/cpu_cop0_tlb.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor0(RabbitizerInstruction *self) {
|
||||
@ -210,6 +214,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_BC1(RabbitizerInstructio
|
||||
switch (fmt) {
|
||||
#include "tables/instr_id/cpu/cpu_cop1_bc1.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuS(RabbitizerInstruction *self) {
|
||||
@ -221,6 +227,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuS(RabbitizerInstructi
|
||||
switch (function) {
|
||||
#include "tables/instr_id/cpu/cpu_cop1_fpu_s.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuD(RabbitizerInstruction *self) {
|
||||
@ -232,6 +240,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuD(RabbitizerInstructi
|
||||
switch (function) {
|
||||
#include "tables/instr_id/cpu/cpu_cop1_fpu_d.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuW(RabbitizerInstruction *self) {
|
||||
@ -243,6 +253,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuW(RabbitizerInstructi
|
||||
switch (function) {
|
||||
#include "tables/instr_id/cpu/cpu_cop1_fpu_w.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuL(RabbitizerInstruction *self) {
|
||||
@ -254,6 +266,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuL(RabbitizerInstructi
|
||||
switch (function) {
|
||||
#include "tables/instr_id/cpu/cpu_cop1_fpu_l.inc"
|
||||
}
|
||||
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
}
|
||||
|
||||
void RabbitizerInstruction_processUniqueId_Coprocessor1(RabbitizerInstruction *self) {
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
#include "instructions/RabbitizerInstructionR4000Allegrex.h"
|
||||
|
||||
void RabbitizerInstructionR4000Allegrex_init(RabbitizerInstruction *self, uint32_t word, uint32_t vram) {
|
||||
RabbitizerInstruction_init(self, word, vram);
|
||||
|
||||
self->uniqueId = RABBITIZER_INSTR_ID_r4000allegrex_INVALID;
|
||||
self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
|
||||
|
||||
self->category = RABBITIZER_INSTRCAT_R4000ALLEGREX;
|
||||
}
|
||||
|
||||
void RabbitizerInstructionR4000Allegrex_destroy(RabbitizerInstruction *self) {
|
||||
RabbitizerInstruction_destroy(self);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -101,6 +101,65 @@ const char *RabbitizerRegister_getNameRspVector(uint8_t regValue) {
|
||||
return RabbitizerRegister_RspVector_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexS(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexS_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexS_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexV2D(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexV2D_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexV2D_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexV3D(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexV3D_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexV3D_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexV4D(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexV4D_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexV4D_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexM2x2(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexM2x2_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexM2x2_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexM3x3(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexM3x3_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexM3x3_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexM4x4(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexM4x4_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexM4x4_Names[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexVfpuControl(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexVfpuControl_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexVfpuControl_Names
|
||||
[regValue][RabbitizerConfig_Cfg.regNames.namedRegisters &&
|
||||
RabbitizerConfig_Cfg.regNames.r4000AllegrexVfpuControlNamedRegisters
|
||||
? 1
|
||||
: 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR4000AllegrexVConstant(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexVConstant_Names));
|
||||
|
||||
return RabbitizerRegister_R4000AllegrexVConstant_Names[regValue]
|
||||
[RabbitizerConfig_Cfg.regNames.namedRegisters ? 1 : 0];
|
||||
}
|
||||
|
||||
const char *RabbitizerRegister_getNameR5900VF(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R5900VF_Names));
|
||||
|
||||
@ -186,6 +245,60 @@ const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_RspVector(u
|
||||
return &RabbitizerRegister_RspVector_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexS(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexS_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexS_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexV2D(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexV2D_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexV2D_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexV3D(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexV3D_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexV3D_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexV4D(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexV4D_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexV4D_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexM2x2(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexM2x2_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexM2x2_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexM3x3(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexM3x3_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexM3x3_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexM4x4(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexM4x4_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexM4x4_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexVfpuControl(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexVfpuControl_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexVfpuControl_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R4000AllegrexVConstant(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R4000AllegrexVConstant_Names));
|
||||
|
||||
return &RabbitizerRegister_R4000AllegrexVConstant_Descriptors[regValue];
|
||||
}
|
||||
|
||||
const RabbitizerRegisterDescriptor *RabbitizerRegister_getDescriptor_R5900VF(uint8_t regValue) {
|
||||
assert(regValue < ARRAY_COUNT(RabbitizerRegister_R5900VF_Names));
|
||||
|
||||
|
||||
@ -4,4 +4,5 @@
|
||||
RABBITIZER_DEF_INSTR_CATEGORY(CPU)
|
||||
RABBITIZER_DEF_INSTR_CATEGORY(RSP) // N64
|
||||
RABBITIZER_DEF_INSTR_CATEGORY(R3000GTE) // R3000 CPU with PS1's Geometry Transformation Engine extension
|
||||
RABBITIZER_DEF_INSTR_CATEGORY(R4000ALLEGREX) // PSP's CPU
|
||||
RABBITIZER_DEF_INSTR_CATEGORY(R5900) // PS2's Emotion Engine
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
#include "instr_id_types/InstrIdType_cpu.inc"
|
||||
#include "instr_id_types/InstrIdType_rsp.inc"
|
||||
#include "instr_id_types/InstrIdType_r3000gte.inc"
|
||||
#include "instr_id_types/InstrIdType_r4000allegrex.inc"
|
||||
#include "instr_id_types/InstrIdType_r5900.inc"
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_TYPE(ALL, MAX)
|
||||
|
||||
@ -4,4 +4,5 @@
|
||||
#include "instr_id/RabbitizerInstrId_cpu.inc"
|
||||
#include "instr_id/RabbitizerInstrId_rsp.inc"
|
||||
#include "instr_id/RabbitizerInstrId_r3000gte.inc"
|
||||
#include "instr_id/RabbitizerInstrId_r4000allegrex.inc"
|
||||
#include "instr_id/RabbitizerInstrId_r5900.inc"
|
||||
|
||||
@ -4,4 +4,5 @@
|
||||
#include "operands/RabbitizerOperandType_cpu.inc"
|
||||
#include "operands/RabbitizerOperandType_rsp.inc"
|
||||
#include "operands/RabbitizerOperandType_r3000gte.inc"
|
||||
#include "operands/RabbitizerOperandType_r4000allegrex.inc"
|
||||
#include "operands/RabbitizerOperandType_r5900.inc"
|
||||
|
||||
@ -9,15 +9,18 @@
|
||||
#include "cpu/cpu_normal.inc"
|
||||
#include "cpu/cpu_special.inc"
|
||||
#include "cpu/cpu_regimm.inc"
|
||||
|
||||
#include "cpu/cpu_cop0.inc"
|
||||
#include "cpu/cpu_cop0_bc0.inc"
|
||||
#include "cpu/cpu_cop0_tlb.inc"
|
||||
|
||||
#include "cpu/cpu_cop1.inc"
|
||||
#include "cpu/cpu_cop1_bc1.inc"
|
||||
#include "cpu/cpu_cop1_fpu_s.inc"
|
||||
#include "cpu/cpu_cop1_fpu_d.inc"
|
||||
#include "cpu/cpu_cop1_fpu_w.inc"
|
||||
#include "cpu/cpu_cop1_fpu_l.inc"
|
||||
|
||||
#include "cpu/cpu_cop2.inc"
|
||||
|
||||
#ifndef INSTRID_AVOID_USERDEF
|
||||
|
||||
155
tables/tables/instr_id/RabbitizerInstrId_r4000allegrex.inc
Normal file
155
tables/tables/instr_id/RabbitizerInstrId_r4000allegrex.inc
Normal file
@ -0,0 +1,155 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , INVALID,
|
||||
.operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_immediate},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_UNKNOWN
|
||||
)
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_normal.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_special.inc"
|
||||
#include "r4000allegrex/r4000allegrex_special_rs.inc"
|
||||
#include "r4000allegrex/r4000allegrex_special_sa.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_regimm.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_special2.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_special3.inc"
|
||||
#include "r4000allegrex/r4000allegrex_special3_bshfl.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_cop0.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop0_bc0.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop0_tlb.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_cop1.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop1_bc1.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop1_fpu_s.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop1_fpu_w.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_cop2.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop2_bc2.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop2_mfhc2.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop2_mfhc2_p.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop2_mfhc2_p_s.inc"
|
||||
#include "r4000allegrex/r4000allegrex_cop2_mthc2.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_vfpu0.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu1.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu3.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_fmt0.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_fmt2.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_fmt3.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_rnd.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_cvtflt.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_cvtint.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_fmt8.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_fmt9.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_control.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_color.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt0_cst.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt2.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu4_fmt2_cndmove.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_vfpu5.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_vfpu6.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu6_fmt7.inc"
|
||||
#include "r4000allegrex/r4000allegrex_vfpu6_fmt7_fmt0.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_vfpu7.inc"
|
||||
|
||||
#include "r4000allegrex/r4000allegrex_quadlr.inc"
|
||||
|
||||
#ifndef INSTRID_AVOID_USERDEF
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_00,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_01,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_02,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_03,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_04,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_05,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_06,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_07,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_08,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_09,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_10,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_11,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_12,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_13,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_14,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_15,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_16,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_17,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_18,
|
||||
.operands={0}
|
||||
)
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , USERDEF_19,
|
||||
.operands={0}
|
||||
)
|
||||
#endif
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, , MAX,
|
||||
.operands={0}
|
||||
)
|
||||
@ -16,6 +16,7 @@
|
||||
111 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// OP
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
cpu, 0x01, tlbr,
|
||||
|
||||
@ -11,8 +11,10 @@
|
||||
10 | *2 | *3 | --- | --- | *4 | *5 | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 = BC instructions, see BC1 list *2 = S instr, see FPU S list
|
||||
*3 = D instr, see FPU D list *4 = W instr, see FPU W list
|
||||
*1 = BC instructions, see BC1 list
|
||||
*2 = S instr, see FPU S list
|
||||
*3 = D instr, see FPU D list
|
||||
*4 = W instr, see FPU W list
|
||||
*5 = L instr, see FPU L list
|
||||
*/
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
/*
|
||||
31----------26-25--------21 -----------------------------------------5----------0
|
||||
| = COP1 | = S | | function |
|
||||
| = COP1 | = D | | function |
|
||||
-------6------------5-----------------------------------------------------6------
|
||||
|---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
|
||||
000 | ADD.D | SUB.D | MUL.D | DIV.D | SQRT.D | ABS.D | MOV.D | NEG.D |
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
/*
|
||||
31----------26-25--------21 -----------------------------------------5----------0
|
||||
| = COP1 | = S | | function |
|
||||
| = COP1 | = L | | function |
|
||||
-------6------------5-----------------------------------------------------6------
|
||||
|---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
|
||||
000 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
/*
|
||||
31----------26-25--------21 -----------------------------------------5----------0
|
||||
| = COP1 | = S | | function |
|
||||
| = COP1 | = W | | function |
|
||||
-------6------------5-----------------------------------------------------6------
|
||||
|---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
|
||||
000 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
| = COP0 | fmt | |
|
||||
------6----------5-----------------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | MFC2 | --- | CFC0 | --- | MTC2 | --- | CTC2 | --- |
|
||||
00 | MFC2 | --- | CFC2 | --- | MTC2 | --- | CTC2 | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ |
|
||||
001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI |
|
||||
010 | *3 | *4 | *5 | --- | BEQL | BNEL | BLEZL | BGTZL |
|
||||
011 | DADDI |DADDIU | LDL | LDR | --- | --- | --- | --- |
|
||||
011 | DADDI | DADDIU| LDL | LDR | --- | --- | --- | --- |
|
||||
100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU |
|
||||
101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE |
|
||||
110 | LL | LWC1 | LWC2 | PREF | LLD | LDC1 | LDC2 | LD |
|
||||
|
||||
17
tables/tables/instr_id/r4000allegrex/r4000allegrex_cop0.inc
Normal file
17
tables/tables/instr_id/r4000allegrex/r4000allegrex_cop0.inc
Normal file
@ -0,0 +1,17 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 ----------------------------------------0
|
||||
| = COP0 | fmt | |
|
||||
------6----------5-----------------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | MFC0 | --- | --- | --- | MTC0 | --- | --- | --- |
|
||||
01 | *1 | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1=BC See BC0 list
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
@ -0,0 +1,16 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21-20------16------------------------------0
|
||||
| = COP0 | BC0 | fmt | |
|
||||
------6----------5----------5------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | BC0F | BC0T | BC0FL | BC0TL | --- | --- | --- | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
@ -0,0 +1,20 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21--------------------------------5--------0
|
||||
| = COP0 | TLB | | fmt |
|
||||
------6----------5-----------------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
000 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
001 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
010 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
011 | ERET | --- | --- | --- | --- | --- | --- | --- |
|
||||
100 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
101 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
111 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
25
tables/tables/instr_id/r4000allegrex/r4000allegrex_cop1.inc
Normal file
25
tables/tables/instr_id/r4000allegrex/r4000allegrex_cop1.inc
Normal file
@ -0,0 +1,25 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 ----------------------------------------0
|
||||
| = COP1 | fmt | |
|
||||
------6----------5-----------------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | MFC1 | --- | CFC1 | MFHC1 | MTC1 | --- | CTC1 | MTHC1 |
|
||||
01 | *1 | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | *2 | --- | --- | --- | *3 | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 = BC See BC1 list
|
||||
*2 = S instr, see FPU S list
|
||||
*3 = W instr, see FPU W list
|
||||
*/
|
||||
|
||||
/*
|
||||
TODO:
|
||||
- MFHC1
|
||||
- MTHC1
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
@ -0,0 +1,16 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21-20------16------------------------------0
|
||||
| = COP1 | BC1 | fmt | |
|
||||
------6----------5----------5------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | BC1F | BC1T | BC1FL | BC1TL | --- | --- | --- | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
@ -0,0 +1,20 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31----------26-25--------21 -----------------------------------------5----------0
|
||||
| = COP1 | = S | | function |
|
||||
-------6------------5-----------------------------------------------------6------
|
||||
|---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
|
||||
000 | ADD.S | SUB.S | MUL.S | DIV.S | SQRT.S | ABS.S | MOV.S | NEG.S |
|
||||
001 | --- | --- | --- | --- |ROUND.W.S|TRUNC.W.S| CEIL.W.S|FLOOR.W.S|
|
||||
010 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
011 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
100 | --- | --- | --- | --- | CVT.W.S | --- | --- | --- |
|
||||
101 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
110 | C.F.S | C.UN.S | C.EQ.S | C.UEQ.S | C.OLT.S | C.ULT.S | C.OLE.S | C.ULE.S |
|
||||
111 | C.SF.S | C.NGLE.S| C.SEQ.S | C.NGL.S | C.LT.S | C.NGE.S | C.LE.S | C.NGT.S |
|
||||
hi |---------|---------|---------|---------|---------|---------|---------|---------|
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
@ -0,0 +1,20 @@
|
||||
/* SPDX-FileCopyrightText: © 2022-2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31----------26-25--------21 -----------------------------------------5----------0
|
||||
| = COP1 | = W | | function |
|
||||
-------6------------5-----------------------------------------------------6------
|
||||
|---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
|
||||
000 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
001 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
010 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
011 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
100 | CVT.S.W | --- | --- | --- | --- | --- | --- | --- |
|
||||
101 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
111 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |---------|---------|---------|---------|---------|---------|---------|---------|
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
19
tables/tables/instr_id/r4000allegrex/r4000allegrex_cop2.inc
Normal file
19
tables/tables/instr_id/r4000allegrex/r4000allegrex_cop2.inc
Normal file
@ -0,0 +1,19 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 ----------------------------------------0
|
||||
| = COP2 | fmt | |
|
||||
------6----------5-----------------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | MFC2 | --- | CFC2 | *2 | MTC2 | --- | CTC2 | *3 |
|
||||
01 | *1 | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 = See BC2 table
|
||||
*2 = See MFHC2 table
|
||||
*3 = See MTHC2 table
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
@ -0,0 +1,40 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25-----21------17-16-------------------------------0
|
||||
| = COP2 | BC2 | |fmt| |
|
||||
------6----------5------------2----------------------------------
|
||||
|---------------0---------------|---------------1---------------| lo
|
||||
0 | BVF | BVT |
|
||||
1 | BVFL | BVTL |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// OP IMM
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x00, bvf,
|
||||
.operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_UNKNOWN,
|
||||
.isBranch=true
|
||||
) // Branch on Vfpu False
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x01, bvt,
|
||||
.operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_UNKNOWN,
|
||||
.isBranch=true
|
||||
) // Branch on Vfpu True
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x02, bvfl,
|
||||
.operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_UNKNOWN,
|
||||
.isBranch=true,
|
||||
.isBranchLikely=true
|
||||
) // Branch on Vfpu False Likely
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x03, bvtl,
|
||||
.operands={RAB_OPERAND_r4000allegrex_imm3, RAB_OPERAND_cpu_branch_target_label},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_UNKNOWN,
|
||||
.isBranch=true,
|
||||
.isBranchLikely=true
|
||||
) // Branch on Vfpu True Likely
|
||||
@ -0,0 +1,26 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 -------------------------7--------------0
|
||||
| = COP2 | MFHC2 | |p| |
|
||||
------6----------5-------------------------------1---------------
|
||||
|---------------0---------------|---------------1---------------| p
|
||||
| mfv | *1 |
|
||||
|-------------------------------|-------------------------------|
|
||||
*1 = See P table
|
||||
*/
|
||||
|
||||
/*
|
||||
mfv
|
||||
31--------26-25-----21-20-----16-----------------7-6------------0
|
||||
| COP2 |0 0 0 1 1| rt |0 0 0 0 0 0 0 0|0| vd |
|
||||
------6----------5---------5---------------------1-------7-------
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0, mfv,
|
||||
.operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_s_vd},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRt=true
|
||||
) // Move word From Vfpu
|
||||
@ -0,0 +1,26 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 -------------------------7-6---4--------0
|
||||
| = COP2 | MFHC2 | |1| fmt | |
|
||||
------6----------5-------------------------------1---3-----------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| fmt
|
||||
| mfvc | --- | --- | --- | --- | --- | --- | *1 |
|
||||
|-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 See S list
|
||||
*/
|
||||
|
||||
/*
|
||||
mfvc
|
||||
31--------26-25-----21-20-----16-----------------7-6------------0
|
||||
| COP2 |0 0 0 1 1| rt |0 0 0 0 0 0 0 0|1| cop2cd |
|
||||
------6----------5---------5---------------------1-------7-------
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x0, mfvc,
|
||||
.operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_cop2cd},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRt=true
|
||||
) // Move word From Vfpu Control
|
||||
@ -0,0 +1,25 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 -------------------------7-6---4--------0
|
||||
| = COP2 | MFHC2 | |1|1 1 1| fmt |
|
||||
------6----------5-------------------------------1---3------4----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
0 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
1 | --- | --- | --- | --- | --- | --- | --- | vsync2|
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
/*
|
||||
vsync2
|
||||
31--------26-25-----21---------------------------7-6---4-3------0
|
||||
| COP2 |0 0 0 1 1| |1|1 1 1|1 1 1 1|
|
||||
------6----------5---------5---------------------1---3------4----
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0xF, vsync2,
|
||||
.operands={0},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R
|
||||
) // SYNChronize2
|
||||
@ -0,0 +1,39 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25------21 -------------------------7--------------0
|
||||
| = COP2 | MFHC2 | |p| |
|
||||
------6----------5-------------------------------1---------------
|
||||
|---------------0---------------|---------------1---------------| p
|
||||
| mtv | mtvc |
|
||||
|-------------------------------|-------------------------------|
|
||||
*/
|
||||
|
||||
/*
|
||||
mtv
|
||||
31--------26-25-----21-20-----16-----------------7-6------------0
|
||||
| COP2 |0 0 1 1 1| rt |0 0 0 0 0 0 0 0|0| vd |
|
||||
------6----------5---------5---------------------1-------7-------
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x0, mtv,
|
||||
.operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_s_vd},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRt=true
|
||||
) // Move word To Vfpu
|
||||
|
||||
/*
|
||||
mtvc
|
||||
31--------26-25-----21-20-----16-----------------7-6------------0
|
||||
| COP2 |0 0 1 1 1| rt |0 0 0 0 0 0 0 0|1| cop2cd |
|
||||
------6----------5---------5---------------------1-------7-------
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x1, mtvc,
|
||||
.operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_r4000allegrex_cop2cd},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRt=true
|
||||
) // Move word To Vfpu Control
|
||||
@ -0,0 +1,67 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26---------------------------------------------------0
|
||||
| opcode | |
|
||||
------6----------------------------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ |
|
||||
001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI |
|
||||
010 | *3 | *4 | *5 | --- | BEQL | BNEL | BLEZL | BGTZL |
|
||||
011 | *6 | *7 | --- | *8 | *9 | --- | --- | *10 |
|
||||
100 | LB | LH | LWL | LW | LBU | LHU | LWR | --- |
|
||||
101 | SB | SH | SWL | SW | --- | --- | SWR | CACHE |
|
||||
110 | LL | LWC1 | LV.S | --- | *11 | --- | LV.Q | *12 |
|
||||
111 | SC | SWC1 | SV.S | --- | *13 | *14 | SV.Q | *15 |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 = SPECIAL, see SPECIAL list
|
||||
*2 = REGIMM, see REGIMM list
|
||||
*3 = COP0
|
||||
*4 = COP1
|
||||
*5 = COP2
|
||||
*6 = VFPU0
|
||||
*7 = VFPU1
|
||||
*8 = VFPU3
|
||||
*9 = SPECIAL2
|
||||
*10 = SPECIAL3
|
||||
*11 = VFPU4
|
||||
*12 = VFPU5
|
||||
*13 = VFPU6 (Matrix operations)
|
||||
*14 = QUADLR
|
||||
*15 = VFPU7
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
|
||||
// OP vt, offset_14(base)
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_ALTNAME(
|
||||
r4000allegrex, 0x32, lv_s, lv.s,
|
||||
.operands={RAB_OPERAND_r4000allegrex_s_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_I,
|
||||
.readsRs=true
|
||||
) // Load Single word to Vfpu
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_ALTNAME(
|
||||
r4000allegrex, 0x3A, sv_s, sv.s,
|
||||
.operands={RAB_OPERAND_r4000allegrex_s_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_I,
|
||||
.modifiesRs=true
|
||||
) // Store Single word to Vfpu
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_ALTNAME(
|
||||
r4000allegrex, 0x36, lv_q, lv.q,
|
||||
.operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_I,
|
||||
.readsRs=true
|
||||
) // Load Single word to Vfpu
|
||||
|
||||
// OP vt, offset_14(base), maybe_wb
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_ALTNAME(
|
||||
r4000allegrex, 0x3E, sv_q, sv.q,
|
||||
.operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base_maybe_wb},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_I,
|
||||
.modifiesRs=true
|
||||
) // Store Single word to Vfpu
|
||||
@ -0,0 +1,25 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26-----------------------------------------------2-1-0
|
||||
| = QUADLR | |Z| |
|
||||
------6------------------------------------------------------1---
|
||||
|---------------0---------------|---------------1---------------| lo
|
||||
| SVL.Q | SVR.Q |
|
||||
|-------------------------------|-------------------------------|
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_ALTNAME(
|
||||
r4000allegrex, 0, svl_q, svl.q,
|
||||
.operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_I,
|
||||
.readsRs=true
|
||||
) // Store Quad word Left from Vfpu
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID_ALTNAME(
|
||||
r4000allegrex, 1, svr_q, svr.q,
|
||||
.operands={RAB_OPERAND_r4000allegrex_q_vt_imm, RAB_OPERAND_r4000allegrex_offset14_base},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_I,
|
||||
.readsRs=true
|
||||
) // Store Quad word Right from Vfpu
|
||||
@ -0,0 +1,16 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26----------20-------16------------------------------0
|
||||
| = REGIMM | | rt | |
|
||||
------6---------------------5------------------------------------
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | BLTZ | BGEZ | BLTZL | BGEZL | --- | --- | --- | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | BLTZAL| BGEZAL|BLTZALL|BGEZALL| --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
102
tables/tables/instr_id/r4000allegrex/r4000allegrex_special.inc
Normal file
102
tables/tables/instr_id/r4000allegrex/r4000allegrex_special.inc
Normal file
@ -0,0 +1,102 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26------------------------------------------5--------0
|
||||
| = SPECIAL | | function|
|
||||
------6----------------------------------------------------6-----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
000 | SLL | --- | *1 | SRA | SLLV | --- | *2 | SRAV |
|
||||
001 | JR | JALR | MOVZ | MOVN |SYSCALL| BREAK | --- | SYNC |
|
||||
010 | MFHI | MTHI | MFLO | MTLO | --- | --- | CLZ | CLO |
|
||||
011 | MULT | MULTU | DIV | DIVU | MADD | MADDU | --- | --- |
|
||||
100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR |
|
||||
101 | --- | --- | SLT | SLTU | MAX | MIN | MSUB | MSUBU |
|
||||
110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
111 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 = SPECIAL rs, see SPECIAL rs list
|
||||
*2 = SPECIAL sa, see SPECIAL sa list
|
||||
*/
|
||||
|
||||
// The other instructions are implemented using the main CPU table
|
||||
|
||||
// OP rd, rs
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x16, clz,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRs=true
|
||||
) // Count Leading Zero
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x17, clo,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRs=true
|
||||
) // Count Leading One
|
||||
|
||||
// OP rs, rt
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x1C, madd,
|
||||
.operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRs=true,
|
||||
.readsRt=true,
|
||||
.modifiesHI=true,
|
||||
.modifiesLO=true
|
||||
) // Multiply ADD
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x1D, maddu,
|
||||
.operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRs=true,
|
||||
.readsRt=true,
|
||||
.modifiesHI=true,
|
||||
.modifiesLO=true
|
||||
) // Multiply ADD Unsigned
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x2E, msub,
|
||||
.operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRs=true,
|
||||
.readsRt=true,
|
||||
.modifiesHI=true,
|
||||
.modifiesLO=true
|
||||
) // Multiply SUBtract
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x2F, msubu,
|
||||
.operands={RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRs=true,
|
||||
.readsRt=true,
|
||||
.modifiesHI=true,
|
||||
.modifiesLO=true
|
||||
) // Multiply SUBtract Unsigned
|
||||
|
||||
// OP rd, rs, rt
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x2C, max,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRs=true,
|
||||
.readsRt=true
|
||||
) // select MAX
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x2D, min,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rs, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRs=true,
|
||||
.readsRt=true
|
||||
) // select MIN
|
||||
@ -0,0 +1,40 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26------------------------------------------5--------0
|
||||
| =SPECIAL2 | | function|
|
||||
------6----------------------------------------------------6-----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
000 | SLEEP | --- | --- | --- | --- | --- | --- | --- |
|
||||
001 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
010 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
011 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
100 | --- | --- | --- | --- | MFIE | --- | MTIE | --- |
|
||||
101 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
111 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// OP
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x00, sleep,
|
||||
.operands={0},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R
|
||||
)
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x24, mfie,
|
||||
.operands={RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRt=true
|
||||
)
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x26, mtie,
|
||||
.operands={RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.readsRt=true
|
||||
)
|
||||
@ -0,0 +1,35 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26------------------------------------------5--------0
|
||||
| =SPECIAL3 | | function|
|
||||
------6----------------------------------------------------6-----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
000 | EXT | --- | --- | --- | INS | --- | --- | --- |
|
||||
001 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
010 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
011 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
100 | *1 | --- | --- | --- | --- | --- | --- | --- |
|
||||
101 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
111 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*1 = SPECIAL3 BSHFL
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x00, ext,
|
||||
.operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs, RAB_OPERAND_r4000allegrex_pos, RAB_OPERAND_r4000allegrex_size},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRt=true,
|
||||
.readsRs=true
|
||||
) // EXTract bit field
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x04, ins,
|
||||
.operands={RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs, RAB_OPERAND_r4000allegrex_pos, RAB_OPERAND_r4000allegrex_size_plus_pos},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRt=true,
|
||||
.readsRs=true
|
||||
) // INSert bit field
|
||||
@ -0,0 +1,56 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26--------------------------------10------6-5--------0
|
||||
| =SPECIAL3 | | sa | = BSHFL |
|
||||
------6------------------------------------------5---------6-----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | --- | --- | WSBH | WSBW | --- | --- | --- | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | SEB | --- | --- | --- | BITREV| --- | --- | --- |
|
||||
11 | SEH | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
// OP rd, rt
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x02, wsbh,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // Word Swap Bytes within Halfword
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x03, wsbw,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // Word Swap Bytes within Word
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x10, seb,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // Sign-Extend Byte
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x18, seh,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // Sign-Extend Halfword
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x14, bitrev,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // BIT REVerse
|
||||
@ -0,0 +1,30 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31--------26-25-----21---------------------------------5--------0
|
||||
| = SPECIAL | rs | | 0x02 |
|
||||
------6----------5-----------------------------------------6-----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | srl | rotr | --- | --- | --- | --- | --- | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x00, srl,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_sa},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // Shift word Right Logical
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x01, rotr,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_sa},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRt=true
|
||||
) // ROTate word Right
|
||||
@ -0,0 +1,32 @@
|
||||
/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
/*
|
||||
31---------26--------------------------------10------6-5--------0
|
||||
| = SPECIAL | | sa | 0x06 |
|
||||
------6------------------------------------------5---------6-----
|
||||
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
00 | srlv | rotrv | --- | --- | --- | --- | --- | --- |
|
||||
01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
10 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
11 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
*/
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x00, srlv,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRs=true,
|
||||
.readsRt=true
|
||||
) // Shift word Right Logical Variable
|
||||
|
||||
RABBITIZER_DEF_INSTR_ID(
|
||||
r4000allegrex, 0x01, rotrv,
|
||||
.operands={RAB_OPERAND_cpu_rd, RAB_OPERAND_cpu_rt, RAB_OPERAND_cpu_rs},
|
||||
.instrType=RABBITIZER_INSTR_TYPE_R,
|
||||
.modifiesRd=true,
|
||||
.readsRs=true,
|
||||
.readsRt=true
|
||||
) // ROTate word Right Variable
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user