16 Commits

Author	SHA1	Message	Date
CTCaer	d37fe213d7	mtc: Name sdram ids	2020-06-14 17:39:39 +03:00
CTCaer	6e256d29c7	Utilize hekate's BDK for hekate main and Nyx	2020-06-14 16:45:45 +03:00
CTCaer	27926b0d55	Allow automatic inlining for modules	2020-06-13 18:40:09 +03:00
CTCaer	8ce6bf82a9	Minimize make info noise during building	2020-06-13 18:39:17 +03:00
CTCaer	a52af1bf41	Fix building on make 4.3	2020-03-04 01:34:35 +02:00
CTCaer	84328aa676	minerva: Make use of new minerva ... - Training and switch is now faster - Compatibility checks: New Minerva does not allow old binaries. New binaries do not allow old Minerva - MTC table is now in a safe region - Periodic training period increased to every 250ms	2019-12-04 21:56:45 +02:00
CTCaer	66c4f30bdf	minerva: Update to v1.2 and use only integers ... Additionally remove support for DRAM types that Switch platform does not have. This will reduce periodic training cost to 30us from 6ms.	2019-12-04 21:46:33 +02:00
Kostas Missos	7c42f72b8a	refactor: Remove all unwanted whitespace	2019-10-18 18:02:06 +03:00
ctcaer@gmail.com	52478833de	[MTC] Utilize Minerva Training Cell	2019-06-30 03:49:33 +03:00
Kostas Missos	cfef8b4f72	Update libminerva to v1.1	2018-11-10 13:30:17 +02:00
Kostas Missos	ec1bb508b3	Fix minerva build ... This is still for testing it out. The real usage will come later.	2018-11-05 10:54:31 +02:00
Kostas Missos	cae9044c17	Minerva our DRAM trainer ... Supports up to 1600MHz and periodic training. For more check here: https://github.com/CTCaer/minerva_tc	2018-11-04 03:15:32 +02:00
Kostas Missos	58b289bee2	Fix build pf sample module by adding missing files	2018-08-25 22:59:54 +03:00
Kostas Missos	1d623eacf9	Our 1st module. LP0 configuration.	2018-08-21 04:14:31 +03:00
Kostas Missos	e5abdd938e	Refactor ALL the things + enable LTO	2018-08-13 11:58:24 +03:00
M4xw	8b0915cb01	Implement elfloader/module support	2018-08-07 22:41:05 +02:00