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minerva: Update to v1.2 and use only integers

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Additionally remove support for DRAM types that Switch platform does not have.

This will reduce periodic training cost to 30us from 6ms.
This commit is contained in:
CTCaer 2019-12-04 21:46:33 +02:00
parent dd8ec0d28b
commit 66c4f30bdf
2 changed files with 356 additions and 499 deletions
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8
modules/hekate_libsys_minerva/mtc_mc_emc_regs.h
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@ -23,8 +23,9 @@
/* Clock controller registers */
#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
#define PLLM_ENABLE (1 << 30)
#define PLLM_LOCK (1 << 27)
#define PLLM_ENABLE (1 << 30)
#define PLLM_LOCK (1 << 27)
#define PLLM_EN_LCKDET (1 << 4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
#define EMC_2X_CLK_SRC_SHIFT 29
@ -34,6 +35,9 @@
#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
#define EMC_DLL_PLLM_VCOB (1 << 10)
#define EMC_DLL_SWITCH_OUT (1 << 11)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE 0x724
/* Memory controller registers */

847
modules/hekate_libsys_minerva/sys_sdrammtc.c
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