mirror of
https://github.com/CTCaer/hekate.git
synced 2024-09-03 05:19:18 +00:00
Our 1st module. LP0 configuration.
This commit is contained in:
parent
3d6216a6f3
commit
1d623eacf9
4
Makefile
4
Makefile
@ -31,7 +31,6 @@ OBJS = $(addprefix $(BUILD)/$(TARGET)/, \
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sdmmc.o \
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sdmmc_driver.o \
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sdram.o \
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sdram_lp0.o \
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tui.o \
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util.o \
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di.o \
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@ -43,6 +42,7 @@ OBJS = $(addprefix $(BUILD)/$(TARGET)/, \
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tsec.o \
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uart.o \
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ini.o \
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ianos.o \
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)
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OBJS += $(addprefix $(BUILD)/$(TARGET)/, \
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@ -53,7 +53,7 @@ OBJS += $(addprefix $(BUILD)/$(TARGET)/, \
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ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
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CUSTOMDEFINES := -DMENU_LOGO_ENABLE #-DDEBUG
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CFLAGS = $(ARCH) -O2 -nostdlib -flto -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
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CFLAGS = $(ARCH) -O2 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
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LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections
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MODULEDIRS := $(wildcard modules/*)
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@ -391,8 +391,6 @@ void config_hw()
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mc_config_carveout();
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sdram_init();
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sdram_lp0_save_params(sdram_get_params());
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}
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void reconfig_hw_workaround(bool extra_reconfig)
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@ -2615,6 +2613,9 @@ void ipl_main()
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//uart_send(UART_C, (u8 *)0x40000000, 0x10000);
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//uart_wait_idle(UART_C, UART_TX_IDLE);
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// Save sdram lp0 config.
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ianos_loader(true, "bootloader/sys/libsys_lp0.bso", DRAM_LIB, (void *)sdram_get_params());
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display_init();
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//display_color_screen(0xAABBCCDD);
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u32 *fb = display_init_framebuffer();
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32
modules/hekate_libsys_lp0/Makefile
Normal file
32
modules/hekate_libsys_lp0/Makefile
Normal file
@ -0,0 +1,32 @@
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ifeq ($(strip $(DEVKITARM)),)
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$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
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endif
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include $(DEVKITARM)/base_rules
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TARGET := libsys_lp0
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BUILD := ../../build/$(TARGET)
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OUTPUT := ../../output
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VPATH = $(dir $(wildcard ./*/)) $(dir $(wildcard ./*/*/))
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OBJS = $(addprefix $(BUILD)/,\
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sys_sdramlp0.o \
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)
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ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork
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CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
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LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc
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.PHONY: clean all
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all: $(TARGET).bso
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$(BUILD)/%.o: ./%.c
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@mkdir -p "$(BUILD)"
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$(CC) $(CFLAGS) -c $< -o $@
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$(TARGET).bso: $(OBJS)
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$(CC) $(LDFLAGS) -e _modInit $^ -o $(OUTPUT)/$(TARGET).bso
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$(STRIP) -g $(OUTPUT)/$(TARGET).bso
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clean:
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@rm -rf $(OUTPUT)/$(TARGET).bso
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563
modules/hekate_libsys_lp0/pmc_lp0_t210.h
Normal file
563
modules/hekate_libsys_lp0/pmc_lp0_t210.h
Normal file
@ -0,0 +1,563 @@
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/*
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* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _TEGRA210_PMC_H_
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#define _TEGRA210_PMC_H_
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#include "types.h"
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struct tegra_pmc_regs {
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u32 cntrl;
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u32 sec_disable;
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u32 pmc_swrst;
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u32 wake_mask;
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u32 wake_lvl;
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u32 wake_status;
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u32 sw_wake_status;
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u32 dpd_pads_oride;
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u32 dpd_sample;
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u32 dpd_enable;
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u32 pwrgate_timer_off;
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u32 clamp_status;
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u32 pwrgate_toggle;
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u32 remove_clamping_cmd;
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u32 pwrgate_status;
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u32 pwrgood_timer;
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u32 blink_timer;
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u32 no_iopower;
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u32 pwr_det;
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u32 pwr_det_latch;
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u32 scratch0;
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u32 scratch1;
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u32 scratch2;
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u32 scratch3;
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u32 scratch4;
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u32 scratch5;
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u32 scratch6;
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u32 scratch7;
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u32 scratch8;
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u32 scratch9;
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u32 scratch10;
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u32 scratch11;
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u32 scratch12;
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u32 scratch13;
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u32 scratch14;
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u32 scratch15;
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u32 scratch16;
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u32 scratch17;
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u32 scratch18;
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u32 scratch19;
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u32 odmdata;
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u32 scratch21;
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u32 scratch22;
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u32 scratch23;
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u32 secure_scratch0;
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u32 secure_scratch1;
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u32 secure_scratch2;
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u32 secure_scratch3;
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u32 secure_scratch4;
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u32 secure_scratch5;
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u32 cpupwrgood_timer;
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u32 cpupwroff_timer;
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u32 pg_mask;
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u32 pg_mask_1;
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u32 auto_wake_lvl;
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u32 auto_wake_lvl_mask;
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u32 wake_delay;
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u32 pwr_det_val;
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u32 ddr_pwr;
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u32 usb_debounce_del;
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u32 usb_a0;
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u32 crypto_op;
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u32 pllp_wb0_override;
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u32 scratch24;
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u32 scratch25;
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u32 scratch26;
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u32 scratch27;
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u32 scratch28;
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u32 scratch29;
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u32 scratch30;
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u32 scratch31;
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u32 scratch32;
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u32 scratch33;
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u32 scratch34;
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u32 scratch35;
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u32 scratch36;
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u32 scratch37;
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u32 scratch38;
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u32 scratch39;
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u32 scratch40;
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u32 scratch41;
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u32 scratch42;
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u32 bondout_mirror[3];
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u32 sys_33v_en;
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u32 bondout_mirror_access;
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u32 gate;
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u32 wake2_mask;
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u32 wake2_lvl;
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u32 wake2_status;
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u32 sw_wake2_status;
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u32 auto_wake2_lvl_mask;
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u32 pg_mask_2;
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u32 pg_mask_ce1;
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u32 pg_mask_ce2;
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u32 pg_mask_ce3;
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u32 pwrgate_timer_ce[7];
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u32 pcx_edpd_cntrl;
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u32 osc_edpd_over;
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u32 clk_out_cntrl;
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u32 sata_pwrgt;
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u32 sensor_ctrl;
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u32 rst_status;
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u32 io_dpd_req;
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u32 io_dpd_status;
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u32 io_dpd2_req;
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u32 io_dpd2_status;
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u32 sel_dpd_tim;
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u32 vddp_sel;
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u32 ddr_cfg;
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u32 e_no_vttgen;
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u8 _rsv0[4];
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u32 pllm_wb0_override_freq;
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u32 test_pwrgate;
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u32 pwrgate_timer_mult;
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u32 dis_sel_dpd;
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u32 utmip_uhsic_triggers;
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u32 utmip_uhsic_saved_state;
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u32 utmip_pad_cfg;
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u32 utmip_term_pad_cfg;
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u32 utmip_uhsic_sleep_cfg;
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u32 utmip_uhsic_sleepwalk_cfg;
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u32 utmip_sleepwalk_p[3];
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u32 uhsic_sleepwalk_p0;
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u32 utmip_uhsic_status;
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u32 utmip_uhsic_fake;
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u32 bondout_mirror3[5 - 3];
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u32 secure_scratch6;
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u32 secure_scratch7;
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u32 scratch43;
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u32 scratch44;
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u32 scratch45;
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u32 scratch46;
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u32 scratch47;
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u32 scratch48;
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u32 scratch49;
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u32 scratch50;
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u32 scratch51;
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u32 scratch52;
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u32 scratch53;
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u32 scratch54;
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u32 scratch55;
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u32 scratch0_eco;
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u32 por_dpd_ctrl;
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u32 scratch2_eco;
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u32 utmip_uhsic_line_wakeup;
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u32 utmip_bias_master_cntrl;
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u32 utmip_master_config;
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u32 td_pwrgate_inter_part_timer;
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u32 utmip_uhsic2_triggers;
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u32 utmip_uhsic2_saved_state;
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u32 utmip_uhsic2_sleep_cfg;
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u32 utmip_uhsic2_sleepwalk_cfg;
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u32 uhsic2_sleepwalk_p1;
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u32 utmip_uhsic2_status;
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u32 utmip_uhsic2_fake;
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u32 utmip_uhsic2_line_wakeup;
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u32 utmip_master2_config;
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u32 utmip_uhsic_rpd_cfg;
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u32 pg_mask_ce0;
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u32 pg_mask3[5 - 3];
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u32 pllm_wb0_override2;
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u32 tsc_mult;
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u32 cpu_vsense_override;
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u32 glb_amap_cfg;
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u32 sticky_bits;
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u32 sec_disable2;
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u32 weak_bias;
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u32 reg_short;
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u32 pg_mask_andor;
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u8 _rsv1[0x2c];
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u32 secure_scratch8; /* offset 0x300 */
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u32 secure_scratch9;
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u32 secure_scratch10;
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u32 secure_scratch11;
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u32 secure_scratch12;
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u32 secure_scratch13;
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u32 secure_scratch14;
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u32 secure_scratch15;
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u32 secure_scratch16;
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u32 secure_scratch17;
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u32 secure_scratch18;
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u32 secure_scratch19;
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u32 secure_scratch20;
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u32 secure_scratch21;
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u32 secure_scratch22;
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u32 secure_scratch23;
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u32 secure_scratch24;
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u32 secure_scratch25;
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u32 secure_scratch26;
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u32 secure_scratch27;
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u32 secure_scratch28;
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u32 secure_scratch29;
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u32 secure_scratch30;
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u32 secure_scratch31;
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u32 secure_scratch32;
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u32 secure_scratch33;
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u32 secure_scratch34;
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u32 secure_scratch35;
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u32 secure_scratch36;
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u32 secure_scratch37;
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u32 secure_scratch38;
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u32 secure_scratch39;
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u32 secure_scratch40;
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u32 secure_scratch41;
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u32 secure_scratch42;
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u32 secure_scratch43;
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u32 secure_scratch44;
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u32 secure_scratch45;
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u32 secure_scratch46;
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u32 secure_scratch47;
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u32 secure_scratch48;
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u32 secure_scratch49;
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u32 secure_scratch50;
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u32 secure_scratch51;
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u32 secure_scratch52;
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u32 secure_scratch53;
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u32 secure_scratch54;
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u32 secure_scratch55;
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u32 secure_scratch56;
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u32 secure_scratch57;
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u32 secure_scratch58;
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u32 secure_scratch59;
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u32 secure_scratch60;
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u32 secure_scratch61;
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u32 secure_scratch62;
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u32 secure_scratch63;
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u32 secure_scratch64;
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u32 secure_scratch65;
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u32 secure_scratch66;
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u32 secure_scratch67;
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u32 secure_scratch68;
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u32 secure_scratch69;
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u32 secure_scratch70;
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u32 secure_scratch71;
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u32 secure_scratch72;
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u32 secure_scratch73;
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u32 secure_scratch74;
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u32 secure_scratch75;
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u32 secure_scratch76;
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u32 secure_scratch77;
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u32 secure_scratch78;
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u32 secure_scratch79;
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u32 _rsv0x420[8];
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u32 cntrl2; /* 0x440 */
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u32 _rsv0x444[2];
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u32 event_counter; /* 0x44C */
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u32 fuse_control;
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u32 scratch1_eco;
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u32 _rsv0x458[1];
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u32 io_dpd3_req; /* 0x45C */
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u32 io_dpd3_status;
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u32 io_dpd4_req;
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u32 io_dpd4_status;
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u32 _rsv0x46C[30];
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u32 ddr_cntrl; /* 0x4E4 */
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u32 _rsv0x4E8[70];
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u32 scratch56; /* 0x600 */
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u32 scratch57;
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u32 scratch58;
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u32 scratch59;
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u32 scratch60;
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u32 scratch61;
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u32 scratch62;
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u32 scratch63;
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u32 scratch64;
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u32 scratch65;
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u32 scratch66;
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u32 scratch67;
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u32 scratch68;
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u32 scratch69;
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u32 scratch70;
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u32 scratch71;
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u32 scratch72;
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u32 scratch73;
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u32 scratch74;
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u32 scratch75;
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u32 scratch76;
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u32 scratch77;
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u32 scratch78;
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u32 scratch79;
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u32 scratch80;
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u32 scratch81;
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u32 scratch82;
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u32 scratch83;
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u32 scratch84;
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u32 scratch85;
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u32 scratch86;
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u32 scratch87;
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u32 scratch88;
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u32 scratch89;
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u32 scratch90;
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u32 scratch91;
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u32 scratch92;
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u32 scratch93;
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u32 scratch94;
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u32 scratch95;
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u32 scratch96;
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u32 scratch97;
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u32 scratch98;
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u32 scratch99;
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u32 scratch100;
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u32 scratch101;
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u32 scratch102;
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u32 scratch103;
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u32 scratch104;
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u32 scratch105;
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u32 scratch106;
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u32 scratch107;
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u32 scratch108;
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u32 scratch109;
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u32 scratch110;
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u32 scratch111;
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u32 scratch112;
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u32 scratch113;
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u32 scratch114;
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u32 scratch115;
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u32 scratch116;
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u32 scratch117;
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u32 scratch118;
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u32 scratch119;
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u32 scratch120; /* 0x700 */
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u32 scratch121;
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u32 scratch122;
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u32 scratch123;
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u32 scratch124;
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u32 scratch125;
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u32 scratch126;
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u32 scratch127;
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u32 scratch128;
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u32 scratch129;
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u32 scratch130;
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u32 scratch131;
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u32 scratch132;
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u32 scratch133;
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u32 scratch134;
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u32 scratch135;
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u32 scratch136;
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u32 scratch137;
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u32 scratch138;
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u32 scratch139;
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u32 scratch140;
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u32 scratch141;
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u32 scratch142;
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u32 scratch143;
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u32 scratch144;
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u32 scratch145;
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u32 scratch146;
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u32 scratch147;
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u32 scratch148;
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u32 scratch149;
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u32 scratch150;
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u32 scratch151;
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u32 scratch152;
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u32 scratch153;
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u32 scratch154;
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u32 scratch155;
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u32 scratch156;
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u32 scratch157;
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u32 scratch158;
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u32 scratch159;
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u32 scratch160;
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u32 scratch161;
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u32 scratch162;
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u32 scratch163;
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u32 scratch164;
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u32 scratch165;
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u32 scratch166;
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u32 scratch167;
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u32 scratch168;
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u32 scratch169;
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u32 scratch170;
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u32 scratch171;
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u32 scratch172;
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u32 scratch173;
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u32 scratch174;
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u32 scratch175;
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u32 scratch176;
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u32 scratch177;
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u32 scratch178;
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u32 scratch179;
|
||||
u32 scratch180;
|
||||
u32 scratch181;
|
||||
u32 scratch182;
|
||||
u32 scratch183;
|
||||
u32 scratch184;
|
||||
u32 scratch185;
|
||||
u32 scratch186;
|
||||
u32 scratch187;
|
||||
u32 scratch188;
|
||||
u32 scratch189;
|
||||
u32 scratch190;
|
||||
u32 scratch191;
|
||||
u32 scratch192;
|
||||
u32 scratch193;
|
||||
u32 scratch194;
|
||||
u32 scratch195;
|
||||
u32 scratch196;
|
||||
u32 scratch197;
|
||||
u32 scratch198;
|
||||
u32 scratch199;
|
||||
u32 scratch200;
|
||||
u32 scratch201;
|
||||
u32 scratch202;
|
||||
u32 scratch203;
|
||||
u32 scratch204;
|
||||
u32 scratch205;
|
||||
u32 scratch206;
|
||||
u32 scratch207;
|
||||
u32 scratch208;
|
||||
u32 scratch209;
|
||||
u32 scratch210;
|
||||
u32 scratch211;
|
||||
u32 scratch212;
|
||||
u32 scratch213;
|
||||
u32 scratch214;
|
||||
u32 scratch215;
|
||||
u32 scratch216;
|
||||
u32 scratch217;
|
||||
u32 scratch218;
|
||||
u32 scratch219;
|
||||
u32 scratch220;
|
||||
u32 scratch221;
|
||||
u32 scratch222;
|
||||
u32 scratch223;
|
||||
u32 scratch224;
|
||||
u32 scratch225;
|
||||
u32 scratch226;
|
||||
u32 scratch227;
|
||||
u32 scratch228;
|
||||
u32 scratch229;
|
||||
u32 scratch230;
|
||||
u32 scratch231;
|
||||
u32 scratch232;
|
||||
u32 scratch233;
|
||||
u32 scratch234;
|
||||
u32 scratch235;
|
||||
u32 scratch236;
|
||||
u32 scratch237;
|
||||
u32 scratch238;
|
||||
u32 scratch239;
|
||||
u32 scratch240;
|
||||
u32 scratch241;
|
||||
u32 scratch242;
|
||||
u32 scratch243;
|
||||
u32 scratch244;
|
||||
u32 scratch245;
|
||||
u32 scratch246;
|
||||
u32 scratch247;
|
||||
u32 scratch248;
|
||||
u32 scratch249;
|
||||
u32 scratch250;
|
||||
u32 scratch251;
|
||||
u32 scratch252;
|
||||
u32 scratch253;
|
||||
u32 scratch254;
|
||||
u32 scratch255;
|
||||
u32 scratch256;
|
||||
u32 scratch257;
|
||||
u32 scratch258;
|
||||
u32 scratch259;
|
||||
u32 scratch260;
|
||||
u32 scratch261;
|
||||
u32 scratch262;
|
||||
u32 scratch263;
|
||||
u32 scratch264;
|
||||
u32 scratch265;
|
||||
u32 scratch266;
|
||||
u32 scratch267;
|
||||
u32 scratch268;
|
||||
u32 scratch269;
|
||||
u32 scratch270;
|
||||
u32 scratch271;
|
||||
u32 scratch272;
|
||||
u32 scratch273;
|
||||
u32 scratch274;
|
||||
u32 scratch275;
|
||||
u32 scratch276;
|
||||
u32 scratch277;
|
||||
u32 scratch278;
|
||||
u32 scratch279;
|
||||
u32 scratch280;
|
||||
u32 scratch281;
|
||||
u32 scratch282;
|
||||
u32 scratch283;
|
||||
u32 scratch284;
|
||||
u32 scratch285;
|
||||
u32 scratch286;
|
||||
u32 scratch287;
|
||||
u32 scratch288;
|
||||
u32 scratch289;
|
||||
u32 scratch290;
|
||||
u32 scratch291;
|
||||
u32 scratch292;
|
||||
u32 scratch293;
|
||||
u32 scratch294;
|
||||
u32 scratch295;
|
||||
u32 scratch296;
|
||||
u32 scratch297;
|
||||
u32 scratch298;
|
||||
u32 scratch299; /* 0x9CC */
|
||||
u32 _rsv0x9D0[50];
|
||||
u32 secure_scratch80; /* 0xa98 */
|
||||
u32 secure_scratch81;
|
||||
u32 secure_scratch82;
|
||||
u32 secure_scratch83;
|
||||
u32 secure_scratch84;
|
||||
u32 secure_scratch85;
|
||||
u32 secure_scratch86;
|
||||
u32 secure_scratch87;
|
||||
u32 secure_scratch88;
|
||||
u32 secure_scratch89;
|
||||
u32 secure_scratch90;
|
||||
u32 secure_scratch91;
|
||||
u32 secure_scratch92;
|
||||
u32 secure_scratch93;
|
||||
u32 secure_scratch94;
|
||||
u32 secure_scratch95;
|
||||
u32 secure_scratch96;
|
||||
u32 secure_scratch97;
|
||||
u32 secure_scratch98;
|
||||
u32 secure_scratch99;
|
||||
u32 secure_scratch100;
|
||||
u32 secure_scratch101;
|
||||
u32 secure_scratch102;
|
||||
u32 secure_scratch103;
|
||||
u32 secure_scratch104;
|
||||
u32 secure_scratch105;
|
||||
u32 secure_scratch106;
|
||||
u32 secure_scratch107;
|
||||
u32 secure_scratch108;
|
||||
u32 secure_scratch109;
|
||||
u32 secure_scratch110;
|
||||
u32 secure_scratch111;
|
||||
u32 secure_scratch112;
|
||||
u32 secure_scratch113;
|
||||
u32 secure_scratch114;
|
||||
u32 secure_scratch115;
|
||||
u32 secure_scratch116;
|
||||
u32 secure_scratch117;
|
||||
u32 secure_scratch118;
|
||||
u32 secure_scratch119;
|
||||
};
|
||||
|
||||
#endif /* _TEGRA210_PMC_H_ */
|
964
modules/hekate_libsys_lp0/sdram_lp0_param_t210.h
Normal file
964
modules/hekate_libsys_lp0/sdram_lp0_param_t210.h
Normal file
@ -0,0 +1,964 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright 2014 Google Inc.
|
||||
* Copyright (C) 2018 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Defines the SDRAM parameter structure.
|
||||
*
|
||||
* Note that PLLM is used by EMC. The field names are in camel case to ease
|
||||
* directly converting BCT config files (*.cfg) into C structure.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
|
||||
#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
|
||||
|
||||
#include "types.h"
|
||||
|
||||
enum
|
||||
{
|
||||
/* Specifies the memory type to be undefined */
|
||||
NvBootMemoryType_None = 0,
|
||||
|
||||
/* Specifies the memory type to be DDR SDRAM */
|
||||
NvBootMemoryType_Ddr = 0,
|
||||
|
||||
/* Specifies the memory type to be LPDDR SDRAM */
|
||||
NvBootMemoryType_LpDdr = 0,
|
||||
|
||||
/* Specifies the memory type to be DDR2 SDRAM */
|
||||
NvBootMemoryType_Ddr2 = 0,
|
||||
|
||||
/* Specifies the memory type to be LPDDR2 SDRAM */
|
||||
NvBootMemoryType_LpDdr2,
|
||||
|
||||
/* Specifies the memory type to be DDR3 SDRAM */
|
||||
NvBootMemoryType_Ddr3,
|
||||
|
||||
/* Specifies the memory type to be LPDDR4 SDRAM */
|
||||
NvBootMemoryType_LpDdr4,
|
||||
|
||||
NvBootMemoryType_Num,
|
||||
|
||||
/* Specifies an entry in the ram_code table that's not in use */
|
||||
NvBootMemoryType_Unused = 0X7FFFFFF,
|
||||
};
|
||||
|
||||
/**
|
||||
* Defines the SDRAM parameter structure
|
||||
*/
|
||||
struct sdram_params
|
||||
{
|
||||
|
||||
/* Specifies the type of memory device */
|
||||
u32 MemoryType;
|
||||
|
||||
/* MC/EMC clock source configuration */
|
||||
|
||||
/* Specifies the M value for PllM */
|
||||
u32 PllMInputDivider;
|
||||
/* Specifies the N value for PllM */
|
||||
u32 PllMFeedbackDivider;
|
||||
/* Specifies the time to wait for PLLM to lock (in microseconds) */
|
||||
u32 PllMStableTime;
|
||||
/* Specifies misc. control bits */
|
||||
u32 PllMSetupControl;
|
||||
/* Specifies the P value for PLLM */
|
||||
u32 PllMPostDivider;
|
||||
/* Specifies value for Charge Pump Gain Control */
|
||||
u32 PllMKCP;
|
||||
/* Specifies VCO gain */
|
||||
u32 PllMKVCO;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare0;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare1;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare2;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare3;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare4;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare5;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare6;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare7;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare8;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare9;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare10;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare11;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare12;
|
||||
/* Spare BCT param */
|
||||
u32 EmcBctSpare13;
|
||||
|
||||
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
|
||||
u32 EmcClockSource;
|
||||
u32 EmcClockSourceDll;
|
||||
|
||||
/* Defines possible override for PLLLM_MISC2 */
|
||||
u32 ClkRstControllerPllmMisc2Override;
|
||||
/* enables override for PLLLM_MISC2 */
|
||||
u32 ClkRstControllerPllmMisc2OverrideEnable;
|
||||
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
|
||||
u32 ClearClk2Mc1;
|
||||
|
||||
/* Auto-calibration of EMC pads */
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
|
||||
u32 EmcAutoCalInterval;
|
||||
/*
|
||||
* Specifies the value for EMC_AUTO_CAL_CONFIG
|
||||
* Note: Trigger bits are set by the SDRAM code.
|
||||
*/
|
||||
u32 EmcAutoCalConfig;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
|
||||
u32 EmcAutoCalConfig2;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
|
||||
u32 EmcAutoCalConfig3;
|
||||
|
||||
/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
|
||||
u32 EmcAutoCalConfig4;
|
||||
u32 EmcAutoCalConfig5;
|
||||
u32 EmcAutoCalConfig6;
|
||||
u32 EmcAutoCalConfig7;
|
||||
u32 EmcAutoCalConfig8;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
|
||||
u32 EmcAutoCalVrefSel0;
|
||||
u32 EmcAutoCalVrefSel1;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
|
||||
u32 EmcAutoCalChannel;
|
||||
|
||||
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
|
||||
u32 EmcPmacroAutocalCfg0;
|
||||
u32 EmcPmacroAutocalCfg1;
|
||||
u32 EmcPmacroAutocalCfg2;
|
||||
u32 EmcPmacroRxTerm;
|
||||
u32 EmcPmacroDqTxDrv;
|
||||
u32 EmcPmacroCaTxDrv;
|
||||
u32 EmcPmacroCmdTxDrv;
|
||||
u32 EmcPmacroAutocalCfgCommon;
|
||||
u32 EmcPmacroZctrl;
|
||||
|
||||
/*
|
||||
* Specifies the time for the calibration
|
||||
* to stabilize (in microseconds)
|
||||
*/
|
||||
u32 EmcAutoCalWait;
|
||||
|
||||
u32 EmcXm2CompPadCtrl;
|
||||
u32 EmcXm2CompPadCtrl2;
|
||||
u32 EmcXm2CompPadCtrl3;
|
||||
|
||||
/*
|
||||
* DRAM size information
|
||||
* Specifies the value for EMC_ADR_CFG
|
||||
*/
|
||||
u32 EmcAdrCfg;
|
||||
|
||||
/*
|
||||
* Specifies the time to wait after asserting pin
|
||||
* CKE (in microseconds)
|
||||
*/
|
||||
u32 EmcPinProgramWait;
|
||||
/* Specifies the extra delay before/after pin RESET/CKE command */
|
||||
u32 EmcPinExtraWait;
|
||||
|
||||
u32 EmcPinGpioEn;
|
||||
u32 EmcPinGpio;
|
||||
|
||||
/*
|
||||
* Specifies the extra delay after the first writing
|
||||
* of EMC_TIMING_CONTROL
|
||||
*/
|
||||
u32 EmcTimingControlWait;
|
||||
|
||||
/* Timing parameters required for the SDRAM */
|
||||
|
||||
/* Specifies the value for EMC_RC */
|
||||
u32 EmcRc;
|
||||
/* Specifies the value for EMC_RFC */
|
||||
u32 EmcRfc;
|
||||
/* Specifies the value for EMC_RFC_PB */
|
||||
u32 EmcRfcPb;
|
||||
/* Specifies the value for EMC_RFC_CTRL2 */
|
||||
u32 EmcRefctrl2;
|
||||
/* Specifies the value for EMC_RFC_SLR */
|
||||
u32 EmcRfcSlr;
|
||||
/* Specifies the value for EMC_RAS */
|
||||
u32 EmcRas;
|
||||
/* Specifies the value for EMC_RP */
|
||||
u32 EmcRp;
|
||||
/* Specifies the value for EMC_R2R */
|
||||
u32 EmcR2r;
|
||||
/* Specifies the value for EMC_W2W */
|
||||
u32 EmcW2w;
|
||||
/* Specifies the value for EMC_R2W */
|
||||
u32 EmcR2w;
|
||||
/* Specifies the value for EMC_W2R */
|
||||
u32 EmcW2r;
|
||||
/* Specifies the value for EMC_R2P */
|
||||
u32 EmcR2p;
|
||||
/* Specifies the value for EMC_W2P */
|
||||
u32 EmcW2p;
|
||||
|
||||
u32 EmcTppd;
|
||||
u32 EmcCcdmw;
|
||||
|
||||
/* Specifies the value for EMC_RD_RCD */
|
||||
u32 EmcRdRcd;
|
||||
/* Specifies the value for EMC_WR_RCD */
|
||||
u32 EmcWrRcd;
|
||||
/* Specifies the value for EMC_RRD */
|
||||
u32 EmcRrd;
|
||||
/* Specifies the value for EMC_REXT */
|
||||
u32 EmcRext;
|
||||
/* Specifies the value for EMC_WEXT */
|
||||
u32 EmcWext;
|
||||
/* Specifies the value for EMC_WDV */
|
||||
u32 EmcWdv;
|
||||
|
||||
u32 EmcWdvChk;
|
||||
u32 EmcWsv;
|
||||
u32 EmcWev;
|
||||
|
||||
/* Specifies the value for EMC_WDV_MASK */
|
||||
u32 EmcWdvMask;
|
||||
|
||||
u32 EmcWsDuration;
|
||||
u32 EmcWeDuration;
|
||||
|
||||
/* Specifies the value for EMC_QUSE */
|
||||
u32 EmcQUse;
|
||||
/* Specifies the value for EMC_QUSE_WIDTH */
|
||||
u32 EmcQuseWidth;
|
||||
/* Specifies the value for EMC_IBDLY */
|
||||
u32 EmcIbdly;
|
||||
/* Specifies the value for EMC_OBDLY */
|
||||
u32 EmcObdly;
|
||||
/* Specifies the value for EMC_EINPUT */
|
||||
u32 EmcEInput;
|
||||
/* Specifies the value for EMC_EINPUT_DURATION */
|
||||
u32 EmcEInputDuration;
|
||||
/* Specifies the value for EMC_PUTERM_EXTRA */
|
||||
u32 EmcPutermExtra;
|
||||
/* Specifies the value for EMC_PUTERM_WIDTH */
|
||||
u32 EmcPutermWidth;
|
||||
/* Specifies the value for EMC_PUTERM_ADJ */
|
||||
////u32 EmcPutermAdj;
|
||||
|
||||
/* Specifies the value for EMC_QRST */
|
||||
u32 EmcQRst;
|
||||
/* Specifies the value for EMC_QSAFE */
|
||||
u32 EmcQSafe;
|
||||
/* Specifies the value for EMC_RDV */
|
||||
u32 EmcRdv;
|
||||
/* Specifies the value for EMC_RDV_MASK */
|
||||
u32 EmcRdvMask;
|
||||
/* Specifies the value for EMC_RDV_EARLY */
|
||||
u32 EmcRdvEarly;
|
||||
/* Specifies the value for EMC_RDV_EARLY_MASK */
|
||||
u32 EmcRdvEarlyMask;
|
||||
/* Specifies the value for EMC_QPOP */
|
||||
u32 EmcQpop;
|
||||
|
||||
/* Specifies the value for EMC_REFRESH */
|
||||
u32 EmcRefresh;
|
||||
/* Specifies the value for EMC_BURST_REFRESH_NUM */
|
||||
u32 EmcBurstRefreshNum;
|
||||
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
|
||||
u32 EmcPreRefreshReqCnt;
|
||||
/* Specifies the value for EMC_PDEX2WR */
|
||||
u32 EmcPdEx2Wr;
|
||||
/* Specifies the value for EMC_PDEX2RD */
|
||||
u32 EmcPdEx2Rd;
|
||||
/* Specifies the value for EMC_PCHG2PDEN */
|
||||
u32 EmcPChg2Pden;
|
||||
/* Specifies the value for EMC_ACT2PDEN */
|
||||
u32 EmcAct2Pden;
|
||||
/* Specifies the value for EMC_AR2PDEN */
|
||||
u32 EmcAr2Pden;
|
||||
/* Specifies the value for EMC_RW2PDEN */
|
||||
u32 EmcRw2Pden;
|
||||
/* Specifies the value for EMC_CKE2PDEN */
|
||||
u32 EmcCke2Pden;
|
||||
/* Specifies the value for EMC_PDEX2CKE */
|
||||
u32 EmcPdex2Cke;
|
||||
/* Specifies the value for EMC_PDEX2MRR */
|
||||
u32 EmcPdex2Mrr;
|
||||
/* Specifies the value for EMC_TXSR */
|
||||
u32 EmcTxsr;
|
||||
/* Specifies the value for EMC_TXSRDLL */
|
||||
u32 EmcTxsrDll;
|
||||
/* Specifies the value for EMC_TCKE */
|
||||
u32 EmcTcke;
|
||||
/* Specifies the value for EMC_TCKESR */
|
||||
u32 EmcTckesr;
|
||||
/* Specifies the value for EMC_TPD */
|
||||
u32 EmcTpd;
|
||||
/* Specifies the value for EMC_TFAW */
|
||||
u32 EmcTfaw;
|
||||
/* Specifies the value for EMC_TRPAB */
|
||||
u32 EmcTrpab;
|
||||
/* Specifies the value for EMC_TCLKSTABLE */
|
||||
u32 EmcTClkStable;
|
||||
/* Specifies the value for EMC_TCLKSTOP */
|
||||
u32 EmcTClkStop;
|
||||
/* Specifies the value for EMC_TREFBW */
|
||||
u32 EmcTRefBw;
|
||||
|
||||
/* FBIO configuration values */
|
||||
|
||||
/* Specifies the value for EMC_FBIO_CFG5 */
|
||||
u32 EmcFbioCfg5;
|
||||
/* Specifies the value for EMC_FBIO_CFG7 */
|
||||
u32 EmcFbioCfg7;
|
||||
/* Specifies the value for EMC_FBIO_CFG8 */
|
||||
u32 EmcFbioCfg8;
|
||||
|
||||
/* Command mapping for CMD brick 0 */
|
||||
u32 EmcCmdMappingCmd0_0;
|
||||
u32 EmcCmdMappingCmd0_1;
|
||||
u32 EmcCmdMappingCmd0_2;
|
||||
u32 EmcCmdMappingCmd1_0;
|
||||
u32 EmcCmdMappingCmd1_1;
|
||||
u32 EmcCmdMappingCmd1_2;
|
||||
u32 EmcCmdMappingCmd2_0;
|
||||
u32 EmcCmdMappingCmd2_1;
|
||||
u32 EmcCmdMappingCmd2_2;
|
||||
u32 EmcCmdMappingCmd3_0;
|
||||
u32 EmcCmdMappingCmd3_1;
|
||||
u32 EmcCmdMappingCmd3_2;
|
||||
u32 EmcCmdMappingByte;
|
||||
|
||||
/* Specifies the value for EMC_FBIO_SPARE */
|
||||
u32 EmcFbioSpare;
|
||||
|
||||
/* Specifies the value for EMC_CFG_RSV */
|
||||
u32 EmcCfgRsv;
|
||||
|
||||
/* MRS command values */
|
||||
|
||||
/* Specifies the value for EMC_MRS */
|
||||
u32 EmcMrs;
|
||||
/* Specifies the MP0 command to initialize mode registers */
|
||||
u32 EmcEmrs;
|
||||
/* Specifies the MP2 command to initialize mode registers */
|
||||
u32 EmcEmrs2;
|
||||
/* Specifies the MP3 command to initialize mode registers */
|
||||
u32 EmcEmrs3;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
|
||||
u32 EmcMrw1;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
|
||||
u32 EmcMrw2;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
|
||||
u32 EmcMrw3;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||
u32 EmcMrw4;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
|
||||
u32 EmcMrw6;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||
u32 EmcMrw8;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
|
||||
u32 EmcMrw9;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
|
||||
u32 EmcMrw10;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
|
||||
u32 EmcMrw12;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
|
||||
u32 EmcMrw13;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
|
||||
u32 EmcMrw14;
|
||||
/*
|
||||
* Specifies the programming to extra LPDDR2 Mode Register
|
||||
* at cold boot
|
||||
*/
|
||||
u32 EmcMrwExtra;
|
||||
/*
|
||||
* Specifies the programming to extra LPDDR2 Mode Register
|
||||
* at warm boot
|
||||
*/
|
||||
u32 EmcWarmBootMrwExtra;
|
||||
/*
|
||||
* Specify the enable of extra Mode Register programming at
|
||||
* warm boot
|
||||
*/
|
||||
u32 EmcWarmBootExtraModeRegWriteEnable;
|
||||
/*
|
||||
* Specify the enable of extra Mode Register programming at
|
||||
* cold boot
|
||||
*/
|
||||
u32 EmcExtraModeRegWriteEnable;
|
||||
|
||||
/* Specifies the EMC_MRW reset command value */
|
||||
u32 EmcMrwResetCommand;
|
||||
/* Specifies the EMC Reset wait time (in microseconds) */
|
||||
u32 EmcMrwResetNInitWait;
|
||||
/* Specifies the value for EMC_MRS_WAIT_CNT */
|
||||
u32 EmcMrsWaitCnt;
|
||||
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
|
||||
u32 EmcMrsWaitCnt2;
|
||||
|
||||
/* EMC miscellaneous configurations */
|
||||
|
||||
/* Specifies the value for EMC_CFG */
|
||||
u32 EmcCfg;
|
||||
/* Specifies the value for EMC_CFG_2 */
|
||||
u32 EmcCfg2;
|
||||
/* Specifies the pipe bypass controls */
|
||||
u32 EmcCfgPipe;
|
||||
u32 EmcCfgPipeClk;
|
||||
u32 EmcFdpdCtrlCmdNoRamp;
|
||||
u32 EmcCfgUpdate;
|
||||
|
||||
/* Specifies the value for EMC_DBG */
|
||||
u32 EmcDbg;
|
||||
u32 EmcDbgWriteMux;
|
||||
|
||||
/* Specifies the value for EMC_CMDQ */
|
||||
u32 EmcCmdQ;
|
||||
/* Specifies the value for EMC_MC2EMCQ */
|
||||
u32 EmcMc2EmcQ;
|
||||
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
|
||||
u32 EmcDynSelfRefControl;
|
||||
|
||||
/* Specifies the value for MEM_INIT_DONE */
|
||||
u32 AhbArbitrationXbarCtrlMemInitDone;
|
||||
|
||||
/* Specifies the value for EMC_CFG_DIG_DLL */
|
||||
u32 EmcCfgDigDll;
|
||||
u32 EmcCfgDigDll_1;
|
||||
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
|
||||
u32 EmcCfgDigDllPeriod;
|
||||
/* Specifies the value of *DEV_SELECTN of various EMC registers */
|
||||
u32 EmcDevSelect;
|
||||
|
||||
/* Specifies the value for EMC_SEL_DPD_CTRL */
|
||||
u32 EmcSelDpdCtrl;
|
||||
|
||||
/* Pads trimmer delays */
|
||||
u32 EmcFdpdCtrlDq;
|
||||
u32 EmcFdpdCtrlCmd;
|
||||
u32 EmcPmacroIbVrefDq_0;
|
||||
u32 EmcPmacroIbVrefDq_1;
|
||||
u32 EmcPmacroIbVrefDqs_0;
|
||||
u32 EmcPmacroIbVrefDqs_1;
|
||||
u32 EmcPmacroIbRxrt;
|
||||
u32 EmcCfgPipe1;
|
||||
u32 EmcCfgPipe2;
|
||||
|
||||
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
|
||||
u32 EmcPmacroQuseDdllRank0_0;
|
||||
u32 EmcPmacroQuseDdllRank0_1;
|
||||
u32 EmcPmacroQuseDdllRank0_2;
|
||||
u32 EmcPmacroQuseDdllRank0_3;
|
||||
u32 EmcPmacroQuseDdllRank0_4;
|
||||
u32 EmcPmacroQuseDdllRank0_5;
|
||||
u32 EmcPmacroQuseDdllRank1_0;
|
||||
u32 EmcPmacroQuseDdllRank1_1;
|
||||
u32 EmcPmacroQuseDdllRank1_2;
|
||||
u32 EmcPmacroQuseDdllRank1_3;
|
||||
u32 EmcPmacroQuseDdllRank1_4;
|
||||
u32 EmcPmacroQuseDdllRank1_5;
|
||||
|
||||
u32 EmcPmacroObDdllLongDqRank0_0;
|
||||
u32 EmcPmacroObDdllLongDqRank0_1;
|
||||
u32 EmcPmacroObDdllLongDqRank0_2;
|
||||
u32 EmcPmacroObDdllLongDqRank0_3;
|
||||
u32 EmcPmacroObDdllLongDqRank0_4;
|
||||
u32 EmcPmacroObDdllLongDqRank0_5;
|
||||
u32 EmcPmacroObDdllLongDqRank1_0;
|
||||
u32 EmcPmacroObDdllLongDqRank1_1;
|
||||
u32 EmcPmacroObDdllLongDqRank1_2;
|
||||
u32 EmcPmacroObDdllLongDqRank1_3;
|
||||
u32 EmcPmacroObDdllLongDqRank1_4;
|
||||
u32 EmcPmacroObDdllLongDqRank1_5;
|
||||
|
||||
u32 EmcPmacroObDdllLongDqsRank0_0;
|
||||
u32 EmcPmacroObDdllLongDqsRank0_1;
|
||||
u32 EmcPmacroObDdllLongDqsRank0_2;
|
||||
u32 EmcPmacroObDdllLongDqsRank0_3;
|
||||
u32 EmcPmacroObDdllLongDqsRank0_4;
|
||||
u32 EmcPmacroObDdllLongDqsRank0_5;
|
||||
u32 EmcPmacroObDdllLongDqsRank1_0;
|
||||
u32 EmcPmacroObDdllLongDqsRank1_1;
|
||||
u32 EmcPmacroObDdllLongDqsRank1_2;
|
||||
u32 EmcPmacroObDdllLongDqsRank1_3;
|
||||
u32 EmcPmacroObDdllLongDqsRank1_4;
|
||||
u32 EmcPmacroObDdllLongDqsRank1_5;
|
||||
|
||||
u32 EmcPmacroIbDdllLongDqsRank0_0;
|
||||
u32 EmcPmacroIbDdllLongDqsRank0_1;
|
||||
u32 EmcPmacroIbDdllLongDqsRank0_2;
|
||||
u32 EmcPmacroIbDdllLongDqsRank0_3;
|
||||
u32 EmcPmacroIbDdllLongDqsRank1_0;
|
||||
u32 EmcPmacroIbDdllLongDqsRank1_1;
|
||||
u32 EmcPmacroIbDdllLongDqsRank1_2;
|
||||
u32 EmcPmacroIbDdllLongDqsRank1_3;
|
||||
|
||||
u32 EmcPmacroDdllLongCmd_0;
|
||||
u32 EmcPmacroDdllLongCmd_1;
|
||||
u32 EmcPmacroDdllLongCmd_2;
|
||||
u32 EmcPmacroDdllLongCmd_3;
|
||||
u32 EmcPmacroDdllLongCmd_4;
|
||||
u32 EmcPmacroDdllShortCmd_0;
|
||||
u32 EmcPmacroDdllShortCmd_1;
|
||||
u32 EmcPmacroDdllShortCmd_2;
|
||||
|
||||
/*
|
||||
* Specifies the delay after asserting CKE pin during a WarmBoot0
|
||||
* sequence (in microseconds)
|
||||
*/
|
||||
u32 WarmBootWait;
|
||||
|
||||
/* Specifies the value for EMC_ODT_WRITE */
|
||||
u32 EmcOdtWrite;
|
||||
|
||||
/* Periodic ZQ calibration */
|
||||
|
||||
/*
|
||||
* Specifies the value for EMC_ZCAL_INTERVAL
|
||||
* Value 0 disables ZQ calibration
|
||||
*/
|
||||
u32 EmcZcalInterval;
|
||||
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
|
||||
u32 EmcZcalWaitCnt;
|
||||
/* Specifies the value for EMC_ZCAL_MRW_CMD */
|
||||
u32 EmcZcalMrwCmd;
|
||||
|
||||
/* DRAM initialization sequence flow control */
|
||||
|
||||
/* Specifies the MRS command value for resetting DLL */
|
||||
u32 EmcMrsResetDll;
|
||||
/* Specifies the command for ZQ initialization of device 0 */
|
||||
u32 EmcZcalInitDev0;
|
||||
/* Specifies the command for ZQ initialization of device 1 */
|
||||
u32 EmcZcalInitDev1;
|
||||
/*
|
||||
* Specifies the wait time after programming a ZQ initialization
|
||||
* command (in microseconds)
|
||||
*/
|
||||
u32 EmcZcalInitWait;
|
||||
/*
|
||||
* Specifies the enable for ZQ calibration at cold boot [bit 0]
|
||||
* and warm boot [bit 1]
|
||||
*/
|
||||
u32 EmcZcalWarmColdBootEnables;
|
||||
|
||||
/*
|
||||
* Specifies the MRW command to LPDDR2 for ZQ calibration
|
||||
* on warmboot
|
||||
*/
|
||||
/* Is issued to both devices separately */
|
||||
u32 EmcMrwLpddr2ZcalWarmBoot;
|
||||
/*
|
||||
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
|
||||
* Is issued to both devices separately
|
||||
*/
|
||||
u32 EmcZqCalDdr3WarmBoot;
|
||||
u32 EmcZqCalLpDdr4WarmBoot;
|
||||
/*
|
||||
* Specifies the wait time for ZQ calibration on warmboot
|
||||
* (in microseconds)
|
||||
*/
|
||||
u32 EmcZcalWarmBootWait;
|
||||
/*
|
||||
* Specifies the enable for DRAM Mode Register programming
|
||||
* at warm boot
|
||||
*/
|
||||
u32 EmcMrsWarmBootEnable;
|
||||
/*
|
||||
* Specifies the wait time after sending an MRS DLL reset command
|
||||
* in microseconds)
|
||||
*/
|
||||
u32 EmcMrsResetDllWait;
|
||||
/* Specifies the extra MRS command to initialize mode registers */
|
||||
u32 EmcMrsExtra;
|
||||
/* Specifies the extra MRS command at warm boot */
|
||||
u32 EmcWarmBootMrsExtra;
|
||||
/* Specifies the EMRS command to enable the DDR2 DLL */
|
||||
u32 EmcEmrsDdr2DllEnable;
|
||||
/* Specifies the MRS command to reset the DDR2 DLL */
|
||||
u32 EmcMrsDdr2DllReset;
|
||||
/* Specifies the EMRS command to set OCD calibration */
|
||||
u32 EmcEmrsDdr2OcdCalib;
|
||||
/*
|
||||
* Specifies the wait between initializing DDR and setting OCD
|
||||
* calibration (in microseconds)
|
||||
*/
|
||||
u32 EmcDdr2Wait;
|
||||
/* Specifies the value for EMC_CLKEN_OVERRIDE */
|
||||
u32 EmcClkenOverride;
|
||||
|
||||
/*
|
||||
* Specifies LOG2 of the extra refresh numbers after booting
|
||||
* Program 0 to disable
|
||||
*/
|
||||
u32 EmcExtraRefreshNum;
|
||||
/* Specifies the master override for all EMC clocks */
|
||||
u32 EmcClkenOverrideAllWarmBoot;
|
||||
/* Specifies the master override for all MC clocks */
|
||||
u32 McClkenOverrideAllWarmBoot;
|
||||
/* Specifies digital dll period, choosing between 4 to 64 ms */
|
||||
u32 EmcCfgDigDllPeriodWarmBoot;
|
||||
|
||||
/* Pad controls */
|
||||
|
||||
/* Specifies the value for PMC_VDDP_SEL */
|
||||
u32 PmcVddpSel;
|
||||
/* Specifies the wait time after programming PMC_VDDP_SEL */
|
||||
u32 PmcVddpSelWait;
|
||||
/* Specifies the value for PMC_DDR_PWR */
|
||||
u32 PmcDdrPwr;
|
||||
/* Specifies the value for PMC_DDR_CFG */
|
||||
u32 PmcDdrCfg;
|
||||
/* Specifies the value for PMC_IO_DPD3_REQ */
|
||||
u32 PmcIoDpd3Req;
|
||||
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
|
||||
u32 PmcIoDpd3ReqWait;
|
||||
u32 PmcIoDpd4ReqWait;
|
||||
|
||||
/* Specifies the value for PMC_REG_SHORT */
|
||||
u32 PmcRegShort;
|
||||
/* Specifies the value for PMC_NO_IOPOWER */
|
||||
u32 PmcNoIoPower;
|
||||
|
||||
u32 PmcDdrCntrlWait;
|
||||
u32 PmcDdrCntrl;
|
||||
|
||||
/* Specifies the value for EMC_ACPD_CONTROL */
|
||||
u32 EmcAcpdControl;
|
||||
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
|
||||
////u32 EmcSwizzleRank0ByteCfg;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
|
||||
u32 EmcSwizzleRank0Byte0;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
|
||||
u32 EmcSwizzleRank0Byte1;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
|
||||
u32 EmcSwizzleRank0Byte2;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
|
||||
u32 EmcSwizzleRank0Byte3;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
|
||||
////u32 EmcSwizzleRank1ByteCfg;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
|
||||
u32 EmcSwizzleRank1Byte0;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
|
||||
u32 EmcSwizzleRank1Byte1;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
|
||||
u32 EmcSwizzleRank1Byte2;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
|
||||
u32 EmcSwizzleRank1Byte3;
|
||||
|
||||
/* Specifies the value for EMC_TXDSRVTTGEN */
|
||||
u32 EmcTxdsrvttgen;
|
||||
|
||||
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
|
||||
u32 EmcDataBrlshft0;
|
||||
u32 EmcDataBrlshft1;
|
||||
|
||||
u32 EmcDqsBrlshft0;
|
||||
u32 EmcDqsBrlshft1;
|
||||
|
||||
u32 EmcCmdBrlshft0;
|
||||
u32 EmcCmdBrlshft1;
|
||||
u32 EmcCmdBrlshft2;
|
||||
u32 EmcCmdBrlshft3;
|
||||
|
||||
u32 EmcQuseBrlshft0;
|
||||
u32 EmcQuseBrlshft1;
|
||||
u32 EmcQuseBrlshft2;
|
||||
u32 EmcQuseBrlshft3;
|
||||
|
||||
u32 EmcDllCfg0;
|
||||
u32 EmcDllCfg1;
|
||||
|
||||
u32 EmcPmcScratch1;
|
||||
u32 EmcPmcScratch2;
|
||||
u32 EmcPmcScratch3;
|
||||
|
||||
u32 EmcPmacroPadCfgCtrl;
|
||||
|
||||
u32 EmcPmacroVttgenCtrl0;
|
||||
u32 EmcPmacroVttgenCtrl1;
|
||||
u32 EmcPmacroVttgenCtrl2;
|
||||
|
||||
u32 EmcPmacroBrickCtrlRfu1;
|
||||
u32 EmcPmacroCmdBrickCtrlFdpd;
|
||||
u32 EmcPmacroBrickCtrlRfu2;
|
||||
u32 EmcPmacroDataBrickCtrlFdpd;
|
||||
u32 EmcPmacroBgBiasCtrl0;
|
||||
u32 EmcPmacroDataPadRxCtrl;
|
||||
u32 EmcPmacroCmdPadRxCtrl;
|
||||
u32 EmcPmacroDataRxTermMode;
|
||||
u32 EmcPmacroCmdRxTermMode;
|
||||
u32 EmcPmacroDataPadTxCtrl;
|
||||
u32 EmcPmacroCommonPadTxCtrl;
|
||||
u32 EmcPmacroCmdPadTxCtrl;
|
||||
u32 EmcCfg3;
|
||||
|
||||
u32 EmcPmacroTxPwrd0;
|
||||
u32 EmcPmacroTxPwrd1;
|
||||
u32 EmcPmacroTxPwrd2;
|
||||
u32 EmcPmacroTxPwrd3;
|
||||
u32 EmcPmacroTxPwrd4;
|
||||
u32 EmcPmacroTxPwrd5;
|
||||
|
||||
u32 EmcConfigSampleDelay;
|
||||
|
||||
u32 EmcPmacroBrickMapping0;
|
||||
u32 EmcPmacroBrickMapping1;
|
||||
u32 EmcPmacroBrickMapping2;
|
||||
|
||||
u32 EmcPmacroTxSelClkSrc0;
|
||||
u32 EmcPmacroTxSelClkSrc1;
|
||||
u32 EmcPmacroTxSelClkSrc2;
|
||||
u32 EmcPmacroTxSelClkSrc3;
|
||||
u32 EmcPmacroTxSelClkSrc4;
|
||||
u32 EmcPmacroTxSelClkSrc5;
|
||||
|
||||
u32 EmcPmacroDdllBypass;
|
||||
|
||||
u32 EmcPmacroDdllPwrd0;
|
||||
u32 EmcPmacroDdllPwrd1;
|
||||
u32 EmcPmacroDdllPwrd2;
|
||||
|
||||
u32 EmcPmacroCmdCtrl0;
|
||||
u32 EmcPmacroCmdCtrl1;
|
||||
u32 EmcPmacroCmdCtrl2;
|
||||
|
||||
/* DRAM size information */
|
||||
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG */
|
||||
u32 McEmemAdrCfg;
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
|
||||
u32 McEmemAdrCfgDev0;
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
|
||||
u32 McEmemAdrCfgDev1;
|
||||
u32 McEmemAdrCfgChannelMask;
|
||||
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
|
||||
u32 McEmemAdrCfgBankMask0;
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
|
||||
u32 McEmemAdrCfgBankMask1;
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
|
||||
u32 McEmemAdrCfgBankMask2;
|
||||
|
||||
/*
|
||||
* Specifies the value for MC_EMEM_CFG which holds the external memory
|
||||
* size (in KBytes)
|
||||
*/
|
||||
u32 McEmemCfg;
|
||||
|
||||
/* MC arbitration configuration */
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_CFG */
|
||||
u32 McEmemArbCfg;
|
||||
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
|
||||
u32 McEmemArbOutstandingReq;
|
||||
|
||||
u32 McEmemArbRefpbHpCtrl;
|
||||
u32 McEmemArbRefpbBankCtrl;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
|
||||
u32 McEmemArbTimingRcd;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
|
||||
u32 McEmemArbTimingRp;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
|
||||
u32 McEmemArbTimingRc;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
|
||||
u32 McEmemArbTimingRas;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
|
||||
u32 McEmemArbTimingFaw;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
|
||||
u32 McEmemArbTimingRrd;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
|
||||
u32 McEmemArbTimingRap2Pre;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
|
||||
u32 McEmemArbTimingWap2Pre;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
|
||||
u32 McEmemArbTimingR2R;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
|
||||
u32 McEmemArbTimingW2W;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
|
||||
u32 McEmemArbTimingR2W;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
|
||||
u32 McEmemArbTimingW2R;
|
||||
|
||||
u32 McEmemArbTimingRFCPB;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
|
||||
u32 McEmemArbDaTurns;
|
||||
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
|
||||
u32 McEmemArbDaCovers;
|
||||
/* Specifies the value for MC_EMEM_ARB_MISC0 */
|
||||
u32 McEmemArbMisc0;
|
||||
/* Specifies the value for MC_EMEM_ARB_MISC1 */
|
||||
u32 McEmemArbMisc1;
|
||||
u32 McEmemArbMisc2;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
|
||||
u32 McEmemArbRing1Throttle;
|
||||
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
|
||||
u32 McEmemArbOverride;
|
||||
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
|
||||
u32 McEmemArbOverride1;
|
||||
/* Specifies the value for MC_EMEM_ARB_RSV */
|
||||
u32 McEmemArbRsv;
|
||||
|
||||
u32 McDaCfg0;
|
||||
u32 McEmemArbTimingCcdmw;
|
||||
|
||||
/* Specifies the value for MC_CLKEN_OVERRIDE */
|
||||
u32 McClkenOverride;
|
||||
|
||||
/* Specifies the value for MC_STAT_CONTROL */
|
||||
u32 McStatControl;
|
||||
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
|
||||
u32 McVideoProtectBom;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
|
||||
u32 McVideoProtectBomAdrHi;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
|
||||
u32 McVideoProtectSizeMb;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
|
||||
u32 McVideoProtectVprOverride;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
|
||||
u32 McVideoProtectVprOverride1;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
|
||||
u32 McVideoProtectGpuOverride0;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
|
||||
u32 McVideoProtectGpuOverride1;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
|
||||
u32 McSecCarveoutBom;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
|
||||
u32 McSecCarveoutAdrHi;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
|
||||
u32 McSecCarveoutSizeMb;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
|
||||
VIDEO_PROTECT_WRITEAccess */
|
||||
u32 McVideoProtectWriteAccess;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
|
||||
SEC_CARVEOUT_WRITEAccess */
|
||||
u32 McSecCarveoutProtectWriteAccess;
|
||||
|
||||
/* Write-Protect Regions (WPR) */
|
||||
u32 McGeneralizedCarveout1Bom;
|
||||
u32 McGeneralizedCarveout1BomHi;
|
||||
u32 McGeneralizedCarveout1Size128kb;
|
||||
u32 McGeneralizedCarveout1Access0;
|
||||
u32 McGeneralizedCarveout1Access1;
|
||||
u32 McGeneralizedCarveout1Access2;
|
||||
u32 McGeneralizedCarveout1Access3;
|
||||
u32 McGeneralizedCarveout1Access4;
|
||||
u32 McGeneralizedCarveout1ForceInternalAccess0;
|
||||
u32 McGeneralizedCarveout1ForceInternalAccess1;
|
||||
u32 McGeneralizedCarveout1ForceInternalAccess2;
|
||||
u32 McGeneralizedCarveout1ForceInternalAccess3;
|
||||
u32 McGeneralizedCarveout1ForceInternalAccess4;
|
||||
u32 McGeneralizedCarveout1Cfg0;
|
||||
|
||||
u32 McGeneralizedCarveout2Bom;
|
||||
u32 McGeneralizedCarveout2BomHi;
|
||||
u32 McGeneralizedCarveout2Size128kb;
|
||||
u32 McGeneralizedCarveout2Access0;
|
||||
u32 McGeneralizedCarveout2Access1;
|
||||
u32 McGeneralizedCarveout2Access2;
|
||||
u32 McGeneralizedCarveout2Access3;
|
||||
u32 McGeneralizedCarveout2Access4;
|
||||
u32 McGeneralizedCarveout2ForceInternalAccess0;
|
||||
u32 McGeneralizedCarveout2ForceInternalAccess1;
|
||||
u32 McGeneralizedCarveout2ForceInternalAccess2;
|
||||
u32 McGeneralizedCarveout2ForceInternalAccess3;
|
||||
u32 McGeneralizedCarveout2ForceInternalAccess4;
|
||||
u32 McGeneralizedCarveout2Cfg0;
|
||||
|
||||
u32 McGeneralizedCarveout3Bom;
|
||||
u32 McGeneralizedCarveout3BomHi;
|
||||
u32 McGeneralizedCarveout3Size128kb;
|
||||
u32 McGeneralizedCarveout3Access0;
|
||||
u32 McGeneralizedCarveout3Access1;
|
||||
u32 McGeneralizedCarveout3Access2;
|
||||
u32 McGeneralizedCarveout3Access3;
|
||||
u32 McGeneralizedCarveout3Access4;
|
||||
u32 McGeneralizedCarveout3ForceInternalAccess0;
|
||||
u32 McGeneralizedCarveout3ForceInternalAccess1;
|
||||
u32 McGeneralizedCarveout3ForceInternalAccess2;
|
||||
u32 McGeneralizedCarveout3ForceInternalAccess3;
|
||||
u32 McGeneralizedCarveout3ForceInternalAccess4;
|
||||
u32 McGeneralizedCarveout3Cfg0;
|
||||
|
||||
u32 McGeneralizedCarveout4Bom;
|
||||
u32 McGeneralizedCarveout4BomHi;
|
||||
u32 McGeneralizedCarveout4Size128kb;
|
||||
u32 McGeneralizedCarveout4Access0;
|
||||
u32 McGeneralizedCarveout4Access1;
|
||||
u32 McGeneralizedCarveout4Access2;
|
||||
u32 McGeneralizedCarveout4Access3;
|
||||
u32 McGeneralizedCarveout4Access4;
|
||||
u32 McGeneralizedCarveout4ForceInternalAccess0;
|
||||
u32 McGeneralizedCarveout4ForceInternalAccess1;
|
||||
u32 McGeneralizedCarveout4ForceInternalAccess2;
|
||||
u32 McGeneralizedCarveout4ForceInternalAccess3;
|
||||
u32 McGeneralizedCarveout4ForceInternalAccess4;
|
||||
u32 McGeneralizedCarveout4Cfg0;
|
||||
|
||||
u32 McGeneralizedCarveout5Bom;
|
||||
u32 McGeneralizedCarveout5BomHi;
|
||||
u32 McGeneralizedCarveout5Size128kb;
|
||||
u32 McGeneralizedCarveout5Access0;
|
||||
u32 McGeneralizedCarveout5Access1;
|
||||
u32 McGeneralizedCarveout5Access2;
|
||||
u32 McGeneralizedCarveout5Access3;
|
||||
u32 McGeneralizedCarveout5Access4;
|
||||
u32 McGeneralizedCarveout5ForceInternalAccess0;
|
||||
u32 McGeneralizedCarveout5ForceInternalAccess1;
|
||||
u32 McGeneralizedCarveout5ForceInternalAccess2;
|
||||
u32 McGeneralizedCarveout5ForceInternalAccess3;
|
||||
u32 McGeneralizedCarveout5ForceInternalAccess4;
|
||||
u32 McGeneralizedCarveout5Cfg0;
|
||||
|
||||
/* Specifies enable for CA training */
|
||||
u32 EmcCaTrainingEnable;
|
||||
|
||||
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
|
||||
spec packet SWIZZLE_BIT6_GT_BIT7 */
|
||||
u32 SwizzleRankByteEncode;
|
||||
/* Specifies enable and offset for patched boot ROM write */
|
||||
u32 BootRomPatchControl;
|
||||
/* Specifies data for patched boot ROM write */
|
||||
u32 BootRomPatchData;
|
||||
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
|
||||
u32 McMtsCarveoutBom;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
|
||||
u32 McMtsCarveoutAdrHi;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
|
||||
u32 McMtsCarveoutSizeMb;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
|
||||
u32 McMtsCarveoutRegCtrl;
|
||||
|
||||
/* End */
|
||||
};
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */
|
1132
modules/hekate_libsys_lp0/sys_sdramlp0.c
Normal file
1132
modules/hekate_libsys_lp0/sys_sdramlp0.c
Normal file
File diff suppressed because it is too large
Load Diff
110
modules/hekate_libsys_lp0/t210.h
Normal file
110
modules/hekate_libsys_lp0/t210.h
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _T210_H_
|
||||
#define _T210_H_
|
||||
|
||||
#include "types.h"
|
||||
|
||||
#define HOST1X_BASE 0x50000000
|
||||
#define DISPLAY_A_BASE 0x54200000
|
||||
#define DSI_BASE 0x54300000
|
||||
#define VIC_BASE 0x54340000
|
||||
#define TSEC_BASE 0x54500000
|
||||
#define SOR1_BASE 0x54580000
|
||||
#define TMR_BASE 0x60005000
|
||||
#define CLOCK_BASE 0x60006000
|
||||
#define FLOW_CTLR_BASE 0x60007000
|
||||
#define SYSREG_BASE 0x6000C000
|
||||
#define SB_BASE (SYSREG_BASE + 0x200)
|
||||
#define GPIO_BASE 0x6000D000
|
||||
#define GPIO_1_BASE (GPIO_BASE)
|
||||
#define GPIO_2_BASE (GPIO_BASE + 0x100)
|
||||
#define GPIO_3_BASE (GPIO_BASE + 0x200)
|
||||
#define GPIO_4_BASE (GPIO_BASE + 0x300)
|
||||
#define GPIO_5_BASE (GPIO_BASE + 0x400)
|
||||
#define GPIO_6_BASE (GPIO_BASE + 0x500)
|
||||
#define GPIO_7_BASE (GPIO_BASE + 0x600)
|
||||
#define GPIO_8_BASE (GPIO_BASE + 0x700)
|
||||
#define EXCP_VEC_BASE 0x6000F000
|
||||
#define APB_MISC_BASE 0x70000000
|
||||
#define PINMUX_AUX_BASE 0x70003000
|
||||
#define UART_BASE 0x70006000
|
||||
#define RTC_BASE 0x7000E000
|
||||
#define PMC_BASE 0x7000E400
|
||||
#define SYSCTR0_BASE 0x7000F000
|
||||
#define FUSE_BASE 0x7000F800
|
||||
#define KFUSE_BASE 0x7000FC00
|
||||
#define SE_BASE 0x70012000
|
||||
#define MC_BASE 0x70019000
|
||||
#define EMC_BASE 0x7001B000
|
||||
#define MIPI_CAL_BASE 0x700E3000
|
||||
#define I2S_BASE 0x702D1000
|
||||
|
||||
#define _REG(base, off) *(vu32 *)((base) + (off))
|
||||
|
||||
#define HOST1X(off) _REG(HOST1X_BASE, off)
|
||||
#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
|
||||
#define DSI(off) _REG(DSI_BASE, off)
|
||||
#define VIC(off) _REG(VIC_BASE, off)
|
||||
#define TSEC(off) _REG(TSEC_BASE, off)
|
||||
#define SOR1(off) _REG(SOR1_BASE, off)
|
||||
#define TMR(off) _REG(TMR_BASE, off)
|
||||
#define CLOCK(off) _REG(CLOCK_BASE, off)
|
||||
#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
|
||||
#define SYSREG(off) _REG(SYSREG_BASE, off)
|
||||
#define SB(off) _REG(SB_BASE, off)
|
||||
#define GPIO(off) _REG(GPIO_BASE, off)
|
||||
#define GPIO_1(off) _REG(GPIO_1_BASE, off)
|
||||
#define GPIO_2(off) _REG(GPIO_2_BASE, off)
|
||||
#define GPIO_3(off) _REG(GPIO_3_BASE, off)
|
||||
#define GPIO_4(off) _REG(GPIO_4_BASE, off)
|
||||
#define GPIO_5(off) _REG(GPIO_5_BASE, off)
|
||||
#define GPIO_6(off) _REG(GPIO_6_BASE, off)
|
||||
#define GPIO_7(off) _REG(GPIO_7_BASE, off)
|
||||
#define GPIO_8(off) _REG(GPIO_8_BASE, off)
|
||||
#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
|
||||
#define APB_MISC(off) _REG(APB_MISC_BASE, off)
|
||||
#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
|
||||
#define RTC(off) _REG(RTC_BASE, off)
|
||||
#define PMC(off) _REG(PMC_BASE, off)
|
||||
#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
|
||||
#define FUSE(off) _REG(FUSE_BASE, off)
|
||||
#define KFUSE(off) _REG(KFUSE_BASE, off)
|
||||
#define SE(off) _REG(SE_BASE, off)
|
||||
#define MC(off) _REG(MC_BASE, off)
|
||||
#define EMC(off) _REG(EMC_BASE, off)
|
||||
#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
|
||||
#define I2S(off) _REG(I2S_BASE, off)
|
||||
|
||||
/*! Misc registers. */
|
||||
#define APB_MISC_PP_PINMUX_GLOBAL 0x40
|
||||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
|
||||
|
||||
/*! System registers. */
|
||||
#define AHB_ARBITRATION_XBAR_CTRL 0xE0
|
||||
#define AHB_AHB_SPARE_REG 0x110
|
||||
|
||||
/*! Secure boot registers. */
|
||||
#define SB_CSR 0x0
|
||||
#define SB_AA64_RESET_LOW 0x30
|
||||
#define SB_AA64_RESET_HIGH 0x34
|
||||
|
||||
/*! SYSCTR0 registers. */
|
||||
#define SYSCTR0_CNTFID0 0x20
|
||||
|
||||
#endif
|
54
modules/hekate_libsys_lp0/types.h
Normal file
54
modules/hekate_libsys_lp0/types.h
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TYPES_H_
|
||||
#define _TYPES_H_
|
||||
|
||||
#define NULL ((void *)0)
|
||||
|
||||
#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
#define OFFSET_OF(t, m) ((u32)&((t *)NULL)->m)
|
||||
#define CONTAINER_OF(mp, t, mn) ((t *)((u32)mp - OFFSET_OF(t, mn)))
|
||||
|
||||
typedef char s8;
|
||||
typedef short s16;
|
||||
typedef short SHORT;
|
||||
typedef int s32;
|
||||
typedef int INT;
|
||||
typedef long LONG;
|
||||
typedef long long int s64;
|
||||
typedef unsigned char u8;
|
||||
typedef unsigned char BYTE;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
typedef unsigned int u32;
|
||||
typedef unsigned int UINT;
|
||||
typedef unsigned long DWORD;
|
||||
typedef unsigned long long QWORD;
|
||||
typedef unsigned long long int u64;
|
||||
typedef volatile unsigned char vu8;
|
||||
typedef volatile unsigned short vu16;
|
||||
typedef volatile unsigned int vu32;
|
||||
|
||||
typedef int bool;
|
||||
#define true 1
|
||||
#define false 0
|
||||
|
||||
#endif
|
@ -11,11 +11,12 @@ VPATH = $(dir $(wildcard ./*/)) $(dir $(wildcard ./*/*/))
|
||||
|
||||
OBJS = $(addprefix $(BUILD)/,\
|
||||
module_sample.o \
|
||||
gfx.o \
|
||||
)
|
||||
|
||||
ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
|
||||
ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork
|
||||
CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
|
||||
LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections
|
||||
LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc
|
||||
|
||||
.PHONY: clean all
|
||||
|
||||
@ -25,7 +26,8 @@ $(BUILD)/%.o: ./%.c
|
||||
$(CC) $(CFLAGS) -c $< -o $@
|
||||
|
||||
$(TARGET).bso: $(OBJS)
|
||||
$(CC) $(LDLAGS) -pie -e _modInit $^ -o $(OUTPUT)/$(TARGET).bso
|
||||
$(CC) $(LDFLAGS) -e _modInit $^ -o $(OUTPUT)/$(TARGET).bso
|
||||
$(STRIP) -g $(OUTPUT)/$(TARGET).bso
|
||||
|
||||
clean:
|
||||
@rm -rf $(OUTPUT)/$(TARGET).bso
|
||||
|
@ -3,8 +3,10 @@
|
||||
*/
|
||||
|
||||
#include "../../common/common_module.h"
|
||||
#include "../../common/common_gfx.h"
|
||||
#include "gfx/gfx.h"
|
||||
|
||||
void _modInit(cbMainModule_t cb, pmoduleConfiguration_t mc)
|
||||
void _modInit(void *moduleConfig, bdkParams_t bp)
|
||||
{
|
||||
cb("Hello World!");
|
||||
gfx_puts(bp->gfxCon, "Hello World!");
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user