hathach 6b6dcc6c09

refactored multiple ports for hcd rusb2

2023-07-26 19:52:33 +07:00

..

boards

refactored multiple ports for hcd rusb2

2023-07-26 19:52:33 +07:00

FreeRTOSConfig

update linker

2023-07-01 16:40:47 +07:00

linker/gcc

initial ra6m5 ek, board_test led + sw works

2023-07-01 21:43:52 +07:00

board_cfg.h

usb hs work with ra 6m5 ek

2023-07-05 17:13:01 +07:00

debug.jlinkscript

add jlinkscript for detect rtt

2023-07-03 16:35:22 +07:00

family.c

correct setting trace clock

2023-07-07 11:07:57 +07:00

family.cmake

updating hcd rusb2

2023-07-26 18:55:41 +07:00

family.mk

add PORT selection for makefile

2023-07-07 16:24:22 +07:00

r_ioport_cfg.h

move vector_data.h and ioport_cfg.h to common family

2023-07-03 10:54:37 +07:00

vector_data.h

usb hs work with ra 6m5 ek

2023-07-05 17:13:01 +07:00