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https://github.com/hathach/tinyusb.git
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add PORT selection for makefile
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e0f1ba8b0e
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@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5
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# For flash-jlink target
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JLINK_DEVICE = R7FA6M5BH
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# Port 1 is highspeed
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PORT ?= 1
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flash: flash-jlink
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@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
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set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
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set(FAMILY_MCUS RA CACHE INTERNAL "")
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set(FAMILY_MCUS RAXXX CACHE INTERNAL "")
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#------------------------------------
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# BOARD_TARGET
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@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
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FSP_RA = hw/mcu/renesas/fsp/ra/fsp
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include $(TOP)/$(BOARD_PATH)/board.mk
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# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
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PORT ?= 0
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CFLAGS += \
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-DCFG_TUSB_MCU=OPT_MCU_RAXXX \
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-DBOARD_TUD_RHPORT=$(PORT) \
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-Wno-error=undef \
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-Wno-error=strict-prototypes \
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-Wno-error=cast-align \
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@ -15,6 +19,14 @@ CFLAGS += \
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-nostartfiles \
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-ffreestanding
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ifeq ($(PORT), 1)
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CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
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$(info "Using PORT 1 HighSpeed")
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else
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CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
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$(info "Using PORT 0 FullSpeed")
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endif
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SRC_C += \
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src/portable/renesas/rusb2/dcd_rusb2.c \
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src/portable/renesas/rusb2/hcd_rusb2.c \
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@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
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// Highspeed FIFO is 32-bit
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if ( is_highspeed_regbase(rusb) ) {
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// TODO 32-bit access for better performance
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ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
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ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3);
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}else {
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@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
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static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
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{
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(void) rusb;
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// TODO 16/32-bit access for better performance
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uint8_t *p = (uint8_t*)buf;
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volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */
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while (len--) *p++ = *reg;
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