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63 lines
2.3 KiB
C
63 lines
2.3 KiB
C
#include <stdbool.h>
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#include <stdint.h>
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#include "mmu.h"
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// Each entry is a gig.
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volatile uint64_t level_1_table[512] __attribute__((aligned(4096)));
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// Third gig has peripherals
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uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
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void setup_mmu_flat_map(void) {
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// Set the first gig to regular access.
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level_1_table[0] = 0x0000000000000000 |
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MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
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MM_DESCRIPTOR_ACCESS_FLAG |
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MM_DESCRIPTOR_BLOCK |
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MM_DESCRIPTOR_VALID;
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level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
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MM_DESCRIPTOR_TABLE |
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MM_DESCRIPTOR_VALID;
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// Set peripherals to register access.
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for (uint64_t i = 480; i < 512; i++) {
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level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
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MM_DESCRIPTOR_EXECUTE_NEVER |
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MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
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MM_DESCRIPTOR_ACCESS_FLAG |
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MM_DESCRIPTOR_BLOCK |
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MM_DESCRIPTOR_VALID;
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}
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uint64_t mair = MAIR_VALUE;
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uint64_t tcr = TCR_VALUE;
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uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP;
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uint64_t sctlr = 0;
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__asm__ volatile (
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// Set MAIR
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"MSR MAIR_EL2, %[mair]\n\t"
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// Set TTBR0
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"MSR TTBR0_EL2, %[ttbr0]\n\t"
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// Set TCR
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"MSR TCR_EL2, %[tcr]\n\t"
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// The ISB forces these changes to be seen before the MMU is enabled.
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"ISB\n\t"
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// Read System Control Register configuration data
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"MRS %[sctlr], SCTLR_EL2\n\t"
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// Write System Control Register configuration data
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"ORR %[sctlr], %[sctlr], #1\n\t"
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// Set [M] bit and enable the MMU.
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"MSR SCTLR_EL2, %[sctlr]\n\t"
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// The ISB forces these changes to be seen by the next instruction
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"ISB\n\t"
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// "AT S1EL2R %[ttbr0]"
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: /* No outputs. */
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: [mair] "r" (mair),
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[tcr] "r" (tcr),
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[ttbr0] "r" (ttbr0),
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[sctlr] "r" (sctlr)
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);
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//__asm__ ("brk #123");
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//while (true) {}
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}
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