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MMU works
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parent
829f92d00f
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157
cortex-a.py
Normal file
157
cortex-a.py
Normal file
@ -0,0 +1,157 @@
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class Armv8AException(gdb.Command):
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def __init__ (self):
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super (Armv8AException, self).__init__ ("armv8a-exception", gdb.COMMAND_USER)
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def print_data_abort(self, frame, iss):
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isv = (iss >> 23) & 0x1
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sas = (iss >> 21) & 0x3
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sse = (iss >> 20) & 0x1
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srt = (iss >> 15) & 0x1f
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sf = (iss >> 14) & 0x1
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ar = (iss >> 13) & 0x1
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vncr = (iss >> 12) & 0x1
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_set = (iss >> 10) & 0x3
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fnv = (iss >> 9) & 0x1
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ea = (iss >> 8) & 0x1
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cm = (iss >> 7) & 0x1
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s1ptw = (iss >> 6) & 0x1
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wnr = (iss >> 5) & 0x1
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dfsc = iss & 0x1f
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if isv:
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# print("isv valid", sas, sse, srt, sf, ar)
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access_sizes = ("Byte", "Halfword", "Word", "Doubleword")
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print("Access size:", access_sizes[sas])
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print("Sign extended:", "Yes" if sse else "No")
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print("Register:", hex(srt), "64-bit" if sf else "32-bit")
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print("Acquire/Release:", "Yes" if ar else "No")
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if dfsc == 0b010000:
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print("Not on translation table walk")
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if not fnv:
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value = int(frame.read_register("FAR_EL2"))
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print("FAR", hex(value))
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elif dfsc == 0b000101:
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print("translation fault level 1")
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elif dfsc == 0b010001:
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print("tag check fault")
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elif dfsc == 0b100001:
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print("alignment fault")
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else:
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print(bin(dfsc))
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print(vncr, _set, fnv, ea, cm, s1ptw, wnr, dfsc)
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def print_instruction_abort(self, frame, iss):
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_set = (iss >> 10) & 0x3
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fnv = (iss >> 9) & 0x1
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ea = (iss >> 8) & 0x1
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s1ptw = (iss >> 6) & 0x1
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ifsc = iss & 0x1f
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if ifsc == 0b010000:
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print("Not on translation table walk")
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if not fnv:
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value = int(frame.read_register("FAR_EL2"))
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print("FAR", hex(value))
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elif ifsc == 0b00101:
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print("translation fault level 1")
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elif ifsc == 0b01001:
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print("access flag fault level 1")
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# elif dfsc == 0b100001:
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# print("alignment fault")
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else:
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print(bin(ifsc))
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def invoke (self, arg, from_tty):
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frame = gdb.selected_frame()
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value = int(frame.read_register("ESR_EL2"))
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if value == 0:
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return None
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iss2 = (value >> 32) & 0x1ff
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ec = (value >> 26) & 0x3ff
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il = (value >> 25) & 0x1
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iss = value & 0xffffff
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if ec == 0b000000:
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print("Unknown fault")
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elif ec == 0b000001:
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print("Trapped WF*")
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elif ec == 0b000011:
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print("Trapped MCR or MRC")
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elif ec == 0b000100:
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print("Trapped MCRR or MRRC")
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elif ec == 0b000101:
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print("Trapped MCR or MRC")
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elif ec == 0b000110:
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print("Trapped LDC or STC")
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elif ec == 0b000111:
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print("Trapped SIMD")
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elif ec == 0b001000:
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print("Trapped VMRS")
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elif ec == 0b001001:
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print("Trapped pointer authentication")
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elif ec == 0b001010:
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print("Trapped LD64B or ST64B*")
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elif ec == 0b001100:
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print("Trapped MRRC")
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elif ec == 0b001101:
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print("Branch target exception")
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elif ec == 0b001110:
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print("Illegal execution state")
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elif ec == 0b010001:
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print("SVC instruction")
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elif ec == 0b010010:
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print("HVC instruction")
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elif ec == 0b010011:
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print("SMC instruction")
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elif ec == 0b010101:
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print("SVC instruction")
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elif ec == 0b010110:
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print("HVC instruction")
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elif ec == 0b010111:
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print("SMC instruction")
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elif ec == 0b011000:
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print("Trapped MRS, MRS or system instruction")
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elif ec == 0b011001:
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print("Trapped SVE")
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elif ec == 0b011010:
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print("Trapped ERET")
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elif ec == 0b011100:
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print("Failed pointer authentication")
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elif ec == 0b100000:
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print("Instruction abort from lower level")
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elif ec == 0b100001:
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print("Instruction abort from same level")
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self.print_instruction_abort(frame, iss)
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elif ec == 0b100010:
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print("PC alignment failure")
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elif ec == 0b100100:
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print("Data abort from lower level")
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elif ec == 0b100101:
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print("Data abort from same level")
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self.print_data_abort(frame, iss)
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elif ec == 0b100110:
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print("SP alignment fault")
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elif ec == 0b101000:
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print("32-bit floating point exception")
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elif ec == 0b101100:
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print("64-bit floating point exception")
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elif ec == 0b101111:
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print("SError interrupt")
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elif ec == 0b110000:
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print("Breakpoint from lower level")
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elif ec == 0b110001:
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print("Breakpoint from same level")
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elif ec == 0b110010:
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print("Software step from lower level")
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elif ec == 0b110011:
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print("Software step from same level")
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elif ec == 0b110100:
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print ("Watch point from same level")
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elif ec == 0b110101:
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print("Watch point from lower level")
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elif ec == 0b111000:
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print("Breakpoint in aarch32 mode")
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elif ec == 0b111010:
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print("Vector catch in aarch32")
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elif ec == 0b111100:
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print("Brk instruction in aarch64")
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print(hex(int(value)), iss2, bin(ec), il, iss)
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Armv8AException()
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@ -3,6 +3,8 @@
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// GPIO
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// Pi 4 base address: 0xFE000000
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// Pi 3 base address: 0x3F000000
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enum {
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PERIPHERAL_BASE = 0xFE000000,
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GPFSEL0 = PERIPHERAL_BASE + 0x200000,
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#include "mmu.h"
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// Each entry is a gig.
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volatile uint64_t level_1_table[32] __attribute__((aligned(4096)));
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volatile uint64_t level_1_table[512] __attribute__((aligned(4096)));
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// Third gig has peripherals
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uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
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@ -14,9 +14,10 @@ void setup_mmu_flat_map(void) {
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// Set the first gig to regular access.
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level_1_table[0] = 0x0000000000000000 |
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MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
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MM_DESCRIPTOR_ACCESS_FLAG |
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MM_DESCRIPTOR_BLOCK |
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MM_DESCRIPTOR_VALID;
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level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
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level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
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MM_DESCRIPTOR_TABLE |
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MM_DESCRIPTOR_VALID;
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// Set peripherals to register access.
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@ -24,6 +25,7 @@ void setup_mmu_flat_map(void) {
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level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
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MM_DESCRIPTOR_EXECUTE_NEVER |
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MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
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MM_DESCRIPTOR_ACCESS_FLAG |
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MM_DESCRIPTOR_BLOCK |
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MM_DESCRIPTOR_VALID;
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}
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@ -47,12 +49,14 @@ void setup_mmu_flat_map(void) {
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// Set [M] bit and enable the MMU.
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"MSR SCTLR_EL2, %[sctlr]\n\t"
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// The ISB forces these changes to be seen by the next instruction
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"ISB"
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"ISB\n\t"
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// "AT S1EL2R %[ttbr0]"
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: /* No outputs. */
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: [mair] "r" (mair),
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[tcr] "r" (tcr),
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[ttbr0] "r" (ttbr0),
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[sctlr] "r" (sctlr)
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);
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while (true) {}
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//__asm__ ("brk #123");
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//while (true) {}
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}
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#define MT_DEVICE_nGnRnE 0x0
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#define MT_NORMAL_NC 0x1
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#define MT_DEVICE_nGnRnE_FLAGS 0x00
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#define MT_NORMAL_NC_FLAGS 0x44
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#define MT_NORMAL_NC_FLAGS 0xff
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#define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
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#define TCR_T0SZ (64 - 35)
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#define TCR_T0SZ (64 - 36)
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#define TCR_PS (0x01 << 16) // 36-bit physical address
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#define TCR_TG0_4K (0 << 14)
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#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
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@ -36,6 +36,7 @@
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// Block attributes
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#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
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#define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52)
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#define MM_DESCRIPTOR_ACCESS_FLAG (0x1ull << 10)
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#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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#define RHPORT_REGS_BASE 0x7e980000
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#define RHPORT_REGS_BASE 0xfe980000
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#define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
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#define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)
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@ -438,6 +438,7 @@ void dcd_init (uint8_t rhport)
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{
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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TU_LOG(2, " dcd_init");
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USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
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@ -477,9 +478,14 @@ void dcd_init (uint8_t rhport)
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// Reset core after selecting PHY
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// Wait AHB IDLE, reset then wait until it is cleared
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while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
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TU_LOG(2, " resetting");
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usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
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TU_LOG(2, " waiting");
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while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
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TU_LOG(2, " reset done");
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// Restart PHY clock
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*((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
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