hathach
|
c5d958d104
|
add ra6m1 board
|
2023-07-01 17:27:45 +07:00 |
|
hathach
|
50381f7b4c
|
refactor to match fsp_cfg
|
2023-07-01 17:09:09 +07:00 |
|
hathach
|
22fb66436d
|
update linker
|
2023-07-01 16:40:47 +07:00 |
|
hathach
|
99e75e6a8a
|
rework ra build
|
2023-07-01 12:41:12 +07:00 |
|
hathach
|
3cb4d73899
|
clean up ra makefile
|
2023-06-30 14:52:04 +07:00 |
|
hathach
|
eb7fcf1b74
|
add CPU_CORE for all family
|
2023-06-24 18:38:41 +07:00 |
|
hathach
|
ffdffc7e06
|
rename FREERTOS_PORT to FREERTOS_PORTABLE_SRC
also fix trailing spaces
|
2023-03-16 23:11:11 +07:00 |
|
hathach
|
e0b1de923c
|
add ra4m1_ek board
|
2023-03-16 22:43:58 +07:00 |
|
hathach
|
2a10d5c20b
|
rename ra board name
|
2023-03-16 11:39:53 +07:00 |
|
hathach
|
bc2127b330
|
rename file link to rusb2
|
2023-03-16 11:03:53 +07:00 |
|
hathach
|
7428a16d2d
|
remove ra submodules
|
2023-03-11 08:23:21 +07:00 |
|
Rafael Silva
|
60aae59eeb
|
style code for consistency with existing codebase
|
2022-06-02 09:35:30 +01:00 |
|
Rafael Silva
|
e0220c6594
|
fix int handling for host in ek_ra4m3 port
|
2022-06-02 09:35:30 +01:00 |
|
Rafael Silva
|
4c89776a27
|
add renesas ek-ra4m3 board port
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
|
2022-06-02 09:35:30 +01:00 |
|