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add ra4m1_ek board
This commit is contained in:
hathach
parent
2a10d5c20b
commit
e0b1de923c
@ -297,8 +297,17 @@ LPC55
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- `LPCXpresso 55s69 EVK <https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK>`__
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- `MCU-Link <https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK>`__
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Renesas RX
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----------
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Renesas
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-------
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RA
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^^
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- `Evaluation Kit for RA4M1 <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group>`__
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- `Evaluation Kit for RA4M3 <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group>`__
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RX
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^^
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- `GR-CITRUS <https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus>`__
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- `Renesas RX65N Target Board <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n>`__
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17
hw/bsp/ra/boards/ra4m1_ek/board.mk
Normal file
17
hw/bsp/ra/boards/ra4m1_ek/board.mk
Normal file
@ -0,0 +1,17 @@
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CFLAGS += \
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-mcpu=cortex-m4 \
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-mfloat-abi=hard \
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-mfpu=fpv4-sp-d16 \
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-DCFG_TUSB_MCU=OPT_MCU_RAXXX
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FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m1
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FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld
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# For flash-jlink target
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JLINK_DEVICE = R7FA4M1AB
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JLINK_IF = SWD
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flash: flash-jlink
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35
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
Normal file
35
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
Normal file
@ -0,0 +1,35 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#include "board.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#undef RA_NOT_DEFINED
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#define BSP_CFG_RTOS (0)
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x400)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif /* BSP_CFG_H_ */
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21
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
Normal file
21
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
Normal file
@ -0,0 +1,21 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
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#define BSP_CFG_CLOCKS_OVERRIDE (0)
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#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
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#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
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#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
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#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
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#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */
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#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
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#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
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#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
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#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
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#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
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#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
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#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
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#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
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#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
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#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
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#endif /* BSP_CLOCK_CFG_H_ */
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5
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h
Normal file
5
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h
Normal file
@ -0,0 +1,5 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (4)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */
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11
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h
Normal file
11
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h
Normal file
@ -0,0 +1,11 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA4M1AB3CFP
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (262144)
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#define BSP_RAM_SIZE_BYTES (32768)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (100)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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78
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
Normal file
78
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
Normal file
@ -0,0 +1,78 @@
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/* generated configuration header file through renesas e2 studio */
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA4M1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (24000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (32000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 4
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#define BSP_HOCO_HZ (48000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 5
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#define BSP_HOCO_HZ (64000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
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#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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/*
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ID Code
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Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
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WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
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*/
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#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#endif /* BSP_MCU_FAMILY_CFG_H_ */
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7
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h
Normal file
7
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h
Normal file
@ -0,0 +1,7 @@
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/* generated configuration header file - do not edit */
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#ifndef R_IOPORT_CFG_H_
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#define R_IOPORT_CFG_H_
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#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
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#endif /* R_IOPORT_CFG_H_ */
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5
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
Normal file
5
hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
Normal file
@ -0,0 +1,5 @@
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/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
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#define TU_IRQn 0
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#define USBFS_RESUME_IRQn 1
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#define USBFS_FIFO_0_IRQn 2
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#define USBFS_FIFO_1_IRQn 3
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232
hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
Normal file
232
hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
Normal file
@ -0,0 +1,232 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022, Rafael Silva
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include <stdio.h>
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#include "bsp/board.h"
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#include "bsp_api.h"
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#include "r_ioport.h"
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#include "r_ioport_api.h"
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#include "renesas.h"
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/* Key code for writing PRCR register. */
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#define BSP_PRV_PRCR_KEY (0xA500U)
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#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
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#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
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#define SW1 (BSP_IO_PORT_01_PIN_05)
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#define LED1 (BSP_IO_PORT_01_PIN_06)
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#define LED_STATE_ON 1
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#define BUTTON_STATE_ACTIVE 0
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/* ISR prototypes */
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void usbfs_interrupt_handler(void);
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void usbfs_resume_handler(void);
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void usbfs_d0fifo_handler(void);
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void usbfs_d1fifo_handler(void);
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BSP_DONT_REMOVE const
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fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
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[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
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[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
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[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
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[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
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};
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const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
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[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
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[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
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[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
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[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
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};
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const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
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{ .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) },
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{ .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) },
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{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
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{ .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
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{ .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
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};
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const ioport_cfg_t g_bsp_pin_cfg = {
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.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
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.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
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};
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ioport_instance_ctrl_t g_ioport_ctrl;
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const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void usbfs_interrupt_handler(void)
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{
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IRQn_Type irq = R_FSP_CurrentIrqGet();
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R_BSP_IrqStatusClear(irq);
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#if CFG_TUH_ENABLED
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tuh_int_handler(0);
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#endif
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#if CFG_TUD_ENABLED
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tud_int_handler(0);
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#endif
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}
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|
||||
void usbfs_resume_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void usbfs_d0fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void usbfs_d1fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
|
||||
/* Enable USB_BASE */
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
|
||||
R_MSTP->MSTPCRB &= ~(1U << 11U);
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Init systick */
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
bsp_io_level_t lvl;
|
||||
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
|
||||
return lvl == BUTTON_STATE_ACTIVE;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
|
||||
int close(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
int fstat(int fd, void *pstat)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pstat;
|
||||
return 0;
|
||||
}
|
||||
off_t lseek(int fd, off_t pos, int whence)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pos;
|
||||
(void) whence;
|
||||
return 0;
|
||||
}
|
||||
int isatty(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
738
hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
Normal file
738
hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
Normal file
@ -0,0 +1,738 @@
|
||||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x8000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x40000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x01010018;
|
||||
ID_CODE_LENGTH = 0x20;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
|
||||
/*
|
||||
XIP_SECONDARY_SLOT_IMAGE = 1;
|
||||
*/
|
||||
|
||||
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
|
||||
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
|
||||
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
|
||||
|
||||
/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
|
||||
__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
|
||||
|
||||
ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
|
||||
ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
|
||||
DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
|
||||
DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
|
||||
NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0;
|
||||
NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0;
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
|
||||
|
||||
OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
|
||||
|
||||
/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
|
||||
* Bootloader images do not configure option settings because they are owned by the bootloader.
|
||||
* FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
|
||||
__bl_FSP_BOOTABLE_IMAGE = 1;
|
||||
__bln_FSP_BOOTABLE_IMAGE = 1;
|
||||
PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
|
||||
__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
|
||||
__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH;
|
||||
__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
|
||||
__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
__bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
|
||||
__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START;
|
||||
__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
|
||||
XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
|
||||
FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
|
||||
XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
|
||||
FLASH_IMAGE_START;
|
||||
LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
|
||||
DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
|
||||
FLASH_LENGTH;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH
|
||||
DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH
|
||||
FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18
|
||||
OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34
|
||||
OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be DEFINED in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
* __qspi_flash_start__
|
||||
* __qspi_flash_end__
|
||||
* __qspi_flash_code_size__
|
||||
* __qspi_region_max_size__
|
||||
* __qspi_region_start_address__
|
||||
* __qspi_region_end_address__
|
||||
* __ospi_device_0_start__
|
||||
* __ospi_device_0_end__
|
||||
* __ospi_device_0_code_size__
|
||||
* __ospi_device_0_region_max_size__
|
||||
* __ospi_device_0_region_start_address__
|
||||
* __ospi_device_0_region_end_address__
|
||||
* __ospi_device_1_start__
|
||||
* __ospi_device_1_end__
|
||||
* __ospi_device_1_code_size__
|
||||
* __ospi_device_1_region_max_size__
|
||||
* __ospi_device_1_region_start_address__
|
||||
* __ospi_device_1_region_end_address__
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Initialized ITCM data. */
|
||||
.itcm_data :
|
||||
{
|
||||
/* Start of ITCM Secure Trustzone region. */
|
||||
__tz_ITCM_S = ABSOLUTE(ITCM_START);
|
||||
|
||||
/* All ITCM data start */
|
||||
__itcm_data_start__ = .;
|
||||
|
||||
KEEP(*(.itcm_data*))
|
||||
|
||||
/* All ITCM data end */
|
||||
__itcm_data_end__ = .;
|
||||
|
||||
/*
|
||||
* Start of the ITCM Non-Secure Trustzone region.
|
||||
* ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192);
|
||||
} > ITCM
|
||||
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
|
||||
|
||||
/* Allocate flash write-boundary-aligned
|
||||
* space for sce9 wrapped public keys for mcuboot if the module is used.
|
||||
*/
|
||||
. = ALIGN(128);
|
||||
KEEP(*(.mcuboot_sce9_key*))
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
__tz_RAM_S = ORIGIN(RAM);
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
/* Start address of the initial values for .dtcm_data. */
|
||||
__dtcm_data_init_start = __etext + __data_end__ - __data_start__;
|
||||
|
||||
/* Initialized DTCM data. */
|
||||
.dtcm_data :
|
||||
{
|
||||
/* Start of DTCM Secure Trustzone region. */
|
||||
__tz_DTCM_S = ABSOLUTE(DTCM_START);
|
||||
|
||||
/* Initialized DTCM data start */
|
||||
__dtcm_data_start__ = .;
|
||||
|
||||
KEEP(*(.dtcm_data*))
|
||||
|
||||
/* Initialized DTCM data end */
|
||||
__dtcm_data_end__ = .;
|
||||
} > DTCM AT > FLASH
|
||||
|
||||
/* Uninitialized DTCM data. */
|
||||
.dtcm_noinit (NOLOAD):
|
||||
{
|
||||
/* Uninitialized DTCM data start */
|
||||
__dtcm_noinit_start = .;
|
||||
|
||||
KEEP(*(.dtcm_noinit*))
|
||||
|
||||
/* Uninitialized DTCM data end */
|
||||
__dtcm_noinit_end = .;
|
||||
|
||||
/*
|
||||
* Start of the DTCM Non-Secure Trustzone region.
|
||||
* DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192);
|
||||
} > DTCM
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section. */
|
||||
|
||||
/* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */
|
||||
/* 1. Get the address to the next block after the .data section in FLASH. */
|
||||
DATA_END = LOADADDR(.data) + SIZEOF(.data);
|
||||
/* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */
|
||||
SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024);
|
||||
/* 3. Manually specify the start location for .gnu.sgstubs */
|
||||
.gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
|
||||
{
|
||||
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
_start_sg = .;
|
||||
*(.gnu.sgstubs*)
|
||||
. = ALIGN(32);
|
||||
_end_sg = .;
|
||||
} > FLASH
|
||||
|
||||
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
|
||||
FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
|
||||
|
||||
/* QSPI_FLASH section to be downloaded via debugger */
|
||||
.qspi_flash :
|
||||
{
|
||||
__qspi_flash_start__ = .;
|
||||
KEEP(*(.qspi_flash*))
|
||||
KEEP(*(.code_in_qspi*))
|
||||
__qspi_flash_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.qspi_non_retentive : AT (__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
__qspi_non_retentive_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
|
||||
|
||||
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
|
||||
__qspi_region_start_address__ = __qspi_flash_start__;
|
||||
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
|
||||
|
||||
/* Support for OctaRAM */
|
||||
.OSPI_DEVICE_0_NO_LOAD (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ospi_device_0_start__ = .;
|
||||
*(.ospi_device_0_no_load*)
|
||||
. = ALIGN(4);
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0_RAM
|
||||
|
||||
.OSPI_DEVICE_1_NO_LOAD (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ospi_device_1_start__ = .;
|
||||
*(.ospi_device_1_no_load*)
|
||||
. = ALIGN(4);
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1_RAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
|
||||
|
||||
/* OSPI_DEVICE_0 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_0 :
|
||||
{
|
||||
__ospi_device_0_start__ = .;
|
||||
KEEP(*(.ospi_device_0*))
|
||||
KEEP(*(.code_in_ospi_device_0*))
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
__ospi_device_0_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
|
||||
|
||||
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
|
||||
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
|
||||
|
||||
/* OSPI_DEVICE_1 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_1 :
|
||||
{
|
||||
__ospi_device_1_start__ = .;
|
||||
KEEP(*(.ospi_device_1*))
|
||||
KEEP(*(.code_in_ospi_device_1*))
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
__ospi_device_1_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
|
||||
|
||||
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
|
||||
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
|
||||
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
|
||||
|
||||
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
|
||||
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
|
||||
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
|
||||
|
||||
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
|
||||
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
|
||||
.ns_buffer (NOLOAD):
|
||||
{
|
||||
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
|
||||
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
|
||||
|
||||
KEEP(*(.ns_buffer*))
|
||||
} > RAM
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
. = ORIGIN(DATA_FLASH);
|
||||
__tz_DATA_FLASH_S = .;
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
|
||||
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
|
||||
} > DATA_FLASH
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_S = ORIGIN(SDRAM);
|
||||
|
||||
/* SDRAM */
|
||||
.sdram (NOLOAD):
|
||||
{
|
||||
__SDRAM_Start = .;
|
||||
KEEP(*(.sdram*))
|
||||
KEEP(*(.frame*))
|
||||
__SDRAM_End = .;
|
||||
} > SDRAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_N = __SDRAM_End;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_N = __ID_Code_End;
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
|
||||
|
||||
.option_setting_ofs :
|
||||
{
|
||||
__OPTION_SETTING_OFS_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
|
||||
KEEP(*(.option_setting_ofs2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
__OPTION_SETTING_OFS_End = .;
|
||||
} > OPTION_SETTING_OFS = 0xFF
|
||||
|
||||
.option_setting_sas :
|
||||
{
|
||||
__OPTION_SETTING_SAS_Start = .;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_SAS_End = .;
|
||||
} > OPTION_SETTING_SAS = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
|
||||
|
||||
.option_setting_ns :
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_ofs3))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps3))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps3))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
|
||||
|
||||
.option_setting_s :
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs3_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec3))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec3))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} > OPTION_SETTING_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
|
||||
}
|
||||
@ -13,3 +13,5 @@ LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA4M3AF
|
||||
JLINK_IF = SWD
|
||||
|
||||
flash: flash-jlink
|
||||
|
||||
@ -91,11 +91,11 @@ void usbfs_interrupt_handler(void)
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
@ -104,37 +104,39 @@ void usbfs_resume_handler(void)
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void usbfs_d0fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void usbfs_d1fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user