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adding hcd_dcache_clean/hcd_dcache_invalidate

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hathach 2023-05-17 16:14:35 +07:00
parent a9aa0e3a1a
commit eb89df4115
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4 changed files with 41 additions and 0 deletions
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15
hw/bsp/imxrt/family.cmake
View File

@ -144,6 +144,21 @@ function(family_configure_target TARGET)
COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
)
# Flash using jlink
set(JLINKEXE JLinkExe)
file(GENERATE
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
CONTENT "halt
loadfile $<TARGET_FILE:${TARGET}>
r
go
exit"
)
add_custom_target(${TARGET}-jlink
DEPENDS ${TARGET}
COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
)
endfunction()

10
src/host/hcd.h
View File

@ -104,6 +104,16 @@ typedef struct
uint8_t speed;
} hcd_devtree_info_t;
//--------------------------------------------------------------------+
// Memory API
//--------------------------------------------------------------------+
// clean/flush data cache: write cache -> memory
void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
// invalidate data cache: mark cache as invalid, next read will read from memory
void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+

9
src/portable/chipidea/ci_hs/hcd_ci_hs.c
View File

@ -41,6 +41,15 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
#include "ci_hs_imxrt.h"
void hcd_dcache_clean(void* addr, uint32_t data_size) {
SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size);
}
void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
}
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h"
#else

7
src/portable/ehci/ehci.h
View File

@ -268,6 +268,7 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
// EHCI Operational Register
//--------------------------------------------------------------------+
enum {
// Bit 0-5 has maskable in interrupt enabled register
EHCI_INT_MASK_USB = TU_BIT(0),
EHCI_INT_MASK_ERROR = TU_BIT(1),
EHCI_INT_MASK_PORT_CHANGE = TU_BIT(2),
@ -276,6 +277,12 @@ enum {
EHCI_INT_MASK_ASYNC_ADVANCE = TU_BIT(5),
EHCI_INT_MASK_NXP_SOF = TU_BIT(7),
EHCI_INT_MASK_HC_HALTED = TU_BIT(12),
EHCI_INT_MASK_RECLAIMATION = TU_BIT(13),
EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14),
EHCI_INT_MASK_ASYNC_SCHED_STATUS = TU_BIT(15),
EHCI_INT_MASK_NXP_ASYNC = TU_BIT(18),
EHCI_INT_MASK_NXP_PERIODIC = TU_BIT(19),