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https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
fix error on EHCI causes xfer error in non-queued qhd which cause memory fault
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2
.idea/cmake.xml
generated
2
.idea/cmake.xml
generated
@ -2,6 +2,7 @@
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<project version="4">
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<component name="CMakeSharedSettings">
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<configurations>
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<configuration PROFILE_NAME="rt1060 evk" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
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<configuration PROFILE_NAME="pca10095" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" BUILD_OPTIONS="-v" />
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<configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" BUILD_OPTIONS="-v" />
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<configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
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@ -27,6 +28,7 @@
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</configuration>
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<configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
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<configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
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<configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
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</configurations>
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</component>
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</project>
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@ -84,10 +84,6 @@
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#define CFG_TUH_RPI_PIO_USB 1
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#endif
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// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
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// #define CFG_TUSB_DEBUG 0
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/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
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* Tinyusb use follows macros to declare transferring memory so that they can be put
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* into those specific section.
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@ -133,7 +129,7 @@
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#endif
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#ifndef CFG_TUH_MEM_ALIGN
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#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
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#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
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#endif
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#define CFG_TUH_HUB 1
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@ -93,16 +93,30 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
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// Debug
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//--------------------------------------------------------------------+
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#if CFG_TUSB_DEBUG >= EHCI_DBG
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static inline void print_portsc(ehci_registers_t* regs)
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{
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static inline void print_portsc(ehci_registers_t* regs) {
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TU_LOG_HEX(EHCI_DBG, regs->portsc);
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TU_LOG(EHCI_DBG, " Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
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TU_LOG(EHCI_DBG, " Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
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TU_LOG(EHCI_DBG, " Port Enabled : %u\r\n", regs->portsc_bm.port_enabled);
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TU_LOG(EHCI_DBG, " Port Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change);
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TU_LOG(EHCI_DBG, " Connect Status : %u\r\n", regs->portsc_bm.current_connect_status);
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TU_LOG(EHCI_DBG, " Connect Change : %u\r\n", regs->portsc_bm.connect_status_change);
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TU_LOG(EHCI_DBG, " Enabled : %u\r\n", regs->portsc_bm.port_enabled);
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TU_LOG(EHCI_DBG, " Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change);
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TU_LOG(EHCI_DBG, " Port Reset : %u\r\n", regs->portsc_bm.port_reset);
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TU_LOG(EHCI_DBG, " Port Power : %u\r\n", regs->portsc_bm.port_power);
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TU_LOG(EHCI_DBG, " OverCurr Change: %u\r\n", regs->portsc_bm.over_current_change);
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TU_LOG(EHCI_DBG, " Force Resume : %u\r\n", regs->portsc_bm.force_port_resume);
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TU_LOG(EHCI_DBG, " Suspend : %u\r\n", regs->portsc_bm.suspend);
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TU_LOG(EHCI_DBG, " Reset : %u\r\n", regs->portsc_bm.port_reset);
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TU_LOG(EHCI_DBG, " Power : %u\r\n", regs->portsc_bm.port_power);
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}
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static inline void print_intr(uint32_t intr) {
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TU_LOG_HEX(EHCI_DBG, intr);
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TU_LOG(EHCI_DBG, " USB Interrupt : %u\r\n", (intr & EHCI_INT_MASK_USB) ? 1 : 0);
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TU_LOG(EHCI_DBG, " USB Error : %u\r\n", (intr & EHCI_INT_MASK_ERROR) ? 1 : 0);
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TU_LOG(EHCI_DBG, " Port Change Detect : %u\r\n", (intr & EHCI_INT_MASK_PORT_CHANGE) ? 1 : 0);
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TU_LOG(EHCI_DBG, " Frame List Rollover: %u\r\n", (intr & EHCI_INT_MASK_FRAMELIST_ROLLOVER) ? 1 : 0);
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TU_LOG(EHCI_DBG, " Host System Error : %u\r\n", (intr & EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR) ? 1 : 0);
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TU_LOG(EHCI_DBG, " Async Advance : %u\r\n", (intr & EHCI_INT_MASK_ASYNC_ADVANCE) ? 1 : 0);
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// TU_LOG(EHCI_DBG, " Interrupt on Async: %u\r\n", (intr & EHCI_INT_MASK_NXP_ASYNC));
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// TU_LOG(EHCI_DBG, " Periodic Schedule : %u\r\n", (intr & EHCI_INT_MASK_NXP_PERIODIC));
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}
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#else
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@ -166,8 +180,8 @@ void hcd_port_reset(uint8_t rhport)
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ehci_registers_t* regs = ehci_data.regs;
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// mask out all change bits since they are Write 1 to clear
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uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
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// mask out Write-1-to-Clear bits
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uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
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// EHCI Table 2-16 PortSC
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// when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit.
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@ -347,7 +361,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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// Power Control (PPC) field in the HCSPARAMS register.
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if (ehci_data.cap_regs->hcsparams_bm.port_power_control) {
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// mask out all change bits since they are Write 1 to clear
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uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL);
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uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_W1C);
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portsc |= ECHI_PORTSC_MASK_PORT_POWER;
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regs->portsc = portsc;
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@ -621,9 +635,14 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
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p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
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// if (XFER_RESULT_FAILED == xfer_result ) {
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// TU_LOG1(" QHD xfer err count: %d\n", qtd_overlay->err_count);
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// TU_BREAKPOINT(); // TODO skip unplugged device
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// while(1){}
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// }
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// No TD, probably an signal noise ?
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TU_VERIFY(p_qhd->p_qtd_list_head, );
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p_qhd->p_qtd_list_head->used = 0; // free QTD
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qtd_remove_1st_from_qhd(p_qhd);
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@ -710,7 +729,8 @@ void hcd_int_handler(uint8_t rhport)
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if (int_status & EHCI_INT_MASK_PORT_CHANGE)
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{
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uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_CHANGE_ALL;
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// Including: Force port resume, over-current change, enable/disable change and connect status change.
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uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C;
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print_portsc(regs);
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if (regs->portsc_bm.connect_status_change)
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@ -306,7 +306,7 @@ enum {
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EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8),
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ECHI_PORTSC_MASK_PORT_POWER = TU_BIT(12),
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EHCI_PORTSC_MASK_CHANGE_ALL =
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EHCI_PORTSC_MASK_W1C =
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
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EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE |
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EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
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