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Add a note about data cache.
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@ -243,6 +243,10 @@
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//--------------------------------------------------------------------+
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// DWC2 controller: use DMA for data transfer
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// For processors with data cache enabled, USB endpoint buffer region
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// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
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// For example, on Cortex-M7 the MPU region can be configured as normal
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// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
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#ifndef CFG_TUD_DWC2_DMA
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#define CFG_TUD_DWC2_DMA 0
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#endif
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