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@ -252,6 +252,55 @@ static void dfifo_init(uint8_t rhport) {
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dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
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}
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// Read a single data packet from receive FIFO
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static void dfifo_read_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
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(void) rhport;
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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volatile const uint32_t* rx_fifo = dwc2->fifo[0];
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// Reading full available 32 bit words from fifo
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uint16_t full_words = len >> 2;
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while (full_words--) {
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tu_unaligned_write32(dst, *rx_fifo);
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dst += 4;
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}
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// Read the remaining 1-3 bytes from fifo
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uint8_t const bytes_rem = len & 0x03;
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if (bytes_rem != 0) {
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uint32_t const tmp = *rx_fifo;
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dst[0] = tu_u32_byte0(tmp);
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if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
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if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
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}
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}
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// Write a single data packet to EPIN FIFO
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static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
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(void) rhport;
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
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// Pushing full available 32 bit words to fifo
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uint16_t full_words = len >> 2;
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while (full_words--) {
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*tx_fifo = tu_unaligned_read32(src);
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src += 4;
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}
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// Write the remaining 1-3 bytes into fifo
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uint8_t const bytes_rem = len & 0x03;
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if (bytes_rem) {
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uint32_t tmp_word = src[0];
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if (bytes_rem > 1) tmp_word |= (src[1] << 8);
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if (bytes_rem > 2) tmp_word |= (src[2] << 16);
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*tx_fifo = tmp_word;
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}
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}
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//--------------------------------------------------------------------
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// Endpoint
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//--------------------------------------------------------------------
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@ -899,56 +948,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
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}
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}
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/*------------------------------------------------------------------*/
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// Read a single data packet from receive FIFO
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static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
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(void) rhport;
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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volatile const uint32_t* rx_fifo = dwc2->fifo[0];
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// Reading full available 32 bit words from fifo
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uint16_t full_words = len >> 2;
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while (full_words--) {
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tu_unaligned_write32(dst, *rx_fifo);
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dst += 4;
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}
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// Read the remaining 1-3 bytes from fifo
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uint8_t const bytes_rem = len & 0x03;
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if (bytes_rem != 0) {
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uint32_t const tmp = *rx_fifo;
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dst[0] = tu_u32_byte0(tmp);
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if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
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if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
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}
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}
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// Write a single data packet to EPIN FIFO
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static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
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(void) rhport;
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
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// Pushing full available 32 bit words to fifo
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uint16_t full_words = len >> 2;
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while (full_words--) {
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*tx_fifo = tu_unaligned_read32(src);
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src += 4;
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}
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// Write the remaining 1-3 bytes into fifo
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uint8_t const bytes_rem = len & 0x03;
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if (bytes_rem) {
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uint32_t tmp_word = src[0];
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if (bytes_rem > 1) tmp_word |= (src[1] << 8);
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if (bytes_rem > 2) tmp_word |= (src[2] << 16);
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*tx_fifo = tmp_word;
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}
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}
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//--------------------------------------------------------------------
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// Interrupt Handler
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//--------------------------------------------------------------------
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static void handle_rxflvl_irq(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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@ -1002,7 +1004,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
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tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
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} else {
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// Linear buffer
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read_fifo_packet(rhport, xfer->buffer, bcnt);
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dfifo_read_packet(rhport, xfer->buffer, bcnt);
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// Increment pointer to xfer data
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xfer->buffer += bcnt;
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@ -1171,7 +1173,7 @@ static void handle_epin_irq(uint8_t rhport) {
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volatile uint32_t* tx_fifo = dwc2->fifo[n];
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tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
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} else {
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write_fifo_packet(rhport, n, xfer->buffer, packet_size);
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dfifo_write_packet(rhport, n, xfer->buffer, packet_size);
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// Increment pointer to xfer data
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xfer->buffer += packet_size;
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@ -244,7 +244,7 @@
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// DWC2 controller: use DMA for data transfer
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#ifndef CFG_TUD_DWC2_DMA
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#define CFG_TUD_DWC2_DMA 1
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#define CFG_TUD_DWC2_DMA 0
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#endif
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// Enable PIO-USB software host controller
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