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addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to get passed otg clock reset

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hathach 2023-10-30 22:21:58 +07:00
parent 27a2c8cba4
commit a4c542a7b4
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GPG Key ID: F5D50C6D51D17CBA
6 changed files with 277 additions and 52 deletions
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12
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
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@ -99,6 +99,18 @@ static void SystemClock_Config(void) {
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
// USB Clock
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
/** Set the OTG PHY reference clock selection
*/
HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
} }
static void SystemPower_Config(void) { static void SystemPower_Config(void) {

11
hw/bsp/stm32u5/family.c
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@ -177,7 +177,6 @@ void board_init(void) {
NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif #endif
// Disable VBUS sense (B device) // Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
@ -185,11 +184,17 @@ void board_init(void) {
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
/* USB clock enable */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
__HAL_RCC_USBPHYC_CLK_ENABLE();
/* Enable USB power on Pwrctrl CR2 register */ /* Enable USB power on Pwrctrl CR2 register */
HAL_PWREx_EnableVddUSB(); HAL_PWREx_EnableVddUSB();
HAL_PWREx_EnableUSBHSTranceiverSupply();
/* USB clock enable */ /*Configuring the SYSCFG registers OTG_HS PHY*/
__HAL_RCC_USB_OTG_HS_CLK_ENABLE(); HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
#endif // USB_OTG_FS #endif // USB_OTG_FS

54
src/portable/synopsys/dwc2/dwc2_info.md Normal file
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@ -0,0 +1,54 @@
| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 |
|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 |
| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 |
| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 |
| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 |
| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 |
| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 |
| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 |
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |

158
src/portable/synopsys/dwc2/dwc2_info.py Normal file
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@ -0,0 +1,158 @@
import click
import ctypes
import pandas as pd
# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4']
dwc2_reg_value = {
'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30],
'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0],
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030]
}
# Combine dwc2_info with dwc2_reg_list
# dwc2_info = {
# 'BCM2711 (Pi4)': {
# 'guid': 0x2708A000,
# 'gsnpsid': 0x4F54280A,
# 'ghwcfg1': 0,
# 'ghwcfg2': 0x228DDD50,
# 'ghwcfg3': 0xFF000E8,
# 'ghwcfg4': 0x1FF00020
# },
dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
class GHWCFG2(ctypes.LittleEndianStructure):
_fields_ = [
("op_mode", ctypes.c_uint32, 3),
("arch", ctypes.c_uint32, 2),
("point2point", ctypes.c_uint32, 1),
("hs_phy_type", ctypes.c_uint32, 2),
("fs_phy_type", ctypes.c_uint32, 2),
("num_dev_ep", ctypes.c_uint32, 4),
("num_host_ch", ctypes.c_uint32, 4),
("period_channel_support", ctypes.c_uint32, 1),
("enable_dynamic_fifo", ctypes.c_uint32, 1),
("mul_cpu_int", ctypes.c_uint32, 1),
("reserved21", ctypes.c_uint32, 1),
("nperiod_tx_q_depth", ctypes.c_uint32, 2),
("host_period_tx_q_depth", ctypes.c_uint32, 2),
("dev_token_q_depth", ctypes.c_uint32, 5),
("otg_enable_ic_usb", ctypes.c_uint32, 1)
]
class GHWCFG3(ctypes.LittleEndianStructure):
_fields_ = [
("xfer_size_width", ctypes.c_uint32, 4),
("packet_size_width", ctypes.c_uint32, 3),
("otg_enable", ctypes.c_uint32, 1),
("i2c_enable", ctypes.c_uint32, 1),
("vendor_ctrl_itf", ctypes.c_uint32, 1),
("optional_feature_removed", ctypes.c_uint32, 1),
("synch_reset", ctypes.c_uint32, 1),
("otg_adp_support", ctypes.c_uint32, 1),
("otg_enable_hsic", ctypes.c_uint32, 1),
("battery_charger_support", ctypes.c_uint32, 1),
("lpm_mode", ctypes.c_uint32, 1),
("total_fifo_size", ctypes.c_uint32, 16)
]
class GHWCFG4(ctypes.LittleEndianStructure):
_fields_ = [
("num_dev_period_in_ep", ctypes.c_uint32, 4),
("power_optimized", ctypes.c_uint32, 1),
("ahb_freq_min", ctypes.c_uint32, 1),
("hibernation", ctypes.c_uint32, 1),
("reserved7", ctypes.c_uint32, 3),
("service_interval_mode", ctypes.c_uint32, 1),
("ipg_isoc_en", ctypes.c_uint32, 1),
("acg_enable", ctypes.c_uint32, 1),
("reserved13", ctypes.c_uint32, 1),
("utmi_phy_data_width", ctypes.c_uint32, 2),
("dev_ctrl_ep_num", ctypes.c_uint32, 4),
("iddg_filter_enabled", ctypes.c_uint32, 1),
("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
("a_valid_filter_enabled", ctypes.c_uint32, 1),
("b_valid_filter_enabled", ctypes.c_uint32, 1),
("dedicated_fifos", ctypes.c_uint32, 1),
("num_dev_in_eps", ctypes.c_uint32, 4),
("dma_desc_enable", ctypes.c_uint32, 1),
("dma_dynamic", ctypes.c_uint32, 1)
]
@click.group()
def cli():
pass
@cli.command()
@click.argument('mcus', nargs=-1)
@click.option('-a', '--all', is_flag=True, help='Print all bit-field values')
def info(mcus, all):
"""Print DWC2 register values for given MCU(s)"""
if len(mcus) == 0:
mcus = dwc2_info
for mcu in mcus:
for entry in dwc2_info:
if mcu.lower() in entry.lower():
print(f"## {entry}")
for r_name, r_value in dwc2_info[entry].items():
print(f"{r_name} = 0x{r_value:08X}")
# Print bit-field values
if all and r_name.upper() in globals():
class_name = globals()[r_name.upper()]
ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
for field_name, field_type, _ in class_name._fields_:
print(f" {field_name} = {getattr(ghwcfg, field_name)}")
@cli.command()
def render_md():
"""Render dwc2_info to Markdown table"""
# Create an empty list to hold the dictionaries
dwc2_info_list = []
#Iterate over the dwc2_info dictionary and extract fields
for device, reg_values in dwc2_info.items():
entry_dict = {"Device": device}
for r_name, r_value in reg_values.items():
entry_dict[r_name] = f"0x{r_value:08X}"
# Print bit-field values
if r_name.upper() in globals():
class_name = globals()[r_name.upper()]
ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
for field_name, field_type, _ in class_name._fields_:
entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name)
dwc2_info_list.append(entry_dict)
# Create a Pandas DataFrame from the list of dictionaries
df = pd.DataFrame(dwc2_info_list).set_index('Device')
# Transpose the DataFrame to switch rows and columns
df = df.T
#print(df)
# Write the Markdown table to a file
with open('dwc2_info.md', 'w') as md_file:
md_file.write(df.to_markdown())
if __name__ == '__main__':
cli()

93
src/portable/synopsys/dwc2/dwc2_stm32.h
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@ -28,7 +28,7 @@
#define _DWC2_STM32_H_ #define _DWC2_STM32_H_
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
// EP_MAX : Max number of bi-directional endpoints including EP0 // EP_MAX : Max number of bi-directional endpoints including EP0
@ -84,17 +84,15 @@
#elif CFG_TUSB_MCU == OPT_MCU_STM32U5 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
#include "stm32u5xx.h" #include "stm32u5xx.h"
// NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY) // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
// USB_OTG_FS_BASE and OTG_FS_IRQn not defined #ifdef USB_OTG_FS
#if !defined(USB_OTG_FS) #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
#define EP_MAX_FS 6
#define EP_FIFO_SIZE_FS 1280
#else
#define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE
#define EP_MAX_HS 9 #define EP_MAX_HS 9
#define EP_FIFO_SIZE_HS 4096 #define EP_FIFO_SIZE_HS 4096
//#define OTG_FS_IRQn OTG_HS_IRQn
#else
#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
#define EP_MAX_FS 6
#define EP_FIFO_SIZE_FS 1280
#endif #endif
#else #else
#error "Unsupported MCUs" #error "Unsupported MCUs"
@ -109,15 +107,14 @@
// On STM32 for consistency we associate // On STM32 for consistency we associate
// - Port0 to OTG_FS, and Port1 to OTG_HS // - Port0 to OTG_FS, and Port1 to OTG_HS
static const dwc2_controller_t _dwc2_controller[] = static const dwc2_controller_t _dwc2_controller[] = {
{ #ifdef USB_OTG_FS_PERIPH_BASE
#ifdef USB_OTG_FS_PERIPH_BASE { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS }, #endif
#endif
#ifdef USB_OTG_HS_PERIPH_BASE #ifdef USB_OTG_HS_PERIPH_BASE
{ .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS }, { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
#endif #endif
}; };
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
@ -128,40 +125,33 @@ static const dwc2_controller_t _dwc2_controller[] =
// extern uint32_t SystemCoreClock; // extern uint32_t SystemCoreClock;
TU_ATTR_ALWAYS_INLINE TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_enable(uint8_t rhport) static inline void dwc2_dcd_int_enable(uint8_t rhport) {
{ NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
} }
TU_ATTR_ALWAYS_INLINE TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_disable (uint8_t rhport) static inline void dwc2_dcd_int_disable(uint8_t rhport) {
{ NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
} }
TU_ATTR_ALWAYS_INLINE TU_ATTR_ALWAYS_INLINE
static inline void dwc2_remote_wakeup_delay(void) static inline void dwc2_remote_wakeup_delay(void) {
{
// try to delay for 1 ms // try to delay for 1 ms
uint32_t count = SystemCoreClock / 1000; uint32_t count = SystemCoreClock / 1000;
while ( count-- ) __NOP(); while (count--) __NOP();
} }
// MCU specific PHY init, called BEFORE core reset // MCU specific PHY init, called BEFORE core reset
static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
{ if (hs_phy_type == HS_PHY_TYPE_NONE) {
if ( hs_phy_type == HS_PHY_TYPE_NONE )
{
// Enable on-chip FS PHY // Enable on-chip FS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
}else } else {
{ // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
// Disable FS PHY
dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
// Enable on-chip HS PHY // Enable on-chip HS PHY
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
{
#ifdef USB_HS_PHYC #ifdef USB_HS_PHYC
// Enable UTMI HS PHY // Enable UTMI HS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
@ -200,34 +190,39 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
} }
// MCU specific PHY update, it is called AFTER init() and core reset // MCU specific PHY update, it is called AFTER init() and core reset
static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
{
// used to set turnaround time for fullspeed, nothing to do in highspeed mode // used to set turnaround time for fullspeed, nothing to do in highspeed mode
if ( hs_phy_type == HS_PHY_TYPE_NONE ) if (hs_phy_type == HS_PHY_TYPE_NONE) {
{
// Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
uint32_t turnaround; uint32_t turnaround;
if ( SystemCoreClock >= 32000000u ) if (SystemCoreClock >= 32000000u) {
turnaround = 0x6u; turnaround = 0x6u;
else if ( SystemCoreClock >= 27500000u ) } else if (SystemCoreClock >= 27500000u) {
turnaround = 0x7u; turnaround = 0x7u;
else if ( SystemCoreClock >= 24000000u ) } else if (SystemCoreClock >= 24000000u) {
turnaround = 0x8u; turnaround = 0x8u;
else if ( SystemCoreClock >= 21800000u ) } else if (SystemCoreClock >= 21800000u) {
turnaround = 0x9u; turnaround = 0x9u;
else if ( SystemCoreClock >= 20000000u ) }
else if (SystemCoreClock >= 20000000u) {
turnaround = 0xAu; turnaround = 0xAu;
else if ( SystemCoreClock >= 18500000u ) }
else if (SystemCoreClock >= 18500000u) {
turnaround = 0xBu; turnaround = 0xBu;
else if ( SystemCoreClock >= 17200000u ) }
else if (SystemCoreClock >= 17200000u) {
turnaround = 0xCu; turnaround = 0xCu;
else if ( SystemCoreClock >= 16000000u ) }
else if (SystemCoreClock >= 16000000u) {
turnaround = 0xDu; turnaround = 0xDu;
else if ( SystemCoreClock >= 15000000u ) }
else if (SystemCoreClock >= 15000000u) {
turnaround = 0xEu; turnaround = 0xEu;
else }
else {
turnaround = 0xFu; turnaround = 0xFu;
}
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos); dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
} }

1
src/portable/synopsys/dwc2/dwc2_type.h
View File

@ -43,6 +43,7 @@ typedef struct
#define DWC2_CORE_REV_3_00a 0x4f54300a #define DWC2_CORE_REV_3_00a 0x4f54300a
#define DWC2_CORE_REV_3_10a 0x4f54310a #define DWC2_CORE_REV_3_10a 0x4f54310a
#define DWC2_CORE_REV_4_00a 0x4f54400a #define DWC2_CORE_REV_4_00a 0x4f54400a
#define DWC2_CORE_REV_4_11a 0x4f54411a
#define DWC2_CORE_REV_4_20a 0x4f54420a #define DWC2_CORE_REV_4_20a 0x4f54420a
#define DWC2_FS_IOT_REV_1_00a 0x5531100a #define DWC2_FS_IOT_REV_1_00a 0x5531100a
#define DWC2_HS_IOT_REV_1_00a 0x5532100a #define DWC2_HS_IOT_REV_1_00a 0x5532100a