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https://github.com/hathach/tinyusb.git
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EHCI adding dcahe support, passing enumertaion
This commit is contained in:
hathach
parent
eb89df4115
commit
a3e017bfd2
@ -108,12 +108,18 @@ typedef struct
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// Memory API
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//--------------------------------------------------------------------+
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// clean/flush data cache: write cache -> memory
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// clean/flush data cache: write cache -> memory.
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// Required before an DMA TX transfer to make sure data is in memory
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void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
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// invalidate data cache: mark cache as invalid, next read will read from memory
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// Required BOTH before and after an DMA RX transfer
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void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
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// clean and invalidate data cache
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// Required before an DMA transfer where memory is both read/write by DMA
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void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
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@ -194,6 +200,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr)
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event.event_id = HCD_EVENT_DEVICE_ATTACH;
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event.connection.hub_addr = 0;
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event.connection.hub_port = 0;
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hcd_event_handler(&event, in_isr);
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}
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@ -224,7 +231,6 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred
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event.xfer_complete.result = result;
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event.xfer_complete.len = xferred_bytes;
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hcd_event_handler(&event, in_isr);
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}
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@ -50,6 +50,10 @@
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SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
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}
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void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
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SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
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}
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#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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#include "ci_hs_lpc18_43.h"
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#else
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@ -92,7 +92,7 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
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//--------------------------------------------------------------------+
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// Debug
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//--------------------------------------------------------------------+
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#if CFG_TUSB_DEBUG >= EHCI_DBG
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#if CFG_TUSB_DEBUG >= (EHCI_DBG + 1)
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static inline void print_portsc(ehci_registers_t* regs) {
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TU_LOG_HEX(EHCI_DBG, regs->portsc);
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TU_LOG(EHCI_DBG, " Connect Status : %u\r\n", regs->portsc_bm.current_connect_status);
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@ -159,7 +159,7 @@ static inline ehci_qtd_t* qtd_find_free (void);
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static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
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static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
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static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
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static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes);
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static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
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static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
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static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
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@ -325,28 +325,27 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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// 3 --> period_head_arr[3] (8ms)
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// TODO EHCI_FRAMELIST_SIZE with other size than 8
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for(uint32_t i=0; i<FRAMELIST_SIZE; i++)
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{
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for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) {
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framelist[i].address = (uint32_t) period_1ms;
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framelist[i].type = EHCI_QTYPE_QHD;
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framelist[i].type = EHCI_QTYPE_QHD;
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}
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for(uint32_t i=0; i<FRAMELIST_SIZE; i+=2)
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{
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for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) {
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list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
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}
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for(uint32_t i=1; i<FRAMELIST_SIZE; i+=4)
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{
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for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) {
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list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
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}
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list_insert(framelist+3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
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list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
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period_1ms->terminate = 1;
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regs->periodic_list_base = (uint32_t) framelist;
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if(hcd_dcache_clean) {
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hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t));
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}
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//------------- TT Control (NXP only) -------------//
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regs->nxp_tt_control = 0;
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@ -430,6 +429,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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// TODO might need to disable async/period list
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list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
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if(hcd_dcache_clean) {
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hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
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hcd_dcache_clean(list_head, sizeof(ehci_link_t));
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}
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return true;
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}
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@ -441,9 +445,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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ehci_qtd_t* td = &ehci_data.control[dev_addr].qtd;
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qtd_init(td, setup_packet, 8);
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td->pid = EHCI_PID_SETUP;
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td->int_on_complete = 1;
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td->next.terminate = 1;
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td->pid = EHCI_PID_SETUP;
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if (hcd_dcache_clean && hcd_dcache_clean_invalidate) {
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hcd_dcache_clean((void *) setup_packet, 8);
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hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t));
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}
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// sw region
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qhd->p_qtd_list_head = td;
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@ -452,6 +459,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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// attach TD
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qhd->qtd_overlay.next.address = (uint32_t) td;
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if (hcd_dcache_clean_invalidate) {
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hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
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}
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return true;
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}
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@ -462,41 +473,48 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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ehci_qhd_t* qhd;
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ehci_qtd_t* qtd;
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if ( epnum == 0 )
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{
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ehci_qhd_t* qhd = qhd_control(dev_addr);
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ehci_qtd_t* qtd = qtd_control(dev_addr);
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qhd = qhd_control(dev_addr);
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qtd = qtd_control(dev_addr);
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qtd_init(qtd, buffer, buflen);
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// first first data toggle is always 1 (data & setup stage)
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qtd->data_toggle = 1;
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qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
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qtd->int_on_complete = 1;
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qtd->next.terminate = 1;
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// sw region
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qhd->p_qtd_list_head = qtd;
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qhd->p_qtd_list_tail = qtd;
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// attach TD
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qhd->qtd_overlay.next.address = (uint32_t) qtd;
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}else
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{
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ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
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ehci_qtd_t *p_qtd = qtd_find_free();
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TU_ASSERT(p_qtd);
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qhd = qhd_get_from_addr(dev_addr, ep_addr);
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qtd = qtd_find_free();
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TU_ASSERT(qtd);
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qtd_init(p_qtd, buffer, buflen);
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p_qtd->pid = p_qhd->pid;
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qtd_init(qtd, buffer, buflen);
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qtd->pid = qhd->pid;
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}
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// Insert TD to QH
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qtd_insert_to_qhd(p_qhd, p_qtd);
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if (hcd_dcache_clean && hcd_dcache_clean_invalidate) {
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// IN transfer: invalidate buffer, OUT transfer: clean buffer
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if (dir) {
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hcd_dcache_invalidate(buffer, buflen);
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}else {
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hcd_dcache_clean(buffer, buflen);
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}
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hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
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}
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p_qhd->p_qtd_list_tail->int_on_complete = 1;
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// Software: assign TD to QHD
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qhd->p_qtd_list_head = qtd;
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qhd->p_qtd_list_tail = qtd;
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// attach head QTD to QHD start transferring
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p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head;
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// attach TD to QHD start transferring
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qhd->qtd_overlay.next.address = (uint32_t) qtd;
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if (hcd_dcache_clean_invalidate) {
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hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
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}
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return true;
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@ -551,6 +569,11 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
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while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
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{
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ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
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if (hcd_dcache_invalidate) {
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hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
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}
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bool const is_ioc = (qtd->int_on_complete != 0);
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uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
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@ -573,8 +596,12 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
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ehci_qhd_t *p_qhd = async_head;
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do
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{
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if ( !p_qhd->qtd_overlay.halted ) // halted or error is processed in error isr
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{
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if (hcd_dcache_invalidate) {
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hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
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}
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// halted or error is processed in error isr
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if ( !p_qhd->qtd_overlay.halted ) {
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qhd_xfer_complete_isr(p_qhd);
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}
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p_qhd = qhd_next(p_qhd);
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@ -640,8 +667,8 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
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// while(1){}
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// }
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// No TD, probably an signal noise ?
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TU_VERIFY(p_qhd->p_qtd_list_head, );
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// No TD yet, it is probably the probably an signal noise ?
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TU_ASSERT(p_qhd->p_qtd_list_head, );
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p_qhd->p_qtd_list_head->used = 0; // free QTD
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qtd_remove_1st_from_qhd(p_qhd);
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@ -714,17 +741,19 @@ static void xfer_error_isr(uint8_t hostid)
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void hcd_int_handler(uint8_t rhport)
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{
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ehci_registers_t* regs = ehci_data.regs;
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uint32_t const int_status = regs->status;
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uint32_t int_status = regs->status;
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int_status &= regs->inten;
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regs->status = int_status; // Acknowledge handled interrupt
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if (int_status == 0) return;
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if (int_status & EHCI_INT_MASK_HC_HALTED) {
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// something seriously wrong, maybe forget to flush/invalidate cache
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TU_BREAKPOINT();
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TU_LOG1(" HC halted\n");
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return;
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}
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if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER)
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{
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ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
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regs->status = EHCI_INT_MASK_FRAMELIST_ROLLOVER; // Acknowledge
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}
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if (int_status & EHCI_INT_MASK_PORT_CHANGE)
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@ -739,31 +768,41 @@ void hcd_int_handler(uint8_t rhport)
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}
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regs->portsc |= port_status; // Acknowledge change bits in portsc
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regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
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}
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if (int_status & EHCI_INT_MASK_ERROR)
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{
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xfer_error_isr(rhport);
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regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
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}
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//------------- some QTD/SITD/ITD with IOC set is completed -------------//
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if (int_status & EHCI_INT_MASK_NXP_ASYNC)
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{
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async_list_xfer_complete_isr( qhd_async_head(rhport) );
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async_list_xfer_complete_isr(qhd_async_head(rhport));
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regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge
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}
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if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
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{
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for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
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{
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period_list_xfer_complete_isr( rhport, i );
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period_list_xfer_complete_isr(rhport, i);
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}
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regs->status = EHCI_INT_MASK_NXP_PERIODIC; // Acknowledge
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}
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if (int_status & EHCI_INT_MASK_USB) {
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// TODO standard EHCI xfer complete
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regs->status = EHCI_INT_MASK_USB; // Acknowledge
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}
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//------------- There is some removed async previously -------------//
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if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) // need to place after EHCI_INT_MASK_NXP_ASYNC
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{
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// need to place after EHCI_INT_MASK_NXP_ASYNC
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if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) {
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async_advance_isr(rhport);
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regs->status = EHCI_INT_MASK_ASYNC_ADVANCE; // Acknowledge
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}
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}
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@ -918,28 +957,30 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
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}
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}
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static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes)
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static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
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{
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tu_memclr(p_qtd, sizeof(ehci_qtd_t));
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tu_memclr(qtd, sizeof(ehci_qtd_t));
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qtd->used = 1;
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p_qtd->used = 1;
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qtd->next.terminate = 1; // init to null
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qtd->alternate.terminate = 1; // not used, always set to terminated
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qtd->active = 1;
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qtd->err_count = 3; // TODO 3 consecutive errors tolerance
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qtd->data_toggle = 0;
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qtd->int_on_complete = 1;
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qtd->total_bytes = total_bytes;
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qtd->expected_bytes = total_bytes;
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p_qtd->next.terminate = 1; // init to null
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p_qtd->alternate.terminate = 1; // not used, always set to terminated
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p_qtd->active = 1;
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p_qtd->err_count = 3; // TODO 3 consecutive errors tolerance
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p_qtd->data_toggle = 0;
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p_qtd->total_bytes = total_bytes;
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p_qtd->expected_bytes = total_bytes;
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p_qtd->buffer[0] = (uint32_t) buffer;
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qtd->buffer[0] = (uint32_t) buffer;
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for(uint8_t i=1; i<5; i++)
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{
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p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
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qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096;
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}
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}
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//------------- List Managing Helper -------------//
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// insert at head
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static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
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{
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new->address = current->address;
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@ -165,6 +165,7 @@ typedef struct TU_ATTR_ALIGNED(32)
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uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
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uint8_t reserved2[2];
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// TODO USBH will only queue 1 TD per QHD, thus we can remove the list
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ehci_qtd_t * volatile p_qtd_list_head; // head of the scheduled TD list
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ehci_qtd_t * volatile p_qtd_list_tail; // tail of the scheduled TD list
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} ehci_qhd_t;
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