mirror of
https://github.com/hathach/tinyusb.git
synced 2025-02-14 00:40:29 +00:00
minor update
This commit is contained in:
parent
e9109f36ba
commit
993473312b
@ -29,6 +29,9 @@
|
||||
|
||||
#if CFG_TUD_ENABLED && defined(TUP_USBIP_MUSB)
|
||||
|
||||
#define MUSB_DEBUG 2
|
||||
#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport])
|
||||
|
||||
#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
|
||||
/* GCC warns that an address may be unaligned, even though
|
||||
* the target CPU has the capability for unaligned memory access. */
|
||||
@ -49,10 +52,6 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
|
||||
#error "Unsupported MCU"
|
||||
#endif
|
||||
|
||||
#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport])
|
||||
|
||||
#define MUSB_DEBUG 2
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
*------------------------------------------------------------------*/
|
||||
@ -60,9 +59,9 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
|
||||
#define REQUEST_TYPE_INVALID (0xFFu)
|
||||
|
||||
typedef union {
|
||||
uint8_t u8;
|
||||
uint16_t u16;
|
||||
uint32_t u32;
|
||||
volatile uint8_t u8;
|
||||
volatile uint16_t u16;
|
||||
volatile uint32_t u32;
|
||||
} hw_fifo_t;
|
||||
|
||||
typedef struct TU_ATTR_PACKED
|
||||
@ -223,11 +222,12 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
|
||||
|
||||
static void process_setup_packet(uint8_t rhport) {
|
||||
musb_regs_t* musb_regs = MUSB_REGS(rhport);
|
||||
|
||||
// Read setup packet
|
||||
uint32_t *p = (void*)&_dcd.setup_packet;
|
||||
volatile uint32_t *fifo_ptr = &musb_regs->fifo[0];
|
||||
|
||||
p[0] = *fifo_ptr;
|
||||
p[1] = *fifo_ptr;
|
||||
p[0] = *fifo_ptr;
|
||||
p[1] = *fifo_ptr;
|
||||
|
||||
_dcd.pipe0.buf = NULL;
|
||||
_dcd.pipe0.length = 0;
|
||||
@ -407,6 +407,7 @@ static void process_ep0(uint8_t rhport)
|
||||
uint_fast8_t csrl = ep_csr->csr0l;
|
||||
|
||||
// TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl);
|
||||
// 21.1.5: endpoint 0 service routine as peripheral
|
||||
|
||||
if (csrl & USB_CSRL0_STALLED) {
|
||||
/* Returned STALL packet to HOST. */
|
||||
@ -705,7 +706,10 @@ void dcd_edpt_close_all(uint8_t rhport)
|
||||
fifo_reset(musb, i, 0);
|
||||
fifo_reset(musb, i, 1);
|
||||
}
|
||||
|
||||
#if MUSB_CFG_DYNAMIC_FIFO
|
||||
alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE;
|
||||
#endif
|
||||
|
||||
if (ie) musb_dcd_int_enable(rhport);
|
||||
}
|
||||
@ -822,10 +826,12 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
||||
* ISR
|
||||
*-------------------------------------------------------------------*/
|
||||
void dcd_int_handler(uint8_t rhport) {
|
||||
musb_regs_t* musb_regs = MUSB_REGS(rhport);
|
||||
const uint8_t saved_index = musb_regs->index; // save endpoint index
|
||||
|
||||
//Part specific ISR setup/entry
|
||||
musb_dcd_int_handler_enter(rhport);
|
||||
|
||||
musb_regs_t* musb_regs = MUSB_REGS(rhport);
|
||||
uint_fast8_t intr_usb = musb_regs->intr_usb; // a read will clear this interrupt status
|
||||
uint_fast8_t intr_tx = musb_regs->intr_tx; // a read will clear this interrupt status
|
||||
uint_fast8_t intr_rx = musb_regs->intr_rx; // a read will clear this interrupt status
|
||||
@ -865,8 +871,7 @@ void dcd_int_handler(uint8_t rhport) {
|
||||
intr_rx &= ~TU_BIT(num);
|
||||
}
|
||||
|
||||
//Part specific ISR exit
|
||||
musb_dcd_int_handler_exit(rhport);
|
||||
musb_regs->index = saved_index; // restore endpoint index
|
||||
}
|
||||
|
||||
#endif
|
||||
|
@ -42,11 +42,6 @@ const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS };
|
||||
#if CFG_TUD_ENABLED
|
||||
#define USBHS_M31_CLOCK_RECOVERY
|
||||
|
||||
// Mapping of peripheral instances to port. Currently just 1.
|
||||
static mxc_usbhs_regs_t* const musb_periph_inst[] = {
|
||||
MXC_USBHS
|
||||
};
|
||||
|
||||
// Mapping of IRQ numbers to port. Currently just 1.
|
||||
static const IRQn_Type musb_irqs[] = {
|
||||
USB_IRQn
|
||||
@ -77,31 +72,21 @@ static inline void musb_dcd_int_clear(uint8_t rhport) {
|
||||
NVIC_ClearPendingIRQ(musb_irqs[rhport]);
|
||||
}
|
||||
|
||||
//Used to save and restore user's register map when interrupt occurs
|
||||
static volatile unsigned isr_saved_index = 0;
|
||||
|
||||
static inline void musb_dcd_int_handler_enter(uint8_t rhport) {
|
||||
mxc_usbhs_regs_t* hs_phy = MXC_USBHS;
|
||||
uint32_t mxm_int, mxm_int_en, mxm_is;
|
||||
|
||||
//save current register index
|
||||
isr_saved_index = musb_periph_inst[rhport]->index;
|
||||
|
||||
//Handle PHY specific events
|
||||
mxm_int = musb_periph_inst[rhport]->mxm_int;
|
||||
mxm_int_en = musb_periph_inst[rhport]->mxm_int_en;
|
||||
mxm_int = hs_phy->mxm_int;
|
||||
mxm_int_en = hs_phy->mxm_int_en;
|
||||
mxm_is = mxm_int & mxm_int_en;
|
||||
musb_periph_inst[rhport]->mxm_int = mxm_is;
|
||||
hs_phy->mxm_int = mxm_is;
|
||||
|
||||
if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void musb_dcd_int_handler_exit(uint8_t rhport) {
|
||||
//restore register index
|
||||
musb_periph_inst[rhport]->index = isr_saved_index;
|
||||
}
|
||||
|
||||
static inline void musb_dcd_phy_init(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
mxc_usbhs_regs_t* hs_phy = MXC_USBHS;
|
||||
@ -120,7 +105,6 @@ static inline void musb_dcd_phy_init(uint8_t rhport) {
|
||||
hs_phy->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64);
|
||||
hs_phy->m31_phy_xcfgi_127_96 = 0;
|
||||
|
||||
|
||||
#ifdef USBHS_M31_CLOCK_RECOVERY
|
||||
hs_phy->m31_phy_noncry_rstb = 1;
|
||||
hs_phy->m31_phy_noncry_en = 1;
|
||||
|
@ -87,11 +87,6 @@ static inline void musb_dcd_int_handler_enter(uint8_t rhport) {
|
||||
//Nothing to do for this part
|
||||
}
|
||||
|
||||
static inline void musb_dcd_int_handler_exit(uint8_t rhport) {
|
||||
(void)rhport;
|
||||
//Nothing to do for this part
|
||||
}
|
||||
|
||||
#if 0
|
||||
typedef struct {
|
||||
uint_fast16_t beg; /* offset of including first element */
|
||||
|
Loading…
x
Reference in New Issue
Block a user