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Merge branch 'hathach:master' into MCX

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jerpa77 2024-02-22 15:47:45 -06:00 committed by GitHub
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21 changed files with 1053 additions and 52 deletions
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51
examples/device/cdc_msc_freertos/src/main.c
View File

@ -52,7 +52,8 @@
#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
#endif
#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE
#define CDC_STACK_SIZE configMINIMAL_STACK_SIZE
#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF PROTOTYPES
@ -69,21 +70,22 @@ enum {
BLINK_SUSPENDED = 2500,
};
// static timer & task
// static task
#if configSUPPORT_STATIC_ALLOCATION
StaticTimer_t blinky_tmdef;
StackType_t blinky_stack[BLINKY_STACK_SIZE];
StaticTask_t blinky_taskdef;
StackType_t usb_device_stack[USBD_STACK_SIZE];
StaticTask_t usb_device_taskdef;
StackType_t cdc_stack[CDC_STACK_SZIE];
StackType_t cdc_stack[CDC_STACK_SIZE];
StaticTask_t cdc_taskdef;
#endif
TimerHandle_t blinky_tm;
static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
static void led_blinky_cb(TimerHandle_t xTimer);
static void usb_device_task(void *param);
void led_blinking_task(void* param);
void cdc_task(void *params);
//--------------------------------------------------------------------+
@ -94,22 +96,20 @@ int main(void) {
board_init();
#if configSUPPORT_STATIC_ALLOCATION
// soft timer for blinky
blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
// blinky task
xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
// Create a task for tinyusb device stack
xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
// Create CDC task
xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef);
#else
blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
#endif
xTimerStart(blinky_tm, 0);
// skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
vTaskStartScheduler();
@ -154,12 +154,12 @@ static void usb_device_task(void *param) {
// Invoked when device is mounted
void tud_mount_cb(void) {
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
blink_interval_ms = BLINK_MOUNTED;
}
// Invoked when device is unmounted
void tud_umount_cb(void) {
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
blink_interval_ms = BLINK_NOT_MOUNTED;
}
// Invoked when usb bus is suspended
@ -167,16 +167,12 @@ void tud_umount_cb(void) {
// Within 7ms, device must draw an average of current less than 2.5 mA from bus
void tud_suspend_cb(bool remote_wakeup_en) {
(void) remote_wakeup_en;
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
blink_interval_ms = BLINK_SUSPENDED;
}
// Invoked when usb bus is resumed
void tud_resume_cb(void) {
if (tud_mounted()) {
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
} else {
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
}
blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
@ -235,10 +231,17 @@ void tud_cdc_rx_cb(uint8_t itf) {
//--------------------------------------------------------------------+
// BLINKING TASK
//--------------------------------------------------------------------+
static void led_blinky_cb(TimerHandle_t xTimer) {
(void) xTimer;
void led_blinking_task(void* param) {
(void) param;
static uint32_t start_ms = 0;
static bool led_state = false;
board_led_write(led_state);
led_state = 1 - led_state; // toggle
while (1) {
// Blink every interval ms
vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
start_ms += blink_interval_ms;
board_led_write(led_state);
led_state = 1 - led_state; // toggle
}
}

3
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
View File

@ -8,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast
# All source paths should be relative to the top level.
LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
SRC_C += \
$(MCU_DIR)/project_template/clock_config.c \
# For flash-jlink target
JLINK_DEVICE = K32L2A41xxxxA

491
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c Normal file
View File

@ -0,0 +1,491 @@
/*
* Copyright 2019 ,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
* Note: The clock could not be set when it is being used as system clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M),
* so before setting FIRC, change to use another available clock source.
*
* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
*
* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
* Wait until the system clock source is changed to target source.
*
* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
* Supported run mode and clock restrictions could be found in Reference Manual.
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v7.0
processor: K32L2A41xxxxA
package_id: K32L2A41VLL1A
mcu_data: ksdk2_0
processor_version: 9.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_smc.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define SCG_CLKOUTCNFG_SIRC 2U /*!< SCG CLKOUT clock select: Slow IRC */
#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
#define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
#define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_SetScgOutSel
* Description : Set the SCG clock out select (CLKOUTSEL).
* Param setting : The selected clock source.
*
*END**************************************************************************/
static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
{
SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_FircSafeConfig
* Description : This function is used to safely configure FIRC clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M).
* Before setting FIRC, change to use SIRC as system clock,
* then configure FIRC. After FIRC is set, change back to use FIRC
* in case SIRC need to be configured.
* Param fircConfig : FIRC configuration.
*
*END**************************************************************************/
static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
{
scg_sys_clk_config_t curConfig;
const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
.div1 = kSCG_AsyncClkDisable,
.div3 = kSCG_AsyncClkDivBy2,
.range = kSCG_SircRangeHigh};
scg_sys_clk_config_t sysClkSafeConfigSource = {
.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved1 = 0,
.reserved2 = 0,
.reserved3 = 0,
#endif
.divCore = kSCG_SysClkDivBy1, /* Core clock divider */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved4 = 0,
#endif
.src = kSCG_SysClkSrcSirc, /* System clock source */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved5 = 0,
#endif
};
/* Init Sirc. */
CLOCK_InitSirc(&scgSircConfig);
/* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
/* Wait for clock source switch finished. */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != sysClkSafeConfigSource.src);
/* Init Firc. */
CLOCK_InitFirc(fircConfig);
/* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
/* Wait for clock source switch finished. */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != sysClkSafeConfigSource.src);
}
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
- {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
- {id: SIRC_CLK.outFreq, value: 8 MHz}
- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
sources:
- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
{
.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved1 = 0,
.reserved2 = 0,
.reserved3 = 0,
#endif
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved4 = 0,
#endif
.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved5 = 0,
#endif
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
{
.freq = 32768U, /* System Oscillator frequency: 32768Hz */
.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
.workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 3: divided by 2 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL, /* Fast IRC Trim disabled */
};
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
{
.enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
.div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
.src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
.prediv = 0, /* Divided by 1 */
.mult = 0, /* Multiply Factor is 16 */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
scg_sys_clk_config_t curConfig;
/* Init SOSC according to board configuration. */
CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
/* Set the XTAL0 frequency based on board settings. */
CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
/* Init FIRC. */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
/* Init SIRC. */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
/* Set SCG to FIRC mode. */
CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
/* Wait for clock source switch finished. */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockHSRUN
outputs:
- {id: CLKOUT.outFreq, value: 8 MHz}
- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: SIRC_CLK.outFreq, value: 8 MHz}
- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
- {id: System_clock.outFreq, value: 96 MHz}
settings:
- {id: SCGMode, value: SPLL}
- {id: powerMode, value: HSRUN}
- {id: CLKOUTConfig, value: 'yes'}
- {id: SCG.DIVSLOW.scale, value: '4'}
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.PREDIV.scale, value: '4'}
- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
sources:
- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockHSRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
{
.divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved1 = 0,
.reserved2 = 0,
.reserved3 = 0,
#endif
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved4 = 0,
#endif
.src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved5 = 0,
#endif
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
{
.freq = 32768U, /* System Oscillator frequency: 32768Hz */
.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
.workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL, /* Fast IRC Trim disabled */
};
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
.div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
.src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
.prediv = 3, /* Divided by 4 */
.mult = 0, /* Multiply Factor is 16 */
};
/*******************************************************************************
* Code for BOARD_BootClockHSRUN configuration
******************************************************************************/
void BOARD_BootClockHSRUN(void)
{
scg_sys_clk_config_t curConfig;
/* Init SOSC according to board configuration. */
CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
/* Set the XTAL0 frequency based on board settings. */
CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
/* Init FIRC. */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
/* Init SIRC. */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
/* Init SysPll. */
CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
/* Set HSRUN power mode. */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
/* Set SCG to SPLL mode. */
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
/* Wait for clock source switch finished. */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
/* Set SCG CLKOUT selection. */
CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: SIRC_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
- {id: System_clock.outFreq, value: 8 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: powerMode, value: VLPR}
- {id: SCG.DIVSLOW.scale, value: '8'}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
sources:
- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
{
.divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved1 = 0,
.reserved2 = 0,
.reserved3 = 0,
#endif
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved4 = 0,
#endif
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
.reserved5 = 0,
#endif
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
.workMode = kSCG_SysOscModeExt, /* Use external clock */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL, /* Fast IRC Trim disabled */
};
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
{
.enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
.div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
.src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
.prediv = 0, /* Divided by 1 */
.mult = 0, /* Multiply Factor is 16 */
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
/* Init FIRC. */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
/* Init SIRC. */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
/* Allow SMC all power modes. */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
/* Set VLPR power mode. */
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
}

164
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h Normal file
View File

@ -0,0 +1,164 @@
/*
* Copyright 2019 ,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 32768U /*!< Board xtal0 frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief SCG set for BOARD_BootClockRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
*/
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockHSRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
*/
/*******************************************************************************
* API for BOARD_BootClockHSRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockHSRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 8000000U /*!< Core clock frequency: 8000000Hz */
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
*/
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

3
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
View File

@ -8,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
# All source paths should be relative to the top level.
LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
SRC_C += \
$(MCU_DIR)/project_template/clock_config.c \
# For flash-jlink target
JLINK_DEVICE = K32L2B31xxxxA

220
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c Normal file
View File

@ -0,0 +1,220 @@
/*
* Copyright 2019 ,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
* and flash clock are in allowed range during clock mode switch.
*
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
*
* 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
*
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v7.0
processor: K32L2B31xxxxA
package_id: K32L2B31VLH0A
mcu_data: ksdk2_0
processor_version: 9.0.0
board: FRDM-K32L2B
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_smc.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 24 MHz}
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: Flash_clock.outFreq, value: 24 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGIRCLK.outFreq, value: 8 MHz}
- {id: MCGPCLK.outFreq, value: 48 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: MCGMode, value: HIRC}
- {id: MCG.CLKS.sel, value: MCG.HIRC}
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
sources:
- {id: MCG.HIRC.outFreq, value: 48 MHz}
- {id: OSC.OSC.outFreq, value: 32 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
{
.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
.hircEnableInNotHircMode = true, /* HIRC source is enabled */
};
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
{
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
};
const osc_config_t oscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
}
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Set MCG to HIRC mode. */
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 1 MHz}
- {id: Core_clock.outFreq, value: 2 MHz}
- {id: Flash_clock.outFreq, value: 1 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGIRCLK.outFreq, value: 2 MHz}
- {id: System_clock.outFreq, value: 2 MHz}
settings:
- {id: MCGMode, value: LIRC2M}
- {id: powerMode, value: VLPR}
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
- {id: RTCCLKOUTConfig, value: 'yes'}
- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
sources:
- {id: MCG.LIRC.outFreq, value: 2 MHz}
- {id: OSC.OSC.outFreq, value: 32.768 kHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
{
.outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
.hircEnableInNotHircMode = false, /* HIRC source is not enabled */
};
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
{
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
};
const osc_config_t oscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
.oscerConfig =
{
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
}
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Set MCG to LIRC2M mode. */
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
SMC_SetPowerModeVlpr(SMC, false);
#else
SMC_SetPowerModeVlpr(SMC);
#endif
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
}

110
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h Normal file
View File

@ -0,0 +1,110 @@
/*
* Copyright 2019 ,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
*/
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
/*! @brief OSC set for BOARD_BootClockRUN configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */
/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
*/
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

3
hw/bsp/nrf/boards/pca10095/board.cmake
View File

@ -1,6 +1,9 @@
set(MCU_VARIANT nrf5340_application)
set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
# enable max3421 host driver for this board
set(MAX3421_HOST 1)
function(update_board TARGET)
target_sources(${TARGET} PRIVATE
${NRFX_DIR}/drivers/src/nrfx_usbreg.c

4
hw/bsp/nrf/boards/pca10095/board.h
View File

@ -42,8 +42,8 @@
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_RX_PIN 32
#define UART_TX_PIN 33
#define UART_RX_PIN 22
#define UART_TX_PIN 20
// SPI for USB host shield
#define MAX3421_SCK_PIN _PINNUM(1, 15)

3
hw/bsp/nrf/boards/pca10095/board.mk
View File

@ -2,6 +2,9 @@ CPU_CORE = cortex-m33
MCU_VARIANT = nrf5340_application
CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
# enable max3421 host driver for this board
MAX3421_HOST = 1
LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c

1
hw/bsp/nrf/family.c
View File

@ -76,6 +76,7 @@ enum {
#define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
#define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
#define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
#define GPIOTE_IRQn GPIOTE1_IRQn
#else
#define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
#define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk

2
src/class/msc/msc_device.c
View File

@ -203,7 +203,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
//--------------------------------------------------------------------+
// Debug
//--------------------------------------------------------------------+
#if CFG_TUSB_DEBUG >= 2
#if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL
TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
{

6
src/class/video/video.h
View File

@ -368,6 +368,8 @@ typedef struct TU_ATTR_PACKED {
uint8_t bCopyProtect;
} tusb_desc_video_format_uncompressed_t;
TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is not correct");
// Uncompressed payload specs: 3.1.2 frame descriptor
#define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
struct TU_ATTR_PACKED { \
@ -381,7 +383,7 @@ typedef struct TU_ATTR_PACKED {
uint32_t dwMinBitRate; \
uint32_t dwMaxBitRate; \
uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
uint32_t dwDefaultFrameInterval; \
uint32_t dwDefaultFrameInterval; /* 100ns unit */\
uint8_t bFrameIntervalType; \
uint32_t dwFrameInterval[_nint]; \
}
@ -413,6 +415,8 @@ typedef struct TU_ATTR_PACKED {
uint8_t bCopyProtect;
} tusb_desc_video_format_mjpeg_t;
TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_mjpeg_t) == 11, "size is not correct");
// MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;

1
src/class/video/video_device.c
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@ -559,6 +559,7 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
if (num_intervals) {
interval = 0;
interval_ms = 0;
} else {
interval = frm->uncompressed.dwFrameInterval[2];
interval_ms = interval / 10000;

3
src/common/tusb_debug.h
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@ -60,6 +60,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
tu_printf("\r\n");
}
// Log with Level
@ -76,7 +77,7 @@ static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
#define TU_LOG1_MEM tu_print_mem
#define TU_LOG1_BUF(_x, _n) tu_print_buf((uint8_t const*)(_x), _n)
#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
#define TU_LOG1_HEX(_x) tu_printf(#_x " = 0x%lX\r\n", (unsigned long) (_x) )
// Log Level 2: Warn
#if CFG_TUSB_DEBUG >= 2

1
src/common/tusb_fifo.c
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@ -224,6 +224,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
}
break;
default: break;
}
}

1
src/device/usbd.c
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@ -500,7 +500,6 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
case DCD_EVENT_SETUP_RECEIVED:
TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
TU_LOG_USBD("\r\n");
// Mark as connected after receiving 1st setup packet.
// But it is easier to set it every time instead of wasting time to check then set

22
src/host/usbh.c
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@ -343,12 +343,12 @@ bool tuh_init(uint8_t controller_id) {
if ( tuh_inited() ) return true;
TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t));
TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t));
TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer));
TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t));
TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t));
TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t));
TU_LOG_INT_USBH(sizeof(usbh_device_t));
TU_LOG_INT_USBH(sizeof(hcd_event_t));
TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
TU_LOG_INT_USBH(sizeof(tuh_xfer_t));
TU_LOG_INT_USBH(sizeof(tu_fifo_t));
TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
// Event queue
_usbh_q = osal_queue_create( &_usbh_qdef );
@ -588,8 +588,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
(xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
tu_str_std_request[xfer->setup->bRequest] : "Class Request");
TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
TU_LOG_USBH("\r\n");
TU_LOG_BUF_USBH(xfer->setup, 8);
if (xfer->complete_cb) {
TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
@ -660,9 +659,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
tusb_control_request_t const * request = &_ctrl_xfer.request;
if (XFER_RESULT_SUCCESS != result) {
TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
TU_LOG1_BUF(request, 8);
TU_LOG1("\r\n");
TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
TU_LOG_BUF_USBH(request, 8);
// terminate transfer if any stage failed
_xfer_complete(dev_addr, result);
@ -680,7 +678,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
case CONTROL_STAGE_DATA:
if (request->wLength) {
TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2);
}
_ctrl_xfer.actual_len = (uint16_t) xferred_bytes;

6
src/host/usbh_pvt.h
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@ -35,7 +35,11 @@
extern "C" {
#endif
#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
#define TU_LOG_MEM_USBH(...) TU_LOG_MEM(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
#define TU_LOG_BUF_USBH(...) TU_LOG_BUF(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
#define TU_LOG_INT_USBH(...) TU_LOG_INT(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
#define TU_LOG_HEX_USBH(...) TU_LOG_HEX(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
enum {
USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)

8
src/portable/nordic/nrf5x/dcd_nrf5x.c
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@ -653,7 +653,11 @@ void dcd_int_handler(uint8_t rhport)
if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
{
iso_enabled = true;
xact_out_dma(EP_ISO_NUM);
// Transfer from endpoint to RAM only if data is not corrupted
if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 ||
(NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_ISOOUTCRC_Msk) == 0) {
xact_out_dma(EP_ISO_NUM);
}
}
// ISOIN: Notify client that data was transferred
@ -683,7 +687,7 @@ void dcd_int_handler(uint8_t rhport)
{
TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk };
enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk };
uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt

2
src/portable/ohci/ohci.h
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@ -83,7 +83,7 @@ typedef struct TU_ATTR_ALIGNED(16)
volatile uint32_t condition_code : 4;
// Word 1
volatile uint8_t* current_buffer_pointer;
uint8_t* volatile current_buffer_pointer;
// Word 2 : next TD
volatile uint32_t next;