Merge pull request #1 from hathach/tannewt-rpi

pi cm4 enumerated as full speed device

examples/device/cdc_msc/src/tusb_config.h

@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
+       CFG_TUSB_MCU == OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED

src/common/tusb_common.h

@@ -337,8 +337,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
-#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) )
+#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2

src/portable/broadcom/synopsys/dcd_synopsys.c

@@ -110,6 +110,8 @@
 
 #include "device/dcd.h"
 
+TU_VERIFY_STATIC(sizeof(USB_OTG_GlobalTypeDef) == 0x140, "size is incorrect");
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -340,7 +342,10 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
   dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
 }
 
-#if defined(USB_HS_PHYC)
+#if 0
+// From CM4IO xtal to usb hub, may not be correct
+#define HSE_VALUE 24000000
+
 static bool USB_HS_PHYCInit(void)
 {
   USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
@@ -435,6 +440,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /* Controller API
  *------------------------------------------------------------------*/
 
+TU_ATTR_UNUSED
 static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) {
   while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {}
 
@@ -456,6 +462,46 @@ void dcd_init (uint8_t rhport)
 
   USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
 
+#if 1
+  // No VBUS sense
+  usb_otg->GCCFG &= ~(1UL << 21); // USB_OTG_GCCFG_VBDEN
+
+  // B-peripheral session valid override enable
+  usb_otg->GOTGCTL |= (1UL << 6); // USB_OTG_GOTGCTL_BVALOEN
+  usb_otg->GOTGCTL |= (1UL << 7); // USB_OTG_GOTGCTL_BVALOVAL
+
+  // Force device mode
+  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
+  usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+  // deactivate internal PHY
+  usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
+
+  // Init The UTMI Interface
+  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+  // Select default internal VBUS Indicator and Drive for ULPI
+  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+
+  // Select UTMI Interface
+  usb_otg->GUSBCFG &= ~(1UL << 4); // USB_OTG_GUSBCFG_ULPI_UTMI_SEL
+  usb_otg->GCCFG |= (1UL << 32);   // USB_OTG_GCCFG_PHYHSEN
+
+  // Enables control of a High Speed USB PHY
+  //USB_HS_PHYCInit();
+
+  // Reset core after selecting PHY
+  // Wait AHB IDLE, reset then wait until it is cleared
+//  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
+//  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+//  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
+
+  reset_core(usb_otg);
+
+  // Restart PHY clock
+  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
+
+#else
 
   // ReadBackReg(&Core->Usb);
   // Core->Usb.UlpiDriveExternalVbus = 0;
@@ -470,7 +516,7 @@ void dcd_init (uint8_t rhport)
   //   LOG_DEBUG("HCD: Interface: UTMI+.\n");
   //   Core->Usb.PhyInterface = false;
 
-  //   HcdReset();  
+  //   HcdReset();
   TU_LOG2("init phy\r\n");
   usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode
   usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface
@@ -486,12 +532,14 @@ void dcd_init (uint8_t rhport)
   // Core->Ahb.DmaRemainderMode = Incremental;
   usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode
   usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
-  
+
   //   LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n");
   //   Core->Usb.HnpCapable = true;
   //   Core->Usb.SrpCapable = true;
   usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP;
 
+#endif
+
   // Clear all interrupts
   usb_otg->GINTSTS |= usb_otg->GINTSTS;
 
@@ -506,12 +554,9 @@ void dcd_init (uint8_t rhport)
   // (non zero-length packet), send STALL back and discard.
   dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
 
-  #if TUD_OPT_HIGH_SPEED
   set_speed(rhport, TUSB_SPEED_HIGH);
-  #else
-  set_speed(rhport, TUSB_SPEED_FULL);
-  #endif
 
+  // TODO internal phy (full speed)
   usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
 
   usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |

src/portable/broadcom/synopsys/synopsys_common.h

@@ -60,12 +60,23 @@ typedef struct
   __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
   uint32_t Reserved30[2];             /*!< Reserved 030h*/
   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
-  __IO uint32_t CID;                  /*!< User ID Register                           Address offset: 03Ch */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved40[48];           /*!< Reserved 040h-0FFh */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
 } USB_OTG_GlobalTypeDef;
 
+
+
 /** 
   * @brief __device_Registers
   */