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https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
Trying to get USB init
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98ab8117d6
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@ -27,14 +27,17 @@
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#include "bsp/board.h"
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#include "board.h"
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#include "broadcom/interrupts.h"
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#include "broadcom/io.h"
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#include "broadcom/mmu.h"
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#include "broadcom/vcmailbox.h"
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uint32_t SystemCoreClock = 700 * 1000 * 1000;
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void OTG_FS_IRQHandler(void)
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void USB_IRQHandler(void)
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{
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tud_int_handler(0);
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}
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@ -54,6 +57,9 @@ void print(const char* str) {
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void board_init(void)
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{
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gpio_initOutputPinWithPullNone(18);
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gpio_initOutputPinWithPullNone(19);
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gpio_initOutputPinWithPullNone(20);
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gpio_initOutputPinWithPullNone(21);
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gpio_setPinOutputBool(18, true);
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gpio_initOutputPinWithPullNone(42);
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setup_mmu_flat_map();
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@ -72,11 +78,17 @@ void board_init(void)
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}
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gpio_setPinOutputBool(42, true);
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gpio_setPinOutputBool(18, true);
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gpio_setPinOutputBool(19, true);
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gpio_setPinOutputBool(20, true);
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gpio_setPinOutputBool(21, true);
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for (size_t j = 0; j < 1000000; j++) {
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__asm__("nop");
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}
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gpio_setPinOutputBool(42, false);
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gpio_setPinOutputBool(18, false);
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gpio_setPinOutputBool(19, false);
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gpio_setPinOutputBool(20, false);
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gpio_setPinOutputBool(21, false);
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}
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// uart_writeText("hello from io\n");
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// gpio_setPinOutputBool(24, true);
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@ -98,11 +110,18 @@ void board_init(void)
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// }
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// while (1) uart_update();
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printf("hello %d\r\n", 21);
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// Turn on USB peripheral.
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print("Turning on USB power\r\n");
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vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
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print("USB power on\r\n");
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BP_SetPriority(USB_IRQn, 0x00);
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BP_ClearPendingIRQ(USB_IRQn);
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BP_EnableIRQ(USB_IRQn);
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BP_EnableIRQs();
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}
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void board_led_write(bool state)
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@ -125,10 +144,12 @@ int board_uart_write(void const * buf, int len)
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{
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for (int i = 0; i < len; i++) {
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const char* cbuf = buf;
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while (!UART1->STAT_b.TX_READY) {}
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if (cbuf[i] == '\n') {
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uart_writeByteBlockingActual('\r');
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UART1->IO = '\r';
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while (!UART1->STAT_b.TX_READY) {}
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}
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uart_writeByteBlockingActual(cbuf[i]);
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UART1->IO = cbuf[i];
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}
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return len;
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}
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@ -18,6 +18,7 @@ CFLAGS += \
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SRC_C += \
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src/portable/broadcom/synopsys/dcd_synopsys.c \
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$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
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$(MCU_DIR)/broadcom/interrupts.c \
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$(MCU_DIR)/broadcom/io.c \
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$(MCU_DIR)/broadcom/mmu.c \
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@ -1 +1 @@
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Subproject commit c24e8f6898d7cf8e2884eb70dbabd97480526450
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Subproject commit e5343acdad77b8cf4a8d09b732a11ecef17d148a
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@ -434,60 +434,63 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) {
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while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {}
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TU_LOG(2, " resetting\r\n");
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usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
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TU_LOG(2, " waiting\r\n");
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while ((usb_otg->GRSTCTL & (USB_OTG_GRSTCTL_AHBIDL | USB_OTG_GRSTCTL_CSRST)) != USB_OTG_GRSTCTL_AHBIDL) {}
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TU_LOG(2, " reset done\r\n");
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}
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void dcd_init (uint8_t rhport)
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{
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printf("test done\r\n");
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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TU_LOG(2, " dcd_init");
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TU_LOG(2, " dcd_init\r\n");
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TU_LOG2("Test 123\r\n");
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USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
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// No HNP/SRP (no OTG support), program timeout later.
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if ( rhport == 1 )
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{
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// On selected MCUs HS port1 can be used with external PHY via ULPI interface
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#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
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// deactivate internal PHY
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usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
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// Init The UTMI Interface
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
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// ReadBackReg(&Core->Usb);
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// Core->Usb.UlpiDriveExternalVbus = 0;
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// Core->Usb.TsDlinePulseEnable = 0;
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// WriteThroughReg(&Core->Usb);
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// Select default internal VBUS Indicator and Drive for ULPI
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
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#else
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usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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#endif
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// This sequence is modeled after: https://github.com/Chadderz121/csud/blob/e13b9355d043a9cdd384b335060f1bc0416df61e/source/hcd/dwc/designware20.c#L689
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIEVBUSD);
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reset_core(usb_otg);
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#if defined(USB_HS_PHYC)
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// Highspeed with embedded UTMI PHYC
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// Core->Usb.ModeSelect = UTMI;
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// LOG_DEBUG("HCD: Interface: UTMI+.\n");
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// Core->Usb.PhyInterface = false;
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// Select UTMI Interface
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usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
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usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
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// HcdReset();
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TU_LOG2("init phy\r\n");
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usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode
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usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface
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reset_core(usb_otg);
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// Enables control of a High Speed USB PHY
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USB_HS_PHYCInit();
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#endif
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} else
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{
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// Enable internal PHY
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usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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}
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// LOG_DEBUG("HCD: ULPI FSLS configuration: disabled.\n");
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// Core->Usb.UlpiFsls = false;
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// Core->Usb.ulpi_clk_sus_m = false;
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_ULPICSM);
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// Reset core after selecting PHY
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// Wait AHB IDLE, reset then wait until it is cleared
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while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
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TU_LOG(2, " resetting");
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usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
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TU_LOG(2, " waiting");
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while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
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TU_LOG(2, " reset done");
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// Restart PHY clock
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*((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
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// LOG_DEBUG("HCD: DMA configuration: enabled.\n");
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// Core->Ahb.DmaEnable = true;
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// Core->Ahb.DmaRemainderMode = Incremental;
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usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode
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usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
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// LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n");
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// Core->Usb.HnpCapable = true;
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// Core->Usb.SrpCapable = true;
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usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP;
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// Clear all interrupts
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usb_otg->GINTSTS |= usb_otg->GINTSTS;
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@ -509,8 +512,7 @@ void dcd_init (uint8_t rhport)
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set_speed(rhport, TUSB_SPEED_FULL);
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#endif
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// Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
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if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
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USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM |
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