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tusb_verify: add riscv assert support

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This simply executes an "ebreak" instruction.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-10-14 11:58:17 +08:00
parent ef07427e06
commit 359189ea2d
1 changed files with 4 additions and 0 deletions
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4
src/common/tusb_verify.h
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@ -89,9 +89,13 @@
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
} while(0) } while(0)
#else
#if defined(__riscv)
#define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
#else #else
#define TU_BREAKPOINT() #define TU_BREAKPOINT()
#endif #endif
#endif
/*------------------------------------------------------------------*/ /*------------------------------------------------------------------*/
/* Macro Generator /* Macro Generator