From 359189ea2d791ab895dc29cbfa4e3eba14caf65f Mon Sep 17 00:00:00 2001
From: Sean Cross <sean@xobs.io>
Date: Mon, 14 Oct 2019 11:58:17 +0800
Subject: [PATCH] tusb_verify: add riscv assert support

This simply executes an "ebreak" instruction.

Signed-off-by: Sean Cross <sean@xobs.io>
---
 src/common/tusb_verify.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index e59481352..2b63ab946 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -89,9 +89,13 @@
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
     if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */            \
   } while(0)
+#else
+#if defined(__riscv)
+  #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
 #else
   #define TU_BREAKPOINT()
 #endif
+#endif
 
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