tusb_verify: add riscv assert support

This simply executes an "ebreak" instruction.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-10-14 11:58:17 +08:00
parent ef07427e06
commit 359189ea2d

View File

@ -89,9 +89,13 @@
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
} while(0)
#else
#if defined(__riscv)
#define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
#else
#define TU_BREAKPOINT()
#endif
#endif
/*------------------------------------------------------------------*/
/* Macro Generator