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Merge branch 'master' into port-samg55

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hathach 2020-02-07 16:50:07 +07:00
commit 087e3c7f56
4 changed files with 153 additions and 107 deletions
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1
examples/rules.mk
View File

@ -120,6 +120,7 @@ endif
# Flash using jlink # Flash using jlink
flash-jlink: $(BUILD)/$(BOARD)-firmware.hex flash-jlink: $(BUILD)/$(BOARD)-firmware.hex
@echo halt > $(BUILD)/$(BOARD).jlink @echo halt > $(BUILD)/$(BOARD).jlink
@echo r > $(BUILD)/$(BOARD).jlink
@echo loadfile $^ >> $(BUILD)/$(BOARD).jlink @echo loadfile $^ >> $(BUILD)/$(BOARD).jlink
@echo r >> $(BUILD)/$(BOARD).jlink @echo r >> $(BUILD)/$(BOARD).jlink
@echo go >> $(BUILD)/$(BOARD).jlink @echo go >> $(BUILD)/$(BOARD).jlink

2
src/class/midi/midi_device.c
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@ -355,7 +355,7 @@ bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32
// nothing to do with in and notif endpoint // nothing to do with in and notif endpoint
return TUSB_ERROR_NONE; return true;
} }
#endif #endif

61
src/portable/nuvoton/nuc121/dcd_nuc121.c
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@ -148,6 +148,37 @@ static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
ep->MXPLD = bytes_now; ep->MXPLD = bytes_now;
} }
/* called by dcd_init() as well as by the ISR during a USB bus reset */
static void bus_reset(void)
{
USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
{
USBD->EP[ep_index].CFG = 0;
USBD->EP[ep_index].CFGP = 0;
}
/* allocate the default EP0 endpoints */
USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
/* USB RAM beyond what we've allocated above is available to the user */
bufseg_addr = PERIPH_EP2_BUF_BASE;
/* Reset USB device address */
USBD->FADDR = 0;
/* reset EP0_IN flag */
active_ep0_xfer = false;
}
/* centralized location for USBD interrupt enable bit mask */ /* centralized location for USBD interrupt enable bit mask */
static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk; static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
@ -167,25 +198,7 @@ void dcd_init(uint8_t rhport)
usb_detach(); usb_detach();
USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE; bus_reset();
for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
{
USBD->EP[ep_index].CFGP &= ~USBD_CFG_STATE_Msk;
}
/* allocate the default EP0 endpoints */
USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
/* USB RAM beyond what we've allocated above is available to the user */
bufseg_addr = PERIPH_EP2_BUF_BASE;
usb_attach(); usb_attach();
@ -329,15 +342,7 @@ void USBD_IRQHandler(void)
/* USB bus reset */ /* USB bus reset */
USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
/* Reset all endpoints to DATA0 */ bus_reset();
for(enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
USBD->EP[ep_index].CFG &= ~USBD_CFG_DSQSYNC_Msk;
/* Reset USB device address */
USBD->FADDR = 0;
/* reset EP0_IN flag */
active_ep0_xfer = false;
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
} }

196
src/portable/nxp/transdimension/dcd_transdimension.c
View File

@ -1,4 +1,4 @@
/* /*
* The MIT License (MIT) * The MIT License (MIT)
* *
* Copyright (c) 2019 Ha Thach (tinyusb.org) * Copyright (c) 2019 Ha Thach (tinyusb.org)
@ -38,22 +38,15 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
#include "fsl_device_registers.h" #include "fsl_device_registers.h"
// RT1010 and RT1020 only has 1 USB controller
#if FSL_FEATURE_SOC_USBHS_COUNT == 1
#define DCD_REGS_BASE { (dcd_registers_t*) USB_BASE }
IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn };
// RT1050, RT1060 has 2 USB controllers
#else #else
#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE } // LPCOpen for 18xx & 43xx
IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn }; #include "chip.h"
#endif #endif
#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
#else #else
#include "chip.h" #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
#define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
IRQn_Type DCD_IRQn[] = { USB0_IRQn, USB1_IRQn };
#endif #endif
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
@ -130,48 +123,48 @@ enum {
typedef struct typedef struct
{ {
//------------- ID + HW Parameter Registers-------------// //------------- ID + HW Parameter Registers-------------//
__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX __I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
//------------- Capability Registers-------------// //------------- Capability Registers-------------//
__I uint8_t CAPLENGTH; ///< Capability Registers Length __I uint8_t CAPLENGTH; ///< Capability Registers Length
__I uint8_t TU_RESERVED[1]; __I uint8_t TU_RESERVED[1];
__I uint16_t HCIVERSION; ///< Host Controller Interface Version __I uint16_t HCIVERSION; ///< Host Controller Interface Version
__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters __I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters __I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
__I uint32_t TU_RESERVED[5]; __I uint32_t TU_RESERVED[5];
__I uint16_t DCIVERSION; ///< Device Controller Interface Version __I uint16_t DCIVERSION; ///< Device Controller Interface Version
__I uint8_t TU_RESERVED[2]; __I uint8_t TU_RESERVED[2];
__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters __I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
__I uint32_t TU_RESERVED[6]; __I uint32_t TU_RESERVED[6];
//------------- Operational Registers -------------// //------------- Operational Registers -------------//
__IO uint32_t USBCMD; ///< USB Command Register __IO uint32_t USBCMD; ///< USB Command Register
__IO uint32_t USBSTS; ///< USB Status Register __IO uint32_t USBSTS; ///< USB Status Register
__IO uint32_t USBINTR; ///< Interrupt Enable Register __IO uint32_t USBINTR; ///< Interrupt Enable Register
__IO uint32_t FRINDEX; ///< USB Frame Index __IO uint32_t FRINDEX; ///< USB Frame Index
__I uint32_t TU_RESERVED; __I uint32_t TU_RESERVED;
__IO uint32_t DEVICEADDR; ///< Device Address __IO uint32_t DEVICEADDR; ///< Device Address
__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address __IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
__I uint32_t TU_RESERVED; __I uint32_t TU_RESERVED;
__IO uint32_t BURSTSIZE; ///< Programmable Burst Size __IO uint32_t BURSTSIZE; ///< Programmable Burst Size
__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning __IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
uint32_t TU_RESERVED[4]; uint32_t TU_RESERVED[4];
__IO uint32_t ENDPTNAK; ///< Endpoint NAK __IO uint32_t ENDPTNAK; ///< Endpoint NAK
__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable __IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
__I uint32_t TU_RESERVED; __I uint32_t TU_RESERVED;
__IO uint32_t PORTSC1; ///< Port Status & Control __IO uint32_t PORTSC1; ///< Port Status & Control
__I uint32_t TU_RESERVED[7]; __I uint32_t TU_RESERVED[7];
__IO uint32_t OTGSC; ///< On-The-Go Status & control __IO uint32_t OTGSC; ///< On-The-Go Status & control
__IO uint32_t USBMODE; ///< USB Device Mode __IO uint32_t USBMODE; ///< USB Device Mode
__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status __IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
__IO uint32_t ENDPTPRIME; ///< Endpoint Prime __IO uint32_t ENDPTPRIME; ///< Endpoint Prime
__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush __IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
__I uint32_t ENDPTSTAT; ///< Endpoint Status __I uint32_t ENDPTSTAT; ///< Endpoint Status
__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete __IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7 __IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
} dcd_registers_t; } dcd_registers_t;
@ -218,20 +211,20 @@ typedef struct
uint32_t : 0 ; uint32_t : 0 ;
// Word 1: Current qTD Pointer // Word 1: Current qTD Pointer
volatile uint32_t qtd_addr; volatile uint32_t qtd_addr;
// Word 2-9: Transfer Overlay // Word 2-9: Transfer Overlay
volatile dcd_qtd_t qtd_overlay; volatile dcd_qtd_t qtd_overlay;
// Word 10-11: Setup request (control OUT only) // Word 10-11: Setup request (control OUT only)
volatile tusb_control_request_t setup_request; volatile tusb_control_request_t setup_request;
//--------------------------------------------------------------------+
/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
/// thus there are 16 bytes padding free that we can make use of.
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
uint8_t reserved[16]; /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
} dcd_qhd_t; /// thus there are 16 bytes padding free that we can make use of.
//--------------------------------------------------------------------+
uint8_t reserved[16];
} dcd_qhd_t;
TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct"); TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
@ -239,17 +232,48 @@ TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
// Variables // Variables
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
#define QHD_MAX 12 typedef struct
{
dcd_registers_t* regs; // registers
const IRQn_Type irqnum; // IRQ number
const uint8_t ep_count; // Max bi-directional Endpoints
}dcd_controller_t;
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
// Each endpoint with direction (IN/OUT) occupies a queue head
// Therefore QHD_MAX is 2 x max endpoint count
#define QHD_MAX (8*2)
dcd_controller_t _dcd_controller[] =
{
// RT1010 and RT1020 only has 1 USB controller
#if FSL_FEATURE_SOC_USBHS_COUNT == 1
{ .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
#else
{ .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
{ .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
#endif
};
#else
#define QHD_MAX (6*2)
dcd_controller_t _dcd_controller[] =
{
{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
{ .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
};
#endif
#define QTD_NEXT_INVALID 0x01 #define QTD_NEXT_INVALID 0x01
typedef struct { typedef struct {
// Must be at 2K alignment // Must be at 2K alignment
dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64); dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd
}dcd_data_t; }dcd_data_t;
static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048); static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// CONTROLLER API // CONTROLLER API
@ -258,16 +282,14 @@ static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
/// follows LPC43xx User Manual 23.10.3 /// follows LPC43xx User Manual 23.10.3
static void bus_reset(uint8_t rhport) static void bus_reset(uint8_t rhport)
{ {
dcd_registers_t* dcd_reg = DCD_REGS[rhport]; dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
// The reset value for all endpoint types is the control endpoint. If one endpoint // The reset value for all endpoint types is the control endpoint. If one endpoint
// direction is enabled and the paired endpoint of opposite direction is disabled, then the // direction is enabled and the paired endpoint of opposite direction is disabled, then the
// endpoint type of the unused direction must bechanged from the control type to any other // endpoint type of the unused direction must be changed from the control type to any other
// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
// for the data PID tracking on the active endpoint. // for the data PID tracking on the active endpoint.
for( int i=1; i < _dcd_controller[rhport].ep_count; i++)
// USB0 has 5 but USB1 only has 3 non-control endpoints
for( int i=1; i < (rhport ? 6 : 4); i++)
{ {
dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18); dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
} }
@ -279,9 +301,9 @@ static void bus_reset(uint8_t rhport)
dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE;
while (dcd_reg->ENDPTPRIME); while (dcd_reg->ENDPTPRIME) {}
dcd_reg->ENDPTFLUSH = 0xFFFFFFFF; dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
while (dcd_reg->ENDPTFLUSH); while (dcd_reg->ENDPTFLUSH) {}
// read reset bit in portsc // read reset bit in portsc
@ -289,18 +311,18 @@ static void bus_reset(uint8_t rhport)
tu_memclr(&_dcd_data, sizeof(dcd_data_t)); tu_memclr(&_dcd_data, sizeof(dcd_data_t));
//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------// //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1; _dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE; _dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
_dcd_data.qhd[0].int_on_setup = 1; // OUT only _dcd_data.qhd[0].int_on_setup = 1; // OUT only
} }
void dcd_init(uint8_t rhport) void dcd_init(uint8_t rhport)
{ {
tu_memclr(&_dcd_data, sizeof(dcd_data_t)); tu_memclr(&_dcd_data, sizeof(dcd_data_t));
dcd_registers_t* const dcd_reg = DCD_REGS[rhport]; dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
// Reset controller // Reset controller
dcd_reg->USBCMD |= USBCMD_RESET; dcd_reg->USBCMD |= USBCMD_RESET;
@ -313,9 +335,11 @@ void dcd_init(uint8_t rhport)
// TODO Force fullspeed on non-highspeed port // TODO Force fullspeed on non-highspeed port
// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
dcd_reg->USBSTS = dcd_reg->USBSTS; dcd_reg->USBSTS = dcd_reg->USBSTS;
dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF; dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND /*| INTR_SOF*/;
dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0 dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
dcd_reg->USBCMD |= TU_BIT(0); // connect dcd_reg->USBCMD |= TU_BIT(0); // connect
@ -323,12 +347,12 @@ void dcd_init(uint8_t rhport)
void dcd_int_enable(uint8_t rhport) void dcd_int_enable(uint8_t rhport)
{ {
NVIC_EnableIRQ(DCD_IRQn[rhport]); NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
} }
void dcd_int_disable(uint8_t rhport) void dcd_int_disable(uint8_t rhport)
{ {
NVIC_DisableIRQ(DCD_IRQn[rhport]); NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
} }
void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
@ -336,7 +360,8 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
// Response with status first before changing device address // Response with status first before changing device address
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
DCD_REGS[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24); dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
} }
void dcd_set_config(uint8_t rhport, uint8_t config_num) void dcd_set_config(uint8_t rhport, uint8_t config_num)
@ -386,7 +411,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr);
DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
} }
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
@ -395,8 +421,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
uint8_t const dir = tu_edpt_dir(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr);
// data toggle also need to be reset // data toggle also need to be reset
DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 ); dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
DCD_REGS[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0)); dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
} }
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@ -408,8 +435,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
uint8_t const ep_idx = 2*epnum + dir; uint8_t const ep_idx = 2*epnum + dir;
// USB0 has 5, USB1 has 3 non-control endpoints // Must not exceed max endpoint number
TU_ASSERT( epnum <= (rhport ? 3 : 5) ); TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
//------------- Prepare Queue Head -------------// //------------- Prepare Queue Head -------------//
dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
@ -419,14 +446,18 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size; p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
// Enable EP Control // Enable EP Control
DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
return true; return true;
} }
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{ {
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr);
uint8_t const ep_idx = 2*epnum + dir; uint8_t const ep_idx = 2*epnum + dir;
@ -435,19 +466,25 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
{ {
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
while(DCD_REGS[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {} while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
} }
dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx]; dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
// address to 32-byte boundaries.
CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
//------------- Prepare qtd -------------// //------------- Prepare qtd -------------//
qtd_init(p_qtd, buffer, total_bytes); qtd_init(p_qtd, buffer, total_bytes);
p_qtd->int_on_complete = true; p_qtd->int_on_complete = true;
p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
// start transfer // start transfer
DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ; dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
return true; return true;
} }
@ -457,7 +494,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
void dcd_isr(uint8_t rhport) void dcd_isr(uint8_t rhport)
{ {
dcd_registers_t* const dcd_reg = DCD_REGS[rhport]; dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
uint32_t const int_enable = dcd_reg->USBINTR; uint32_t const int_enable = dcd_reg->USBINTR;
uint32_t const int_status = dcd_reg->USBSTS & int_enable; uint32_t const int_status = dcd_reg->USBSTS & int_enable;
@ -484,6 +521,9 @@ void dcd_isr(uint8_t rhport)
} }
} }
// Make sure we read the latest version of _dcd_data.
CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
// TODO disconnection does not generate interrupt !!!!!! // TODO disconnection does not generate interrupt !!!!!!
// if (int_status & INTR_PORT_CHANGE) // if (int_status & INTR_PORT_CHANGE)
// { // {