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add new ch32v203g6u board, sysfreq is defined in board.cmake/mk

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hathach 2024-06-21 16:08:37 +07:00
parent ac3ec59845
commit 02bea8982e
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GPG Key ID: 26FAB84F615C3C52
16 changed files with 107 additions and 46 deletions
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4
hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
View File

@ -1,5 +1,5 @@
CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
LDFLAGS += \
-Wl,--defsym=__flash_size=64K \
-Wl,--defsym=__ram_size=20K \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__RAM_SIZE=20K \

4
hw/bsp/ch32v10x/family.cmake
View File

@ -59,8 +59,8 @@ function(add_board_target BOARD_TARGET)
)
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
-Wl,--defsym=__flash_size=${LD_FLASH_SIZE}
-Wl,--defsym=__ram_size=${LD_RAM_SIZE}
-Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
-Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
-nostartfiles
--specs=nosys.specs --specs=nano.specs
)

7
hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk
View File

@ -1,7 +0,0 @@
MCU_VARIANT = D6
CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
LDFLAGS += \
-Wl,--defsym=__flash_size=64K \
-Wl,--defsym=__ram_size=20K \

1
hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake → hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
View File

@ -7,6 +7,7 @@ set(LD_RAM_SIZE 20K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSE=144000000
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

5
hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h → hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
View File

@ -9,6 +9,11 @@ extern "C" {
#define LED_PIN GPIO_Pin_15
#define LED_STATE_ON 0
#define UART_DEV USART1
#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
#define UART_TX_PIN GPIO_Pin_9
#define UART_RX_PIN GPIO_Pin_10
#ifdef __cplusplus
}
#endif

9
hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk Normal file
View File

@ -0,0 +1,9 @@
MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSE=144000000 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__RAM_SIZE=20K \

11
hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake Normal file
View File

@ -0,0 +1,11 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 32K)
set(LD_RAM_SIZE 10K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSI=144000000
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

21
hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h Normal file
View File

@ -0,0 +1,21 @@
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LED_PORT GPIOA
#define LED_PIN GPIO_Pin_0
#define LED_STATE_ON 1
#define UART_DEV USART2
#define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE)
#define UART_TX_PIN GPIO_Pin_2
#define UART_RX_PIN GPIO_Pin_3
#ifdef __cplusplus
}
#endif
#endif

9
hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk Normal file
View File

@ -0,0 +1,9 @@
MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSI=144000000 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=32K \
-Wl,--defsym=__RAM_SIZE=10K \

1
hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
View File

@ -5,6 +5,7 @@ set(LD_RAM_SIZE 20K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSE=144000000
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

6
hw/bsp/ch32v20x/boards/nanoch32v203/board.h
View File

@ -8,7 +8,11 @@ extern "C" {
#define LED_PORT GPIOA
#define LED_PIN GPIO_Pin_15
#define LED_STATE_ON 0
#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE)
#define UART_DEV USART1
#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
#define UART_TX_PIN GPIO_Pin_9
#define UART_RX_PIN GPIO_Pin_10
#ifdef __cplusplus
}

8
hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
View File

@ -1,7 +1,9 @@
MCU_VARIANT = D6
CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSE=144000000 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
LDFLAGS += \
-Wl,--defsym=__flash_size=64K \
-Wl,--defsym=__ram_size=20K \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__RAM_SIZE=20K \

45
hw/bsp/ch32v20x/family.c
View File

@ -96,28 +96,17 @@ void board_init(void) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
uint8_t usb_div;
switch (SystemCoreClock) {
case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break;
case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break;
default: TU_ASSERT(0,); break;
}
RCC_USBCLKConfig(usb_div);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); // FSDEV
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS
GPIO_InitTypeDef GPIO_InitStructure = {
.GPIO_Pin = LED_PIN,
.GPIO_Mode = GPIO_Mode_Out_OD,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Speed = GPIO_Speed_10MHz,
};
GPIO_Init(LED_PORT, &GPIO_InitStructure);
// UART TX is PA9
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
#ifdef UART_DEV
UART_CLOCK_EN();
GPIO_InitTypeDef usart_init = {
.GPIO_Pin = GPIO_Pin_9,
.GPIO_Pin = UART_TX_PIN,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Mode = GPIO_Mode_AF_PP,
};
@ -131,11 +120,23 @@ void board_init(void) {
.USART_Mode = USART_Mode_Tx,
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
};
USART_Init(USART1, &usart);
USART_Cmd(USART1, ENABLE);
USART_Init(UART_DEV, &usart);
USART_Cmd(UART_DEV, ENABLE);
#endif
// USB init
uint8_t usb_div;
switch (SystemCoreClock) {
case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break;
case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break;
default: TU_ASSERT(0,); break;
}
RCC_USBCLKConfig(usb_div);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); // FSDEV
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS
__enable_irq();
board_delay(2);
}
void board_led_write(bool state) {
@ -153,11 +154,15 @@ int board_uart_read(uint8_t *buf, int len) {
}
int board_uart_write(void const *buf, int len) {
#ifdef UART_DEV
const char *bufc = (const char *) buf;
for (int i = 0; i < len; i++) {
while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, *bufc++);
while (USART_GetFlagStatus(UART_DEV, USART_FLAG_TC) == RESET);
USART_SendData(UART_DEV, *bufc++);
}
#else
(void) buf; (void) len;
#endif
return len;
}

9
hw/bsp/ch32v20x/family.cmake
View File

@ -41,6 +41,7 @@ function(add_board_target BOARD_TARGET)
add_library(${BOARD_TARGET} STATIC
${SDK_SRC_DIR}/Core/core_riscv.c
${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_flash.c
${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
@ -76,14 +77,14 @@ function(add_board_target BOARD_TARGET)
-mcmodel=medany
)
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
-Wl,--defsym=__flash_size=${LD_FLASH_SIZE}
-Wl,--defsym=__ram_size=${LD_RAM_SIZE}
-nostartfiles
--specs=nosys.specs --specs=nano.specs
-Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
-Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
"LINKER:--script=${LD_FILE_GNU}"
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
message(FATAL_ERROR "Clang is not supported for MSP432E4")
message(FATAL_ERROR "Clang is not supported for CH32v")
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--config=${LD_FILE_IAR}"

11
hw/bsp/ch32v20x/linker/ch32v20x.ld
View File

@ -1,17 +1,16 @@
/* Define default values if not already defined */
__FLASH_SIZE = DEFINED(__flash_size) ? __flash_size : 64K;
__RAM_SIZE = DEFINED(__ram_size) ? __ram_size : 20K;
__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K;
__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K;
__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048;
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __FLASH_SIZE
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __RAM_SIZE
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size
}
ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
SECTIONS

2
hw/bsp/ch32v20x/system_ch32v20x.c
View File

@ -24,7 +24,7 @@
//#define SYSCLK_FREQ_72MHz_HSE 72000000
// #define SYSCLK_FREQ_96MHz_HSE 96000000
//#define SYSCLK_FREQ_120MHz_HSE 120000000
#define SYSCLK_FREQ_144MHz_HSE 144000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
//#define SYSCLK_FREQ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHz_HSI 48000000
//#define SYSCLK_FREQ_56MHz_HSI 56000000