From 02bea8982e36b6a60fd424e1040c7e37c95e0628 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 21 Jun 2024 16:08:37 +0700 Subject: [PATCH] add new ch32v203g6u board, sysfreq is defined in board.cmake/mk --- .../ch32v10x/boards/ch32v103r_r1_1v0/board.mk | 4 +- hw/bsp/ch32v10x/family.cmake | 4 +- .../ch32v20x/boards/ch32v203_r0_1v0/board.mk | 7 --- .../board.cmake | 1 + .../board.h | 5 +++ .../ch32v20x/boards/ch32v203c_r0_1v0/board.mk | 9 ++++ .../boards/ch32v203g_r0_1v0/board.cmake | 11 +++++ .../ch32v20x/boards/ch32v203g_r0_1v0/board.h | 21 +++++++++ .../ch32v20x/boards/ch32v203g_r0_1v0/board.mk | 9 ++++ .../ch32v20x/boards/nanoch32v203/board.cmake | 1 + hw/bsp/ch32v20x/boards/nanoch32v203/board.h | 6 ++- hw/bsp/ch32v20x/boards/nanoch32v203/board.mk | 8 ++-- hw/bsp/ch32v20x/family.c | 45 ++++++++++--------- hw/bsp/ch32v20x/family.cmake | 9 ++-- hw/bsp/ch32v20x/linker/ch32v20x.ld | 11 +++-- hw/bsp/ch32v20x/system_ch32v20x.c | 2 +- 16 files changed, 107 insertions(+), 46 deletions(-) delete mode 100644 hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk rename hw/bsp/ch32v20x/boards/{ch32v203_r0_1v0 => ch32v203c_r0_1v0}/board.cmake (88%) rename hw/bsp/ch32v20x/boards/{ch32v203_r0_1v0 => ch32v203c_r0_1v0}/board.h (52%) create mode 100644 hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk create mode 100644 hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake create mode 100644 hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h create mode 100644 hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk index 70e65333c..e594f42a7 100644 --- a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk +++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk @@ -1,5 +1,5 @@ CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY LDFLAGS += \ - -Wl,--defsym=__flash_size=64K \ - -Wl,--defsym=__ram_size=20K \ + -Wl,--defsym=__FLASH_SIZE=64K \ + -Wl,--defsym=__RAM_SIZE=20K \ diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake index b0d8241d3..c0af0ef44 100644 --- a/hw/bsp/ch32v10x/family.cmake +++ b/hw/bsp/ch32v10x/family.cmake @@ -59,8 +59,8 @@ function(add_board_target BOARD_TARGET) ) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -Wl,--defsym=__flash_size=${LD_FLASH_SIZE} - -Wl,--defsym=__ram_size=${LD_RAM_SIZE} + -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE} + -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE} -nostartfiles --specs=nosys.specs --specs=nano.specs ) diff --git a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk deleted file mode 100644 index 7d7462312..000000000 --- a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk +++ /dev/null @@ -1,7 +0,0 @@ -MCU_VARIANT = D6 - -CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY - -LDFLAGS += \ - -Wl,--defsym=__flash_size=64K \ - -Wl,--defsym=__ram_size=20K \ diff --git a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake similarity index 88% rename from hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake rename to hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake index 31b6b716e..3dd87d3de 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake +++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake @@ -7,6 +7,7 @@ set(LD_RAM_SIZE 20K) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC + SYSCLK_FREQ_144MHz_HSE=144000000 CFG_EXAMPLE_MSC_DUAL_READONLY ) endfunction() diff --git a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h similarity index 52% rename from hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h rename to hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h index 3ed2aef04..64eaf931e 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h @@ -9,6 +9,11 @@ extern "C" { #define LED_PIN GPIO_Pin_15 #define LED_STATE_ON 0 +#define UART_DEV USART1 +#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) +#define UART_TX_PIN GPIO_Pin_9 +#define UART_RX_PIN GPIO_Pin_10 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk new file mode 100644 index 000000000..7d5894629 --- /dev/null +++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk @@ -0,0 +1,9 @@ +MCU_VARIANT = D6 + +CFLAGS += \ + -DSYSCLK_FREQ_144MHz_HSE=144000000 \ + -DCFG_EXAMPLE_MSC_DUAL_READONLY \ + +LDFLAGS += \ + -Wl,--defsym=__FLASH_SIZE=64K \ + -Wl,--defsym=__RAM_SIZE=20K \ diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake new file mode 100644 index 000000000..6e5305212 --- /dev/null +++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT D6) + +set(LD_FLASH_SIZE 32K) +set(LD_RAM_SIZE 10K) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + SYSCLK_FREQ_144MHz_HSI=144000000 + CFG_EXAMPLE_MSC_DUAL_READONLY + ) +endfunction() diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h new file mode 100644 index 000000000..d6c3a64c8 --- /dev/null +++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h @@ -0,0 +1,21 @@ +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED_PORT GPIOA +#define LED_PIN GPIO_Pin_0 +#define LED_STATE_ON 1 + +#define UART_DEV USART2 +#define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE) +#define UART_TX_PIN GPIO_Pin_2 +#define UART_RX_PIN GPIO_Pin_3 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk new file mode 100644 index 000000000..e5e4d63ba --- /dev/null +++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk @@ -0,0 +1,9 @@ +MCU_VARIANT = D6 + +CFLAGS += \ + -DSYSCLK_FREQ_144MHz_HSI=144000000 \ + -DCFG_EXAMPLE_MSC_DUAL_READONLY \ + +LDFLAGS += \ + -Wl,--defsym=__FLASH_SIZE=32K \ + -Wl,--defsym=__RAM_SIZE=10K \ diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake index 8d3e0326e..f8dc862a7 100644 --- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake +++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake @@ -5,6 +5,7 @@ set(LD_RAM_SIZE 20K) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC + SYSCLK_FREQ_144MHz_HSE=144000000 CFG_EXAMPLE_MSC_DUAL_READONLY ) endfunction() diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h index c8d28d90f..64eaf931e 100644 --- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h +++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h @@ -8,7 +8,11 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_15 #define LED_STATE_ON 0 -#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) + +#define UART_DEV USART1 +#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) +#define UART_TX_PIN GPIO_Pin_9 +#define UART_RX_PIN GPIO_Pin_10 #ifdef __cplusplus } diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk index 7d7462312..7d5894629 100644 --- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk +++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk @@ -1,7 +1,9 @@ MCU_VARIANT = D6 -CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY +CFLAGS += \ + -DSYSCLK_FREQ_144MHz_HSE=144000000 \ + -DCFG_EXAMPLE_MSC_DUAL_READONLY \ LDFLAGS += \ - -Wl,--defsym=__flash_size=64K \ - -Wl,--defsym=__ram_size=20K \ + -Wl,--defsym=__FLASH_SIZE=64K \ + -Wl,--defsym=__RAM_SIZE=20K \ diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 8575f5699..ea98a5e19 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -96,28 +96,17 @@ void board_init(void) { RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - uint8_t usb_div; - switch (SystemCoreClock) { - case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break; - case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break; - case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break; - default: TU_ASSERT(0,); break; - } - RCC_USBCLKConfig(usb_div); - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); // FSDEV - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS - GPIO_InitTypeDef GPIO_InitStructure = { .GPIO_Pin = LED_PIN, .GPIO_Mode = GPIO_Mode_Out_OD, - .GPIO_Speed = GPIO_Speed_50MHz, + .GPIO_Speed = GPIO_Speed_10MHz, }; GPIO_Init(LED_PORT, &GPIO_InitStructure); - // UART TX is PA9 - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); +#ifdef UART_DEV + UART_CLOCK_EN(); GPIO_InitTypeDef usart_init = { - .GPIO_Pin = GPIO_Pin_9, + .GPIO_Pin = UART_TX_PIN, .GPIO_Speed = GPIO_Speed_50MHz, .GPIO_Mode = GPIO_Mode_AF_PP, }; @@ -131,11 +120,23 @@ void board_init(void) { .USART_Mode = USART_Mode_Tx, .USART_HardwareFlowControl = USART_HardwareFlowControl_None, }; - USART_Init(USART1, &usart); - USART_Cmd(USART1, ENABLE); + USART_Init(UART_DEV, &usart); + USART_Cmd(UART_DEV, ENABLE); +#endif + + // USB init + uint8_t usb_div; + switch (SystemCoreClock) { + case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break; + case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break; + case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break; + default: TU_ASSERT(0,); break; + } + RCC_USBCLKConfig(usb_div); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); // FSDEV + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS __enable_irq(); - board_delay(2); } void board_led_write(bool state) { @@ -153,11 +154,15 @@ int board_uart_read(uint8_t *buf, int len) { } int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV const char *bufc = (const char *) buf; for (int i = 0; i < len; i++) { - while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); - USART_SendData(USART1, *bufc++); + while (USART_GetFlagStatus(UART_DEV, USART_FLAG_TC) == RESET); + USART_SendData(UART_DEV, *bufc++); } +#else + (void) buf; (void) len; +#endif return len; } diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake index 28fd13697..faa79ed66 100644 --- a/hw/bsp/ch32v20x/family.cmake +++ b/hw/bsp/ch32v20x/family.cmake @@ -41,6 +41,7 @@ function(add_board_target BOARD_TARGET) add_library(${BOARD_TARGET} STATIC ${SDK_SRC_DIR}/Core/core_riscv.c + ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_flash.c ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c @@ -76,14 +77,14 @@ function(add_board_target BOARD_TARGET) -mcmodel=medany ) target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -Wl,--defsym=__flash_size=${LD_FLASH_SIZE} - -Wl,--defsym=__ram_size=${LD_RAM_SIZE} -nostartfiles --specs=nosys.specs --specs=nano.specs + -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE} + -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE} + "LINKER:--script=${LD_FILE_GNU}" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - message(FATAL_ERROR "Clang is not supported for MSP432E4") + message(FATAL_ERROR "Clang is not supported for CH32v") elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" diff --git a/hw/bsp/ch32v20x/linker/ch32v20x.ld b/hw/bsp/ch32v20x/linker/ch32v20x.ld index cd5c8dc17..f84808b0d 100644 --- a/hw/bsp/ch32v20x/linker/ch32v20x.ld +++ b/hw/bsp/ch32v20x/linker/ch32v20x.ld @@ -1,17 +1,16 @@ /* Define default values if not already defined */ -__FLASH_SIZE = DEFINED(__flash_size) ? __flash_size : 64K; -__RAM_SIZE = DEFINED(__ram_size) ? __ram_size : 20K; +__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K; +__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K; +__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048; MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __FLASH_SIZE - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __RAM_SIZE + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size } ENTRY( _start ) -__stack_size = 2048; - PROVIDE( _stack_size = __stack_size ); SECTIONS diff --git a/hw/bsp/ch32v20x/system_ch32v20x.c b/hw/bsp/ch32v20x/system_ch32v20x.c index bdc0d498f..435feae1b 100644 --- a/hw/bsp/ch32v20x/system_ch32v20x.c +++ b/hw/bsp/ch32v20x/system_ch32v20x.c @@ -24,7 +24,7 @@ //#define SYSCLK_FREQ_72MHz_HSE 72000000 // #define SYSCLK_FREQ_96MHz_HSE 96000000 //#define SYSCLK_FREQ_120MHz_HSE 120000000 -#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 //#define SYSCLK_FREQ_HSI HSI_VALUE //#define SYSCLK_FREQ_48MHz_HSI 48000000 //#define SYSCLK_FREQ_56MHz_HSI 56000000