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Merge pull request #1171 from vlj/llvm-fix

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Fix Sonic CD music with LLVM backend
This commit is contained in:
Raul Tambre 2015-08-08 18:35:29 +03:00
commit fd5fbab115
4 changed files with 22 additions and 6 deletions
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1
rpcs3/Emu/Cell/PPUDisAsm.h
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@ -1,6 +1,7 @@
#pragma once #pragma once
#include "Emu/Cell/PPCDisAsm.h" #include "Emu/Cell/PPCDisAsm.h"
#include "Emu/Cell/PPUOpcodes.h"
class PPUDisAsm class PPUDisAsm
: public PPUOpcodes : public PPUOpcodes

14
rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
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@ -1,6 +1,7 @@
#include "stdafx.h" #include "stdafx.h"
#include "Utilities/Log.h" #include "Utilities/Log.h"
#include "Emu/System.h" #include "Emu/System.h"
#include "Emu/Cell/PPUDisAsm.h"
#include "Emu/Cell/PPULLVMRecompiler.h" #include "Emu/Cell/PPULLVMRecompiler.h"
#include "Emu/Memory/Memory.h" #include "Emu/Memory/Memory.h"
#include "llvm/Support/TargetSelect.h" #include "llvm/Support/TargetSelect.h"
@ -120,6 +121,12 @@ std::pair<Executable, llvm::ExecutionEngine *> Compiler::Compile(const std::stri
m_ir_builder->SetInsertPoint(GetBasicBlockFromAddress(0)); m_ir_builder->SetInsertPoint(GetBasicBlockFromAddress(0));
m_ir_builder->CreateBr(GetBasicBlockFromAddress(cfg.start_address)); m_ir_builder->CreateBr(GetBasicBlockFromAddress(cfg.start_address));
// Used to decode instructions
PPUDisAsm dis_asm(CPUDisAsm_DumpMode);
dis_asm.offset = vm::get_ptr<u8>(cfg.start_address);
m_recompilation_engine.Log() << "Recompiling block :\n\n";
// Convert each instruction in the CFG to LLVM IR // Convert each instruction in the CFG to LLVM IR
std::vector<PHINode *> exit_instr_list; std::vector<PHINode *> exit_instr_list;
for (u32 instr_i : cfg.instruction_addresses) { for (u32 instr_i : cfg.instruction_addresses) {
@ -130,6 +137,12 @@ std::pair<Executable, llvm::ExecutionEngine *> Compiler::Compile(const std::stri
if (instr_bb->empty()) { if (instr_bb->empty()) {
u32 instr = vm::ps3::read32(m_state.current_instruction_address); u32 instr = vm::ps3::read32(m_state.current_instruction_address);
// Dump PPU opcode
dis_asm.dump_pc = m_state.current_instruction_address * 4;
(*PPU_instr::main_list)(&dis_asm, instr);
m_recompilation_engine.Log() << dis_asm.last_opcode;
Decode(instr); Decode(instr);
if (!m_state.hit_branch_instruction) if (!m_state.hit_branch_instruction)
m_ir_builder->CreateBr(GetBasicBlockFromAddress(m_state.current_instruction_address + 4)); m_ir_builder->CreateBr(GetBasicBlockFromAddress(m_state.current_instruction_address + 4));
@ -210,6 +223,7 @@ std::pair<Executable, llvm::ExecutionEngine *> Compiler::Compile(const std::stri
} }
} }
m_recompilation_engine.Log() << "LLVM bytecode:\n";
m_recompilation_engine.Log() << *m_module; m_recompilation_engine.Log() << *m_module;
std::string verify; std::string verify;

8
rpcs3/Emu/Cell/PPULLVMRecompilerCore.cpp
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@ -2660,16 +2660,16 @@ void Compiler::MTOCRF(u32 l, u32 crm, u32 rs) {
for (u32 i = 0; i < 8; i++) { for (u32 i = 0; i < 8; i++) {
if (crm & (1 << i)) { if (crm & (1 << i)) {
mask |= 0xF << ((7 - i) * 4); mask |= 0xF << (i * 4); // move 0xF to the left i positions (in hex form)
if (l) { if (l) {
break; break;
} }
} }
} }
cr_i32 = m_ir_builder->CreateAnd(cr_i32, ~mask); cr_i32 = m_ir_builder->CreateAnd(cr_i32, ~mask); // null ith nibble
rs_i32 = m_ir_builder->CreateAnd(rs_i32, ~mask); rs_i32 = m_ir_builder->CreateAnd(rs_i32, mask); // null everything except ith nibble
cr_i32 = m_ir_builder->CreateOr(cr_i32, rs_i32); cr_i32 = m_ir_builder->CreateOr(cr_i32, rs_i32); // now ith cr nibble == ith rs nibble
SetCr(cr_i32); SetCr(cr_i32);
} }

3
rpcs3/Emu/Cell/PPULLVMRecompilerTests.cpp
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@ -692,7 +692,8 @@ void Compiler::RunAllTests() {
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFE, 5, 5, 21u, 22u, 23u, 0u, 1u); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFE, 5, 5, 21u, 22u, 23u, 0u, 1u);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDE, 0, 5, 7u, 8u, 9u, 0u, 0u); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDE, 0, 5, 7u, 8u, 9u, 0u, 0u);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDE, 5, 5, 21u, 22u, 23u, 0u, 1u); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDE, 5, 5, 21u, 22u, 23u, 0u, 1u);
// TODO: MTOCRF VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTOCRF, 0, 5, 7u, 8u, 0u);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTOCRF, 5, 5, 0u, 22u, 1u)
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDZE, 0, 5, 7u, 8u, 0u, 0u); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDZE, 0, 5, 7u, 8u, 0u, 0u);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDZE, 5, 5, 21u, 22u, 0u, 1u); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDZE, 5, 5, 21u, 22u, 0u, 1u);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFZE, 0, 5, 7u, 8u, 0u, 0u); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFZE, 0, 5, 7u, 8u, 0u, 0u);