mirror/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2025-03-13 07:14:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Debugger: Improve SPU/PPU vector registers

Browse Source
This commit is contained in:
Eladash 2020-11-11 05:59:24 +02:00 committed by Ivan
parent 908b2703f3
commit 74274f6d77
2 changed files with 22 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
rpcs3/Emu/Cell/PPUThread.cpp
View File

@ -513,9 +513,24 @@ std::string ppu_thread::dump_regs() const
fmt::append(ret, "f%d%s: %.6G\n", i, i <= 9 ? " " : "", fpr[i]); fmt::append(ret, "f%d%s: %.6G\n", i, i <= 9 ? " " : "", fpr[i]);
} }
for (uint i = 0; i < 32; ++i) for (uint i = 0; i < 32; ++i, ret += '\n')
{ {
fmt::append(ret, "v%d%s: %s [x: %g y: %g z: %g w: %g]\n", i, i <= 9 ? " " : "", vr[i], vr[i]._f[3], vr[i]._f[2], vr[i]._f[1], vr[i]._f[0]); fmt::append(ret, "v%d%s: ", i, i <= 9 ? " " : "");
const auto r = vr[i];
const u32 i3 = r.u32r[0];
if (v128::from32p(i3) == r)
{
// Shortand formatting
fmt::append(ret, "%08x", i3);
fmt::append(ret, " [x: %g]", r.fr[0]);
}
else
{
fmt::append(ret, "%08x %08x %08x %08x", r.u32r[0], r.u32r[1], r.u32r[2], r.u32r[3]);
fmt::append(ret, " [x: %g y: %g z: %g w: %g]", r.fr[0], r.fr[1], r.fr[2], r.fr[3]);
}
} }
fmt::append(ret, "CR: 0x%08x\n", cr.pack()); fmt::append(ret, "CR: 0x%08x\n", cr.pack());

8
rpcs3/Emu/Cell/SPUThread.cpp
View File

@ -1202,7 +1202,7 @@ std::string spu_thread::dump_regs() const
if (auto [size, dst, src] = SPUDisAsm::try_get_insert_mask_info(r); size) if (auto [size, dst, src] = SPUDisAsm::try_get_insert_mask_info(r); size)
{ {
// Special: insertation masks // Special: insertion masks
const std::string_view type = const std::string_view type =
size == 1 ? "byte" : size == 1 ? "byte" :
@ -1222,13 +1222,15 @@ std::string spu_thread::dump_regs() const
if (v128::from32p(i3) == r) if (v128::from32p(i3) == r)
{ {
// Shortand formatting // Shortand formatting
fmt::append(ret, "0x%08x$", i3); fmt::append(ret, "%08x", i3);
} }
else else
{ {
fmt::append(ret, "%s", r); fmt::append(ret, "%08x %08x %08x %08x", r.u32r[0], r.u32r[1], r.u32r[2], r.u32r[3]);
} }
// TODO: SPU floats fomatting
if (i3 >= 0x80 && is_exec_code(i3)) if (i3 >= 0x80 && is_exec_code(i3))
{ {
SPUDisAsm dis_asm(CPUDisAsm_NormalMode); SPUDisAsm dis_asm(CPUDisAsm_NormalMode);