From 74274f6d77bdb38faa9e0152433b0bb1825558d0 Mon Sep 17 00:00:00 2001
From: Eladash <elad3356p@gmail.com>
Date: Wed, 11 Nov 2020 05:59:24 +0200
Subject: [PATCH] Debugger: Improve SPU/PPU vector registers

---
 rpcs3/Emu/Cell/PPUThread.cpp | 19 +++++++++++++++++--
 rpcs3/Emu/Cell/SPUThread.cpp |  8 +++++---
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/rpcs3/Emu/Cell/PPUThread.cpp b/rpcs3/Emu/Cell/PPUThread.cpp
index 5668a55f48..69914af39d 100644
--- a/rpcs3/Emu/Cell/PPUThread.cpp
+++ b/rpcs3/Emu/Cell/PPUThread.cpp
@@ -513,9 +513,24 @@ std::string ppu_thread::dump_regs() const
 		fmt::append(ret, "f%d%s: %.6G\n", i, i <= 9 ? " " : "", fpr[i]);
 	}
 
-	for (uint i = 0; i < 32; ++i)
+	for (uint i = 0; i < 32; ++i, ret += '\n')
 	{
-		fmt::append(ret, "v%d%s: %s [x: %g y: %g z: %g w: %g]\n", i, i <= 9 ? " " : "", vr[i], vr[i]._f[3], vr[i]._f[2], vr[i]._f[1], vr[i]._f[0]);
+		fmt::append(ret, "v%d%s: ", i, i <= 9 ? " " : "");
+ 
+		const auto r = vr[i];
+		const u32 i3 = r.u32r[0];
+
+		if (v128::from32p(i3) == r)
+		{
+			// Shortand formatting
+			fmt::append(ret, "%08x", i3);
+			fmt::append(ret, " [x: %g]", r.fr[0]);
+		}
+		else
+		{
+			fmt::append(ret, "%08x %08x %08x %08x", r.u32r[0], r.u32r[1], r.u32r[2], r.u32r[3]);
+			fmt::append(ret, " [x: %g y: %g z: %g w: %g]", r.fr[0], r.fr[1], r.fr[2], r.fr[3]);
+		}
 	}
 
 	fmt::append(ret, "CR: 0x%08x\n", cr.pack());
diff --git a/rpcs3/Emu/Cell/SPUThread.cpp b/rpcs3/Emu/Cell/SPUThread.cpp
index 77d9bcd9b0..0906d9147c 100644
--- a/rpcs3/Emu/Cell/SPUThread.cpp
+++ b/rpcs3/Emu/Cell/SPUThread.cpp
@@ -1202,7 +1202,7 @@ std::string spu_thread::dump_regs() const
 
 		if (auto [size, dst, src] = SPUDisAsm::try_get_insert_mask_info(r); size)
 		{
-			// Special: insertation masks
+			// Special: insertion masks
 
 			const std::string_view type =
 				size == 1 ? "byte" :
@@ -1222,13 +1222,15 @@ std::string spu_thread::dump_regs() const
 		if (v128::from32p(i3) == r)
 		{
 			// Shortand formatting
-			fmt::append(ret, "0x%08x$", i3);
+			fmt::append(ret, "%08x", i3);
 		}
 		else
 		{
-			fmt::append(ret, "%s", r);
+			fmt::append(ret, "%08x %08x %08x %08x", r.u32r[0], r.u32r[1], r.u32r[2], r.u32r[3]);
 		}
 
+		// TODO: SPU floats fomatting
+
 		if (i3 >= 0x80 && is_exec_code(i3))
 		{
 			SPUDisAsm dis_asm(CPUDisAsm_NormalMode);