mirror of
https://github.com/Decompollaborate/rabbitizer.git
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b51b62da45
* setup ALLEGREX * more setup * clo * fix * Implement SPECIAL_RS and SPECIAL_SA instructions * more table placeholders * Implement bshfl instructions * Rename to R4000Allegrex * Implement SPECIAL instructions * Add tests * Remove some duplicated tests * Implement SPECIAL3 instructions * fix bug in test * update * Implement COPz * Implement SPECIAL2 instructions * Implement COP1 * Yeet cop3 * som tests * bvf, bvfl, bvt, bvtl * fix bshfl prefix * need to implement the vfpu registers * implement vt_7? * R4000AllegrexVF -> R4000AllegrexVScalar * Add test suite to compare with the sn toolchain decoding * more vfpu test cases * forgor this * I can't decide how to name these registers * Prepare tables for all register types * Fix typo * Implement vector scalar register operands * Implement quad registers * Fix tests? * svl.q, svr.q * Implement a bunch of vfpu0 instructions * implement registers for `.t` and `.p` instructions * Implement VFPU1 instructions * bleh * VFPU1, VFPU3 and `vcmp.` * Fix wrong register type on some instructions * start vfpu3 * Implement VFPU3 instructions * start categorizing VFPU4 * Categorize VFPU5 * VFPU6 identification * Identify VFPU7 * COP2 is weird * organize COP2 a bit * Add test cases for VFPU4 FMT * VFPU4 FMT2 stuff * VFPU4 FMT3 stuff * VFPU5 stuff * VFPU6 stuff * VFPU7 stuff * Implement COP2 instructions * Implement vmov, vabs and vneg * VPFU4 FMT0 FMT0 FMT0 implemented * VFPU FMT0 FMT0 FMT2 * vnrcp, vnsin, vrexp2 * vrnds, vrndi, vrndf1, vrndf2 * Change tests a bit * vf2h, vh2f, vsbz, vlgb * vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s * vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg * vsrt3, vsrt4, vsgn * vmfvc and vmtvc placeholders * vt4444, vt5551, vt5650 * vcst placeholder * vf2in * vf2iz * vf2iu, vf2id, vi2f * vcmovt, vcmovf * vwbn.s, viim.s, vfim.s * vpfxs, vpfxt, vpfxd, vnop, vsync, vflush * vmmov, vmidt, vmzero, vmone * vrot * vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul * Implement matrix operands * fix matrix operands * Fix `illegal` tests * hack out a way to check the test cases are assemblable * test-fixing: branches * fix more test cases * fix vmfvc and vmtvc * more test fixing * vdiv and fix operand R323 * more test fixing * Fix matrix operands * implement vcmp comparisons * fix vsync2 * vsqrt and vrndf1 fixes * Implement "constant" operand for `vcst` * Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f * Add missing vcmovt and vcmovf operands * Add missing vwbn operand * Tests cases for vmmul * Fix vtfm2 * Implement "transpose matrix register" * Add placeholders for the remaining missing operands * Implement viim operand * Implement vrot code operand * placeholders for rp and wp operands * test cases for vpfxs, vpfxt and vpfxd * Properly implement rpx, rpy, rpz and rpw * Properly implement wpx, wpy, wpz and wpw operands * Implement vfim * changelog * readme * some cleanup * Restructure some tables * more table restructure * fix tests * more table yeeting * more cleanup * more cleanup * reanming * moar * fmt
42 lines
1.9 KiB
C
42 lines
1.9 KiB
C
typedef struct ScePspFVector3 {
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float x, y, z;
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} ScePspFVector3;
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typedef struct ScePspFMatrix3 {
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ScePspFVector3 x, y, z;
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} ScePspFMatrix3;
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ScePspFVector3 *sceVfpuMatrix3Transform(ScePspFVector3 *pv0, const ScePspFMatrix3 *pm1, const ScePspFVector3 *pv2)
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{
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#if 0
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pv0->x = (pm1->x.x * pv2->x) + (pm1->y.x * pv2->y) + (pm1->z.x * pv2->z);
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pv0->y = (pm1->x.y * pv2->x) + (pm1->y.y * pv2->y) + (pm1->z.y * pv2->z);
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pv0->z = (pm1->x.z * pv2->x) + (pm1->y.z * pv2->y) + (pm1->z.z * pv2->z);
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#else
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__asm__ (
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".set push\n" // save assembler option
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".set noreorder\n" // suppress reordering
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"lv.s s100, 0 + %1\n" // s100 = pm1->x.x
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"lv.s s101, 4 + %1\n" // s101 = pm1->x.y
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"lv.s s102, 8 + %1\n" // s102 = pm1->x.z
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"lv.s s110, 12 + %1\n" // s110 = pm1->y.x
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"lv.s s111, 16 + %1\n" // s111 = pm1->y.y
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"lv.s s112, 20 + %1\n" // s112 = pm1->y.z
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"lv.s s120, 24 + %1\n" // s120 = pm1->z.x
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"lv.s s121, 28 + %1\n" // s121 = pm1->z.y
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"lv.s s122, 32 + %1\n" // s122 = pm1->z.z
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"lv.s s200, 0 + %2\n" // s200 = pv2->x
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"lv.s s201, 4 + %2\n" // s201 = pv2->y
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"lv.s s202, 8 + %2\n" // s202 = pv2->z
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"vctfm3.t c000, e100, c200\n" // c000 = e100 * c200
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"sv.s s000, 0 + %0\n" // pv0->x = s000
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"sv.s s001, 4 + %0\n" // pv0->y = s001
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"sv.s s002, 8 + %0\n" // pv0->z = s002
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".set pop\n" // restore assembler option
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: "=o"(*pv0)
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: "o"(*pm1), "o"(*pv2)
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);
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#endif
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return (pv0);
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}
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