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51 Commits

Author SHA1 Message Date
angie
02302f29b6 Fix some instructions missing their corresponding AccessType 2024-10-13 11:54:05 -03:00
angie
1c22fdcc43 New RegistersTracker.getJrRegData method to simplify getting jr information and RegistersTracker.processBranch to track register usage on branches 2024-07-19 13:58:06 -04:00
Angie
fc2e1098ec Fix vilwr and viswr 2024-07-15 20:28:41 -04:00
Angie
ef2598d2c7 Fix pmfhl and pmthl missing the .fmt specifier 2024-07-15 16:05:53 -04:00
Angie
2c5e2cfc26 Implement rfe 2024-07-13 17:30:13 -04:00
angie
ea58c73ecf Fix registers not being cleared after tail call 2024-07-12 09:57:33 -04:00
Anghelo Carvajal
b51b62da45
ALLEGREX support (#60) 
* setup ALLEGREX

* more setup

* clo

* fix

* Implement SPECIAL_RS and SPECIAL_SA instructions

* more table placeholders

* Implement bshfl instructions

* Rename to R4000Allegrex

* Implement SPECIAL instructions

* Add tests

* Remove some duplicated tests

* Implement SPECIAL3 instructions

* fix bug in test

* update

* Implement COPz

* Implement SPECIAL2 instructions

* Implement COP1

* Yeet cop3

* som tests

* bvf, bvfl, bvt, bvtl

* fix bshfl prefix

* need to implement the vfpu registers

* implement vt_7?

* R4000AllegrexVF -> R4000AllegrexVScalar

* Add test suite to compare with the sn toolchain decoding

* more vfpu test cases

* forgor this

* I can't decide how to name these registers

* Prepare tables for all register types

* Fix typo

* Implement vector scalar register operands

* Implement quad registers

* Fix tests?

* svl.q, svr.q

* Implement a bunch of vfpu0 instructions

* implement registers for `.t` and `.p` instructions

* Implement VFPU1 instructions

* bleh

* VFPU1, VFPU3 and `vcmp.`

* Fix wrong register type on some instructions

* start vfpu3

* Implement VFPU3 instructions

* start categorizing VFPU4

* Categorize VFPU5

* VFPU6 identification

* Identify VFPU7

* COP2 is weird

* organize COP2 a bit

* Add test cases for VFPU4 FMT

* VFPU4 FMT2 stuff

* VFPU4 FMT3 stuff

* VFPU5 stuff

* VFPU6 stuff

* VFPU7 stuff

* Implement COP2 instructions

* Implement vmov, vabs and vneg

* VPFU4 FMT0 FMT0 FMT0 implemented

* VFPU FMT0 FMT0 FMT2

* vnrcp, vnsin, vrexp2

* vrnds, vrndi, vrndf1, vrndf2

* Change tests a bit

* vf2h, vh2f, vsbz, vlgb

* vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s

* vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg

* vsrt3, vsrt4, vsgn

* vmfvc and vmtvc placeholders

* vt4444, vt5551, vt5650

* vcst placeholder

* vf2in

* vf2iz

* vf2iu, vf2id, vi2f

* vcmovt, vcmovf

* vwbn.s, viim.s, vfim.s

* vpfxs, vpfxt, vpfxd, vnop, vsync, vflush

* vmmov, vmidt, vmzero, vmone

* vrot

* vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul

* Implement matrix operands

* fix matrix operands

* Fix `illegal` tests

* hack out a way to check the test cases are assemblable

* test-fixing: branches

* fix more test cases

* fix vmfvc and vmtvc

* more test fixing

* vdiv and fix operand R323

* more test fixing

* Fix matrix operands

* implement vcmp comparisons

* fix vsync2

* vsqrt and vrndf1 fixes

* Implement "constant" operand for `vcst`

* Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f

* Add missing vcmovt and vcmovf operands

* Add missing vwbn operand

* Tests cases for vmmul

* Fix vtfm2

* Implement "transpose matrix register"

* Add placeholders for the remaining missing operands

* Implement viim operand

* Implement vrot code operand

* placeholders for rp and wp operands

* test cases for vpfxs, vpfxt and vpfxd

* Properly implement rpx, rpy, rpz and rpw

* Properly implement wpx, wpy, wpz and wpw operands

* Implement vfim

* changelog

* readme

* some cleanup

* Restructure some tables

* more table restructure

* fix tests

* more table yeeting

* more cleanup

* more cleanup

* reanming

* moar

* fmt
 2024-04-22 13:15:58 -04:00
angie
9bf73dd20b Fix typo 2024-04-13 15:04:04 -04:00
angie
757bb8d380 Fix rsp pref too 2024-03-11 09:30:45 -03:00
angie
13d5c1b069 Fix c.seq.d 2024-03-11 09:17:29 -03:00
Angie
c4360efe43 Fix pref 2024-03-10 16:56:29 -03:00
angie
a6ecfecb99 Implement neg pseudo 2024-02-18 11:34:07 -03:00
angie
5cd3ae194b Deprecate isImplemented 2024-02-11 13:17:10 -03:00
angie
728815fba3 Update copyright years 2024-01-28 12:16:11 -03:00
descawed
b92e43ef51
getBranchVramGeneric should return an unsigned value (#49) 
* getBranchVramGeneric should return an unsigned value

* Add test

* Revert "Add test"

This reverts commit 55e7bc12bf.
 2023-12-25 14:58:47 -03:00
angie
80aa0b6c20 Change flag_disasmAsData to flag_r5900DisasmAsData and redo the logic completely 2023-11-12 10:33:23 -03:00
angie
6b39156123 format 2023-11-11 13:56:40 -03:00
angie
111ee90a3a flag_r5900UseDollar 2023-11-11 13:55:06 -03:00
angie
049b47b32c flag_disasmAsData 2023-11-11 13:19:56 -03:00
angie
9a98ff93ee Properly implement r5900's vcallms operand 
Closes #42
 2023-09-13 10:45:11 -03:00
angie
619eba0c4a Bindings for InstrIdType 2023-05-04 13:44:22 -04:00
Angie
69f69357f7 Move all the tables into a tables folder 2023-05-02 19:01:54 -04:00
Angie
cd98ae0e0f Update copyright year in every file 2023-05-02 16:41:02 -04:00
angie
37b2ce06e2 Autogenerate pyi files 2023-04-30 17:39:05 -04:00
angie
3c8904b6fb Fix borken identation in tables 2023-04-30 15:58:01 -04:00
angie
d57c3b22b2 simplify including operand incs 2023-04-30 15:34:27 -04:00
angie
e8c39685fc format 2023-04-30 12:38:20 -04:00
angie
bf775c7351 C++ bindings for R3000GTE 2023-04-30 12:36:32 -04:00
Anghelo Carvajal
8237818ff9
Add R3000GTE instruction set support (#31) 
* initial gte setup

* starting to parse gte instructions

* R3000_GTE -> R3000GTE

* decode all the non-operand instructions

* remove printfs, whoops

* decode gte with operands

* cleanups

* bindings stuffs

* RabbitizerInstrId_isValid

* fix missing include
 2023-04-29 23:07:07 -04:00
angie
8a805123d4 Implement workaround for R5900's trunc.w.s issue 2023-04-16 10:05:01 -04:00
angie
eb11d93da9 Implement mfc2, mtc2, cfc2 and ctc2 2023-01-21 15:42:40 -03:00
angie
716d21f8ea fix "emitted" typo 2022-12-26 20:24:41 -03:00
angie
90eeda5f68 Change column limit to 120 2022-12-20 00:47:17 -03:00
angie
5063702a07 modifiesF* and readsF 2022-12-20 00:42:27 -03:00
angie
2e74fc914f outputsToGprZero 2022-12-19 19:04:26 -03:00
angie
6758468699 RegisterDescriptor 2022-12-19 17:07:32 -03:00
angie
ef2acdb328 Remove jalr_rd hack 2022-12-19 15:04:59 -03:00
angie
3735d91fcc Pregenerate every table 2022-12-16 15:37:46 -03:00
angie
61ccff4e42 Rename isJrRa to isReturn and isJrNotRa to isJumptableJump 2022-12-15 20:33:02 -03:00
angie
77dda82424 readsR* functions 2022-12-14 18:03:13 -03:00
angie
6d49bb4abf Remove signedness from access type and move it to doesUnsignedMemoryAccess 2022-10-16 17:02:50 -03:00
angie
5d0f9ad8f6 reads/modifies HI/LO 2022-10-14 14:58:14 -03:00
angie
71d241150f getDestinationGpr 2022-10-14 13:55:20 -03:00
angie
7cec779b85 AccessType enum 2022-10-13 19:41:46 -03:00
angie
c1a6abe186 Deprecate getGenericBranchOffset, add getBranchOffsetGeneric and getBranchVramGeneric 2022-10-13 17:41:50 -03:00
angie
faaf017aef isJumpWithAddress 2022-10-13 14:32:36 -03:00
Angie
72bf240f46 format 2022-10-10 20:24:41 -03:00
Angie
516b92f254 Fix building with g++ 2022-10-10 20:23:18 -03:00
Angie
ef58c6053e whoops 2022-10-09 18:35:31 -03:00
Angie
4ebd49711b add missing operand to trap instructions 2022-10-09 18:29:31 -03:00