15 Commits

Author SHA1 Message Date
Anghelo Carvajal
b51b62da45
ALLEGREX support (#60)
* setup ALLEGREX

* more setup

* clo

* fix

* Implement SPECIAL_RS and SPECIAL_SA instructions

* more table placeholders

* Implement bshfl instructions

* Rename to R4000Allegrex

* Implement SPECIAL instructions

* Add tests

* Remove some duplicated tests

* Implement SPECIAL3 instructions

* fix bug in test

* update

* Implement COPz

* Implement SPECIAL2 instructions

* Implement COP1

* Yeet cop3

* som tests

* bvf, bvfl, bvt, bvtl

* fix bshfl prefix

* need to implement the vfpu registers

* implement vt_7?

* R4000AllegrexVF -> R4000AllegrexVScalar

* Add test suite to compare with the sn toolchain decoding

* more vfpu test cases

* forgor this

* I can't decide how to name these registers

* Prepare tables for all register types

* Fix typo

* Implement vector scalar register operands

* Implement quad registers

* Fix tests?

* svl.q, svr.q

* Implement a bunch of vfpu0 instructions

* implement registers for `.t` and `.p` instructions

* Implement VFPU1 instructions

* bleh

* VFPU1, VFPU3 and `vcmp.`

* Fix wrong register type on some instructions

* start vfpu3

* Implement VFPU3 instructions

* start categorizing VFPU4

* Categorize VFPU5

* VFPU6 identification

* Identify VFPU7

* COP2 is weird

* organize COP2 a bit

* Add test cases for VFPU4 FMT

* VFPU4 FMT2 stuff

* VFPU4 FMT3 stuff

* VFPU5 stuff

* VFPU6 stuff

* VFPU7 stuff

* Implement COP2 instructions

* Implement vmov, vabs and vneg

* VPFU4 FMT0 FMT0 FMT0 implemented

* VFPU FMT0 FMT0 FMT2

* vnrcp, vnsin, vrexp2

* vrnds, vrndi, vrndf1, vrndf2

* Change tests a bit

* vf2h, vh2f, vsbz, vlgb

* vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s

* vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg

* vsrt3, vsrt4, vsgn

* vmfvc and vmtvc placeholders

* vt4444, vt5551, vt5650

* vcst placeholder

* vf2in

* vf2iz

* vf2iu, vf2id, vi2f

* vcmovt, vcmovf

* vwbn.s, viim.s, vfim.s

* vpfxs, vpfxt, vpfxd, vnop, vsync, vflush

* vmmov, vmidt, vmzero, vmone

* vrot

* vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul

* Implement matrix operands

* fix matrix operands

* Fix `illegal` tests

* hack out a way to check the test cases are assemblable

* test-fixing: branches

* fix more test cases

* fix vmfvc and vmtvc

* more test fixing

* vdiv and fix operand R323

* more test fixing

* Fix matrix operands

* implement vcmp comparisons

* fix vsync2

* vsqrt and vrndf1 fixes

* Implement "constant" operand for `vcst`

* Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f

* Add missing vcmovt and vcmovf operands

* Add missing vwbn operand

* Tests cases for vmmul

* Fix vtfm2

* Implement "transpose matrix register"

* Add placeholders for the remaining missing operands

* Implement viim operand

* Implement vrot code operand

* placeholders for rp and wp operands

* test cases for vpfxs, vpfxt and vpfxd

* Properly implement rpx, rpy, rpz and rpw

* Properly implement wpx, wpy, wpz and wpw operands

* Implement vfim

* changelog

* readme

* some cleanup

* Restructure some tables

* more table restructure

* fix tests

* more table yeeting

* more cleanup

* more cleanup

* reanming

* moar

* fmt
2024-04-22 13:15:58 -04:00
angie
728815fba3 Update copyright years 2024-01-28 12:16:11 -03:00
Angie
69f69357f7 Move all the tables into a tables folder 2023-05-02 19:01:54 -04:00
Angie
cd98ae0e0f Update copyright year in every file 2023-05-02 16:41:02 -04:00
angie
90eeda5f68 Change column limit to 120 2022-12-20 00:47:17 -03:00
angie
75fe4e4fe3 use registerdescriptors 2022-12-19 18:38:05 -03:00
angie
3735d91fcc Pregenerate every table 2022-12-16 15:37:46 -03:00
Anghelo Carvajal
136fb7a09a
Add R5900 support (#5)
* starting r5900 stuff

* operands of pmaddh

* expose R5900 to python

* fix merge issues

* move to subtables

* mmi0 and mmi3

* the rest of mmi instructions

* normal, special, regimm and cop0

* fpu_s

* cop2 special1

* starting cop2 special2

* the rest of special2

* operands for normal, special, mmi and mmi0

* mmi1 and mmi2

* Fix mmi

* sync.p

* mmi3 and cop1

* add r5900 opcodes to InstrId.pyi

* add invalid bits to unknown instruction comment

* progress on cop2 special1

* kinda finish cop2 special1

* cop2 special2 progress

* Special case for R5900 cvt.w.s -> trunc.w.s

* R5900 c.olt.s and c.ole.s

* Fix a bunch of VU0 instructions

* I'm getting tired of this bullshit

* vlqi, vsqi, vlqd, vsqd

* fix some operands

* fix div1

* lqc2 and sqc2

* sqrt.s and mult

* fix mtsa and bc2

* Remove redundant .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN

* RabbitizerInstrSuffix

* Impleme instr suffix type

* add instr suffix to remaining instructions

* ifdef out xyzw suffix from registers

* format

* fix warnings

* uncomment stuff on InstrId.pyi

* readme
2022-08-27 12:22:48 -04:00
Anghelo Carvajal
f8979ede3e
Fix RSP instruction decoding (#4)
* Use the proper registers on RSP GPR instructions

* Add IMM_base operand to RSP instructions

* Use `ra` on RSP GPR registers

* Fix RABBITIZER_OPERAND_TYPE_RSP_rd

* ??

* fix vector register element index

* fix RSP mfc2 and mtc2

* fix vmov and similar instructions

* format

* update readme

* version pump
2022-08-22 16:27:51 -04:00
angie
baaef2f242 Format files with clang-format and add a format rule to makefile 2022-07-09 17:40:53 -04:00
angie
6b7650476f Change capitalization 2022-06-05 13:19:45 -04:00
angie
4cbc14c813 FpcCsr 2022-06-05 02:19:05 -04:00
angie
145114c096 toggle register names 2022-06-05 01:57:22 -04:00
angie
6a0cdbb637 more stuff 2022-06-04 23:23:06 -04:00
angie
2e5ed6a0b6 Implement every RegisterType 2022-06-03 22:39:10 -04:00