2024-01-28 12:16:11 -03:00
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/* SPDX-FileCopyrightText: © 2022-2024 Decompollaborate */
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2022-06-03 20:19:58 -04:00
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/* SPDX-License-Identifier: MIT */
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2022-06-03 22:39:10 -04:00
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#ifndef RABBITIZER_UTILS_H
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#define RABBITIZER_UTILS_H
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2022-06-04 01:24:59 -04:00
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#include <stddef.h>
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2022-06-03 22:39:10 -04:00
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#include <stdint.h>
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2022-10-04 08:31:02 -03:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2022-06-03 20:19:58 -04:00
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2022-06-06 01:59:38 -04:00
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#if !defined(__GNUC__) && !defined(__clang__)
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#define __attribute__(x)
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#endif
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2023-05-01 20:59:01 -04:00
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#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202000L) || (defined(__cplusplus) && __cplusplus >= 201103L)
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2022-07-09 19:19:53 -04:00
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#define CONST [[gnu::const]]
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2022-06-06 01:59:38 -04:00
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#define DEPRECATED(reason) [[deprecated (reason)]]
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#define FALLTHROUGH [[fallthrough]]
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#define NODISCARD [[nodiscard]]
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#define NORETURN [[noreturn]]
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#define NON_NULL(...) [[gnu::nonnull (__VA_ARGS__)]]
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#define PURE [[gnu::pure]]
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#define RETURNS_NON_NULL [[gnu::returns_nonnull]]
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#define UNUSED [[maybe_unused]]
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#else
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#define CONST __attribute__((const))
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2022-06-06 01:59:38 -04:00
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#define DEPRECATED(reason) __attribute__((deprecated (reason)))
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#define FALLTHROUGH __attribute__((fallthrough))
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#define NODISCARD __attribute__((warn_unused_result))
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2022-06-06 01:59:38 -04:00
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#define NORETURN _Noreturn
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#define NON_NULL(...) __attribute__((nonnull (__VA_ARGS__)))
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#define PURE __attribute__((pure))
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#define RETURNS_NON_NULL __attribute__((returns_nonnull))
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2022-06-06 01:59:38 -04:00
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#define UNUSED __attribute__((unused))
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#endif
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2022-07-09 19:19:53 -04:00
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2022-06-10 14:01:00 -04:00
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#if defined(_MSC_VER)
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# define UNREACHABLE __assume(0)
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#elif defined(__GNUC__) || defined(__clang__)
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2022-06-10 14:01:00 -04:00
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# define UNREACHABLE __builtin_unreachable()
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#else
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# define UNREACHABLE
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#endif
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2023-11-11 13:19:56 -03:00
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typedef enum RabTrinaryValue {
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RAB_TRINARY_VAL_NONE,
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RAB_TRINARY_VAL_FALSE,
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RAB_TRINARY_VAL_TRUE,
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} RabTrinaryValue;
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#define ARRAY_COUNT(arr) (sizeof(arr) / sizeof((arr)[0]))
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2022-06-03 20:19:58 -04:00
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2023-08-08 12:18:23 -04:00
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#define RAB_MAX(a, b) ((a) > (b) ? (a) : (b))
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#define RAB_MIN(a, b) ((a) < (b) ? (a) : (b))
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2023-02-23 13:50:05 -03:00
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#define RAB_STRINGIFY2(x) #x
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#define RAB_STRINGIFY(x) RAB_STRINGIFY2(x)
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2022-09-26 11:15:28 -03:00
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ALLEGREX support (#60)
* setup ALLEGREX
* more setup
* clo
* fix
* Implement SPECIAL_RS and SPECIAL_SA instructions
* more table placeholders
* Implement bshfl instructions
* Rename to R4000Allegrex
* Implement SPECIAL instructions
* Add tests
* Remove some duplicated tests
* Implement SPECIAL3 instructions
* fix bug in test
* update
* Implement COPz
* Implement SPECIAL2 instructions
* Implement COP1
* Yeet cop3
* som tests
* bvf, bvfl, bvt, bvtl
* fix bshfl prefix
* need to implement the vfpu registers
* implement vt_7?
* R4000AllegrexVF -> R4000AllegrexVScalar
* Add test suite to compare with the sn toolchain decoding
* more vfpu test cases
* forgor this
* I can't decide how to name these registers
* Prepare tables for all register types
* Fix typo
* Implement vector scalar register operands
* Implement quad registers
* Fix tests?
* svl.q, svr.q
* Implement a bunch of vfpu0 instructions
* implement registers for `.t` and `.p` instructions
* Implement VFPU1 instructions
* bleh
* VFPU1, VFPU3 and `vcmp.`
* Fix wrong register type on some instructions
* start vfpu3
* Implement VFPU3 instructions
* start categorizing VFPU4
* Categorize VFPU5
* VFPU6 identification
* Identify VFPU7
* COP2 is weird
* organize COP2 a bit
* Add test cases for VFPU4 FMT
* VFPU4 FMT2 stuff
* VFPU4 FMT3 stuff
* VFPU5 stuff
* VFPU6 stuff
* VFPU7 stuff
* Implement COP2 instructions
* Implement vmov, vabs and vneg
* VPFU4 FMT0 FMT0 FMT0 implemented
* VFPU FMT0 FMT0 FMT2
* vnrcp, vnsin, vrexp2
* vrnds, vrndi, vrndf1, vrndf2
* Change tests a bit
* vf2h, vh2f, vsbz, vlgb
* vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s
* vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg
* vsrt3, vsrt4, vsgn
* vmfvc and vmtvc placeholders
* vt4444, vt5551, vt5650
* vcst placeholder
* vf2in
* vf2iz
* vf2iu, vf2id, vi2f
* vcmovt, vcmovf
* vwbn.s, viim.s, vfim.s
* vpfxs, vpfxt, vpfxd, vnop, vsync, vflush
* vmmov, vmidt, vmzero, vmone
* vrot
* vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul
* Implement matrix operands
* fix matrix operands
* Fix `illegal` tests
* hack out a way to check the test cases are assemblable
* test-fixing: branches
* fix more test cases
* fix vmfvc and vmtvc
* more test fixing
* vdiv and fix operand R323
* more test fixing
* Fix matrix operands
* implement vcmp comparisons
* fix vsync2
* vsqrt and vrndf1 fixes
* Implement "constant" operand for `vcst`
* Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f
* Add missing vcmovt and vcmovf operands
* Add missing vwbn operand
* Tests cases for vmmul
* Fix vtfm2
* Implement "transpose matrix register"
* Add placeholders for the remaining missing operands
* Implement viim operand
* Implement vrot code operand
* placeholders for rp and wp operands
* test cases for vpfxs, vpfxt and vpfxd
* Properly implement rpx, rpy, rpz and rpw
* Properly implement wpx, wpy, wpz and wpw operands
* Implement vfim
* changelog
* readme
* some cleanup
* Restructure some tables
* more table restructure
* fix tests
* more table yeeting
* more cleanup
* more cleanup
* reanming
* moar
* fmt
2024-04-22 13:15:58 -04:00
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#define MASK(v, w) ((v) & ((1U << (w)) - 1U))
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2022-07-03 08:34:26 -04:00
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/*
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* the SHIFT macros take a value, a shift amount, and a width.
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*
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* For the left shift, the lower bits of the value are masked,
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* then shifted left.
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*
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* For the right shift, the value is shifted right, then the lower bits
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* are masked.
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*
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* (NOTE: SHIFTL(v, 0, 32) won't work, just use an assignment)
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*
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*/
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2022-07-05 00:53:28 -04:00
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#define SHIFTL(v, s, w) (MASK((v), (w)) << (s))
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#define SHIFTR(v, s, w) (MASK((v) >> (s), (w)))
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2022-07-03 08:34:26 -04:00
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ALLEGREX support (#60)
* setup ALLEGREX
* more setup
* clo
* fix
* Implement SPECIAL_RS and SPECIAL_SA instructions
* more table placeholders
* Implement bshfl instructions
* Rename to R4000Allegrex
* Implement SPECIAL instructions
* Add tests
* Remove some duplicated tests
* Implement SPECIAL3 instructions
* fix bug in test
* update
* Implement COPz
* Implement SPECIAL2 instructions
* Implement COP1
* Yeet cop3
* som tests
* bvf, bvfl, bvt, bvtl
* fix bshfl prefix
* need to implement the vfpu registers
* implement vt_7?
* R4000AllegrexVF -> R4000AllegrexVScalar
* Add test suite to compare with the sn toolchain decoding
* more vfpu test cases
* forgor this
* I can't decide how to name these registers
* Prepare tables for all register types
* Fix typo
* Implement vector scalar register operands
* Implement quad registers
* Fix tests?
* svl.q, svr.q
* Implement a bunch of vfpu0 instructions
* implement registers for `.t` and `.p` instructions
* Implement VFPU1 instructions
* bleh
* VFPU1, VFPU3 and `vcmp.`
* Fix wrong register type on some instructions
* start vfpu3
* Implement VFPU3 instructions
* start categorizing VFPU4
* Categorize VFPU5
* VFPU6 identification
* Identify VFPU7
* COP2 is weird
* organize COP2 a bit
* Add test cases for VFPU4 FMT
* VFPU4 FMT2 stuff
* VFPU4 FMT3 stuff
* VFPU5 stuff
* VFPU6 stuff
* VFPU7 stuff
* Implement COP2 instructions
* Implement vmov, vabs and vneg
* VPFU4 FMT0 FMT0 FMT0 implemented
* VFPU FMT0 FMT0 FMT2
* vnrcp, vnsin, vrexp2
* vrnds, vrndi, vrndf1, vrndf2
* Change tests a bit
* vf2h, vh2f, vsbz, vlgb
* vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s
* vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg
* vsrt3, vsrt4, vsgn
* vmfvc and vmtvc placeholders
* vt4444, vt5551, vt5650
* vcst placeholder
* vf2in
* vf2iz
* vf2iu, vf2id, vi2f
* vcmovt, vcmovf
* vwbn.s, viim.s, vfim.s
* vpfxs, vpfxt, vpfxd, vnop, vsync, vflush
* vmmov, vmidt, vmzero, vmone
* vrot
* vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul
* Implement matrix operands
* fix matrix operands
* Fix `illegal` tests
* hack out a way to check the test cases are assemblable
* test-fixing: branches
* fix more test cases
* fix vmfvc and vmtvc
* more test fixing
* vdiv and fix operand R323
* more test fixing
* Fix matrix operands
* implement vcmp comparisons
* fix vsync2
* vsqrt and vrndf1 fixes
* Implement "constant" operand for `vcst`
* Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f
* Add missing vcmovt and vcmovf operands
* Add missing vwbn operand
* Tests cases for vmmul
* Fix vtfm2
* Implement "transpose matrix register"
* Add placeholders for the remaining missing operands
* Implement viim operand
* Implement vrot code operand
* placeholders for rp and wp operands
* test cases for vpfxs, vpfxt and vpfxd
* Properly implement rpx, rpy, rpz and rpw
* Properly implement wpx, wpy, wpz and wpw operands
* Implement vfim
* changelog
* readme
* some cleanup
* Restructure some tables
* more table restructure
* fix tests
* more table yeeting
* more cleanup
* more cleanup
* reanming
* moar
* fmt
2024-04-22 13:15:58 -04:00
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#define BITREPACK(fullword, v, s, w) ((SHIFTR((fullword), (s)+(w), 32U-((s)+(w))) << ((s)+(w))) | SHIFTL((v), (s), (w)) | MASK((fullword), (s)))
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2022-07-03 19:28:13 -04:00
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#define BITREPACK_RIGHT(fullword, v, s, w) (SHIFTL((v), (s), (w)) | MASK((fullword), (s)))
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2022-07-03 08:34:26 -04:00
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2022-07-10 16:04:39 -04:00
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#define RABUTILS_BUFFER_ADVANCE(buffer, totalSize, expression) \
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do { \
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2023-05-01 23:04:58 -04:00
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size_t __tempSize = (size_t)(expression); \
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2024-04-03 12:45:21 -03:00
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if ((buffer) != NULL) { \
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(buffer) += __tempSize; \
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} \
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(totalSize) += __tempSize; \
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} while (0)
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#define RABUTILS_BUFFER_WRITE_CHAR(buffer, totalSize, character) \
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do { \
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if ((buffer) != NULL) { \
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2024-04-03 12:41:26 -03:00
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*(buffer) = (character); \
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} \
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2022-07-10 16:04:39 -04:00
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RABUTILS_BUFFER_ADVANCE(buffer, totalSize, 1); \
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} while (0)
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#define RABUTILS_BUFFER_SPRINTF(buffer, totalSize, format, ...) \
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do { \
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int _len; \
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if (buffer != NULL) { \
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_len = sprintf(buffer, format, __VA_ARGS__); \
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} else { \
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_len = snprintf(NULL, 0, format, __VA_ARGS__); \
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} \
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2022-07-10 16:04:39 -04:00
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assert(_len > 0); \
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RABUTILS_BUFFER_ADVANCE(buffer, totalSize, _len); \
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} while (0)
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#define RABUTILS_BUFFER_CPY(buffer, totalSize, string) \
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do { \
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size_t _tempSize = strlen(string); \
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2024-04-03 12:45:21 -03:00
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if ((buffer) != NULL) { \
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2024-04-03 12:41:26 -03:00
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memcpy(buffer, string, _tempSize); \
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} \
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2022-07-10 16:04:39 -04:00
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RABUTILS_BUFFER_ADVANCE(buffer, totalSize, _tempSize); \
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} while (0)
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2022-07-09 19:19:53 -04:00
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CONST NODISCARD
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2022-06-03 22:39:10 -04:00
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int32_t RabbitizerUtils_From2Complement(uint32_t number, int bits);
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2022-07-09 19:19:53 -04:00
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NON_NULL(1)
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2022-06-04 01:24:59 -04:00
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size_t RabbitizerUtils_CharFill(char *dst, int count, char fillchar);
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2022-07-10 16:04:39 -04:00
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NON_NULL(1, 3)
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size_t RabbitizerUtils_escapeString(char *dst, size_t dstSize, const char *src, size_t srcSize);
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ALLEGREX support (#60)
* setup ALLEGREX
* more setup
* clo
* fix
* Implement SPECIAL_RS and SPECIAL_SA instructions
* more table placeholders
* Implement bshfl instructions
* Rename to R4000Allegrex
* Implement SPECIAL instructions
* Add tests
* Remove some duplicated tests
* Implement SPECIAL3 instructions
* fix bug in test
* update
* Implement COPz
* Implement SPECIAL2 instructions
* Implement COP1
* Yeet cop3
* som tests
* bvf, bvfl, bvt, bvtl
* fix bshfl prefix
* need to implement the vfpu registers
* implement vt_7?
* R4000AllegrexVF -> R4000AllegrexVScalar
* Add test suite to compare with the sn toolchain decoding
* more vfpu test cases
* forgor this
* I can't decide how to name these registers
* Prepare tables for all register types
* Fix typo
* Implement vector scalar register operands
* Implement quad registers
* Fix tests?
* svl.q, svr.q
* Implement a bunch of vfpu0 instructions
* implement registers for `.t` and `.p` instructions
* Implement VFPU1 instructions
* bleh
* VFPU1, VFPU3 and `vcmp.`
* Fix wrong register type on some instructions
* start vfpu3
* Implement VFPU3 instructions
* start categorizing VFPU4
* Categorize VFPU5
* VFPU6 identification
* Identify VFPU7
* COP2 is weird
* organize COP2 a bit
* Add test cases for VFPU4 FMT
* VFPU4 FMT2 stuff
* VFPU4 FMT3 stuff
* VFPU5 stuff
* VFPU6 stuff
* VFPU7 stuff
* Implement COP2 instructions
* Implement vmov, vabs and vneg
* VPFU4 FMT0 FMT0 FMT0 implemented
* VFPU FMT0 FMT0 FMT2
* vnrcp, vnsin, vrexp2
* vrnds, vrndi, vrndf1, vrndf2
* Change tests a bit
* vf2h, vh2f, vsbz, vlgb
* vuc2ifs, vc2i, vus2i, vs2i, vi2uc, vi2c, vi2us, vi2s
* vsrt1, vsrt2, vbfy1, vbfy2, vocp, vsocp, vfad, vavg
* vsrt3, vsrt4, vsgn
* vmfvc and vmtvc placeholders
* vt4444, vt5551, vt5650
* vcst placeholder
* vf2in
* vf2iz
* vf2iu, vf2id, vi2f
* vcmovt, vcmovf
* vwbn.s, viim.s, vfim.s
* vpfxs, vpfxt, vpfxd, vnop, vsync, vflush
* vmmov, vmidt, vmzero, vmone
* vrot
* vmmul, vhtfm2, vtfm2, vhtfm3, vtfm3, vhtfm4, vtfm4, vmscl, vcrsp, vqmul
* Implement matrix operands
* fix matrix operands
* Fix `illegal` tests
* hack out a way to check the test cases are assemblable
* test-fixing: branches
* fix more test cases
* fix vmfvc and vmtvc
* more test fixing
* vdiv and fix operand R323
* more test fixing
* Fix matrix operands
* implement vcmp comparisons
* fix vsync2
* vsqrt and vrndf1 fixes
* Implement "constant" operand for `vcst`
* Add missing operand of vf2in, vf2iz, vf2iu, vf2id, vi2f
* Add missing vcmovt and vcmovf operands
* Add missing vwbn operand
* Tests cases for vmmul
* Fix vtfm2
* Implement "transpose matrix register"
* Add placeholders for the remaining missing operands
* Implement viim operand
* Implement vrot code operand
* placeholders for rp and wp operands
* test cases for vpfxs, vpfxt and vpfxd
* Properly implement rpx, rpy, rpz and rpw
* Properly implement wpx, wpy, wpz and wpw operands
* Implement vfim
* changelog
* readme
* some cleanup
* Restructure some tables
* more table restructure
* fix tests
* more table yeeting
* more cleanup
* more cleanup
* reanming
* moar
* fmt
2024-04-22 13:15:58 -04:00
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CONST NODISCARD
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uint32_t RabbitizerUtils_floatRepr_32From16(uint16_t arg);
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2022-06-03 22:39:10 -04:00
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2022-10-04 08:31:02 -03:00
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#ifdef __cplusplus
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}
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#endif
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2022-06-03 20:19:58 -04:00
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#endif
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