1
0
mirror of https://github.com/CTCaer/hekate.git synced 2024-12-29 09:26:55 +00:00
hekate/bdk/mem
CTCaer 2648a2655c bdk: sdram: add info about custom 8GB T210 config
That's a suggestion on which 4GB modules are certainly fine to use.
2024-04-25 04:50:07 +03:00
..
emc.h sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
heap.c bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
heap.h bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
mc_t210.h bdk: smmu: refactor driver and allow other asid 2024-03-13 01:54:46 +02:00
mc.c bdk: mc: remove some redundant carveout cfg 2024-01-07 12:33:29 +02:00
mc.h
minerva.c bdk: minerva: l4t: adjust sdmmc1 la and freq table 2024-03-29 13:21:53 +02:00
minerva.h bdk: minerva: l4t: adjust sdmmc1 la and freq table 2024-03-29 13:21:53 +02:00
mtc_table.h bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
sdram_config_t210b01.inl bdk: update copyright year 2024-01-07 12:38:10 +02:00
sdram_config.inl bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
sdram_param_t210.h
sdram_param_t210b01.h
sdram.c sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
sdram.h bdk: sdram: add info about custom 8GB T210 config 2024-04-25 04:50:07 +03:00
smmu.c bdk: smmu: refactor and update driver 2024-03-14 09:21:06 +02:00
smmu.h bdk: smmu: refactor and update driver 2024-03-14 09:21:06 +02:00