mirror of
https://github.com/CTCaer/hekate.git
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bdk: smmu: refactor driver and allow other asid
This commit is contained in:
parent
20e661fc01
commit
9a520d63a6
@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2014, NVIDIA Corporation.
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* Copyright (c) 2018-2023, CTCaer
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -14,6 +15,22 @@
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#ifndef _MC_T210_H_
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#define _MC_T210_H_
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/*! MC SMMU registers */
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#define MC_SMMU_CONFIG 0x10
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#define MC_SMMU_TLB_CONFIG 0x14
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#define MC_SMMU_PTC_CONFIG 0x18
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#define MC_SMMU_PTB_ASID 0x1c
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#define MC_SMMU_PTB_DATA 0x20
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
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#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
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#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
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#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
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/*! MC General registers */
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#define MC_INTSTATUS 0x0
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#define MC_INTMASK 0x4
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#define MC_ERR_STATUS 0x8
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@ -464,7 +481,7 @@
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#define MC_UNTRANSLATED_REGION_CHECK 0x948
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#define MC_DA_CONFIG0 0x9dc
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/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */
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/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */
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#define SEC_CARVEOUT_CA0_R_PTCR BIT(0)
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#define SEC_CARVEOUT_CA0_R_DISPLAY0A BIT(1)
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#define SEC_CARVEOUT_CA0_R_DISPLAY0AB BIT(2)
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@ -484,7 +501,7 @@
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#define SEC_CARVEOUT_CA0_R_PPCSAHBSLV BIT(30)
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#define SEC_CARVEOUT_CA0_R_SATAR BIT(31)
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/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */
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/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */
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#define SEC_CARVEOUT_CA1_R_VDEBSEV BIT(2)
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#define SEC_CARVEOUT_CA1_R_VDEMBE BIT(3)
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#define SEC_CARVEOUT_CA1_R_VDEMCE BIT(4)
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@ -504,7 +521,7 @@
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#define SEC_CARVEOUT_CA1_W_VDEBSEV BIT(30)
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#define SEC_CARVEOUT_CA1_W_VDEDBG BIT(31)
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/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */
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/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */
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#define SEC_CARVEOUT_CA2_W_VDEMBE BIT(0)
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#define SEC_CARVEOUT_CA2_W_VDETPM BIT(1)
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#define SEC_CARVEOUT_CA2_R_ISPRA BIT(4)
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@ -524,7 +541,7 @@
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#define SEC_CARVEOUT_CA2_W_GPU BIT(25)
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#define SEC_CARVEOUT_CA2_R_DISPLAYT BIT(26)
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/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */
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/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */
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#define SEC_CARVEOUT_CA3_R_SDMMCA BIT(0)
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#define SEC_CARVEOUT_CA3_R_SDMMCAA BIT(1)
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#define SEC_CARVEOUT_CA3_R_SDMMC BIT(2)
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@ -544,7 +561,7 @@
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#define SEC_CARVEOUT_CA3_R_NVJPG BIT(30)
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#define SEC_CARVEOUT_CA3_W_NVJPG BIT(31)
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/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */
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/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */
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#define SEC_CARVEOUT_CA4_R_SE BIT(0)
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#define SEC_CARVEOUT_CA4_W_SE BIT(1)
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#define SEC_CARVEOUT_CA4_R_AXIAP BIT(2)
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@ -23,6 +23,23 @@
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#include <soc/t210.h>
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#include <mem/mc_t210.h>
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#include <mem/smmu.h>
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#include <memory_map.h>
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT)
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT)
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#define SMMU_PDIR_SHIFT 12
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#define SMMU_PDE_SHIFT 12
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PFN_MASK 0x000FFFFF
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
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#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
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#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
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u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
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@ -37,7 +54,7 @@ u8 smmu_payload[] __attribute__((aligned(16))) = {
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0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG
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};
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void *page_alloc(u32 num)
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void *smmu_page_zalloc(u32 num)
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{
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u8 *res = _pageheap;
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_pageheap += SZ_PAGE * num;
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@ -45,15 +62,15 @@ void *page_alloc(u32 num)
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return res;
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}
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u32 *smmu_alloc_pdir()
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static u32 *_smmu_pdir_alloc()
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{
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u32 *pdir = (u32 *)page_alloc(1);
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u32 *pdir = (u32 *)smmu_page_zalloc(1);
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for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
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pdir[pdn] = _PDE_VACANT(pdn);
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return pdir;
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}
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void smmu_flush_regs()
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static void _smmu_flush_regs()
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{
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(void)MC(MC_SMMU_PTB_DATA);
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}
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@ -61,10 +78,10 @@ void smmu_flush_regs()
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void smmu_flush_all()
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{
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MC(MC_SMMU_PTC_FLUSH) = 0;
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smmu_flush_regs();
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_smmu_flush_regs();
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MC(MC_SMMU_TLB_FLUSH) = 0;
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smmu_flush_regs();
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_smmu_flush_regs();
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}
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void smmu_init()
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@ -95,14 +112,14 @@ void smmu_enable()
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u32 *smmu_init_domain4(u32 dev_base, u32 asid)
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{
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u32 *pdir = smmu_alloc_pdir();
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u32 *pdir = _smmu_pdir_alloc();
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
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smmu_flush_regs();
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_smmu_flush_regs();
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MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
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smmu_flush_regs();
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_smmu_flush_regs();
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return pdir;
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}
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@ -117,7 +134,7 @@ u32 *smmu_get_pte(u32 *pdir, u32 iova)
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ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
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else
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{
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ptbl = (u32 *)page_alloc(1);
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ptbl = (u32 *)smmu_page_zalloc(1);
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u32 addr = SMMU_PDN_TO_ADDR(pdn);
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for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
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ptbl[pn] = _PTE_VACANT(addr);
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@ -140,16 +157,16 @@ void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
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smmu_flush_all();
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}
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u32 *smmu_init_for_tsec()
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u32 *smmu_init_domain(u32 asid)
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{
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return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1);
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return smmu_init_domain4(asid, 1);
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}
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void smmu_deinit_for_tsec()
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void smmu_deinit_domain(u32 asid)
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{
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MC(MC_SMMU_PTB_ASID) = 1;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TSEC_ASID) = 0;
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smmu_flush_regs();
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MC(asid) = 0;
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_smmu_flush_regs();
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}
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#include <utils/types.h>
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#define SMMU_HEAP_ADDR 0xA0000000
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#define MC_INTSTATUS 0x0
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#define MC_INTMASK 0x4
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#define MC_ERR_STATUS 0x8
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#define MC_ERR_ADR 0xc
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#define MC_SMMU_CONFIG 0x10
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#define MC_SMMU_TLB_CONFIG 0x14
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#define MC_SMMU_PTC_CONFIG 0x18
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#define MC_SMMU_PTB_ASID 0x1c
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#define MC_SMMU_PTB_DATA 0x20
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_AVPC_ASID 0x23C
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#define MC_SMMU_TSEC_ASID 0x294
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#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
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#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
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#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
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#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
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#define SMMU_PDE_NEXT_SHIFT 28
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#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
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#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT 30
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#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT 31
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT)
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT)
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#define SMMU_PDIR_SHIFT 12
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#define SMMU_PDE_SHIFT 12
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PFN_MASK 0x000FFFFF
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
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#define _READABLE (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
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#define _WRITABLE (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
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#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
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@ -66,17 +34,13 @@
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#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
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#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
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#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
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#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
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void *page_alloc(u32 num);
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u32 *smmu_alloc_pdir();
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void smmu_flush_regs();
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void smmu_flush_all();
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void smmu_init();
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void smmu_enable();
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u32 *smmu_init_domain4(u32 dev_base, u32 asid);
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u32 *smmu_get_pte(u32 *pdir, u32 iova);
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
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u32 *smmu_init_for_tsec();
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void smmu_deinit_for_tsec();
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void *smmu_page_zalloc(u32 num);
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void smmu_flush_all();
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void smmu_init();
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void smmu_enable();
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u32 *smmu_init_domain4(u32 dev_base, u32 asid);
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u32 *smmu_get_pte(u32 *pdir, u32 iova);
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
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u32 *smmu_init_domain(u32 asid);
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void smmu_deinit_domain(u32 asid);
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@ -50,7 +50,9 @@
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/* Stack theoretical max: 33MB */
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#define IPL_STACK_TOP 0x83100000
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#define IPL_HEAP_START 0x84000000
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#define IPL_HEAP_SZ SZ_512M
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#define IPL_HEAP_SZ (SZ_512M - SZ_64M)
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#define SMMU_HEAP_ADDR 0xA0000000
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/* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */
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// Virtual disk / Chainloader buffers.
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@ -145,20 +145,20 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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if (type == TSEC_FW_TYPE_EMU)
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{
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// Init SMMU translation for TSEC.
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pdir = smmu_init_for_tsec();
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pdir = smmu_init_domain(MC_SMMU_TSEC_ASID);
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smmu_init();
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// Enable SMMU.
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smmu_enable();
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// Clock reset controller.
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car = page_alloc(1);
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car = smmu_page_zalloc(1);
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memcpy(car, (void *)CLOCK_BASE, SZ_PAGE);
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car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = 2;
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smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE);
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// Fuse driver.
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fuse = page_alloc(1);
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fuse = smmu_page_zalloc(1);
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memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, SZ_1K);
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fuse[0x82C / 4] = 0;
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fuse[0x9E0 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
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@ -166,34 +166,34 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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smmu_map(pdir, (FUSE_BASE - 0x800), (u32)fuse, 1, _READABLE | _NONSECURE);
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// Power management controller.
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pmc = page_alloc(1);
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pmc = smmu_page_zalloc(1);
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smmu_map(pdir, RTC_BASE, (u32)pmc, 1, _READABLE | _NONSECURE);
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// Flow control.
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flowctrl = page_alloc(1);
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flowctrl = smmu_page_zalloc(1);
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smmu_map(pdir, FLOW_CTLR_BASE, (u32)flowctrl, 1, _WRITABLE | _NONSECURE);
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// Security engine.
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se = page_alloc(1);
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se = smmu_page_zalloc(1);
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memcpy(se, (void *)SE_BASE, SZ_PAGE);
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smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE);
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// Memory controller.
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mc = page_alloc(1);
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mc = smmu_page_zalloc(1);
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memcpy(mc, (void *)MC_BASE, SZ_PAGE);
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mc[MC_IRAM_BOM / 4] = 0;
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mc[MC_IRAM_TOM / 4] = DRAM_START;
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smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE);
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// IRAM
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iram = page_alloc(0x30);
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iram = smmu_page_zalloc(0x30);
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memcpy(iram, tsec_ctxt->pkg1, 0x30000);
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// PKG1.1 magic offset.
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pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / 4));
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smmu_map(pdir, 0x40010000, (u32)iram, 0x30, _READABLE | _WRITABLE | _NONSECURE);
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// Exception vectors
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evec = page_alloc(1);
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evec = smmu_page_zalloc(1);
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smmu_map(pdir, EXCP_VEC_BASE, (u32)evec, 1, _READABLE | _WRITABLE | _NONSECURE);
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}
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@ -229,7 +229,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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if (kidx != 8)
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{
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res = -6;
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smmu_deinit_for_tsec();
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smmu_deinit_domain(MC_SMMU_TSEC_ASID);
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goto out_free;
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}
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@ -240,7 +240,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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memcpy(tsec_keys, &key, 0x20);
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memcpy(tsec_ctxt->pkg1, iram, 0x30000);
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smmu_deinit_for_tsec();
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smmu_deinit_domain(MC_SMMU_TSEC_ASID);
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// for (int i = 0; i < kidx; i++)
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// gfx_printf("key %08X\n", key[i]);
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@ -194,7 +194,7 @@ void irq_wait_event(u32 irq)
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_irq_enable_source(irq);
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// Halt BPMP and wait for the IRQ. No need to use WAIT_EVENT + LIC_IRQ when BPMP serves the IRQ.
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FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_STOP_UNTIL_IRQ;
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FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_STOP_UNTIL_IRQ;
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_irq_disable_source(irq);
|
||||
_irq_ack_source(irq);
|
||||
|
Loading…
Reference in New Issue
Block a user