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mirror of https://github.com/CTCaer/hekate.git synced 2024-12-27 21:19:20 +00:00
hekate/bdk/mem
CTCaer 9e41aa7759 bdk: smmu: refactor and update driver
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
2024-03-14 09:21:06 +02:00
..
emc.h sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
heap.c bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
heap.h bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
mc_t210.h bdk: smmu: refactor driver and allow other asid 2024-03-13 01:54:46 +02:00
mc.c bdk: mc: remove some redundant carveout cfg 2024-01-07 12:33:29 +02:00
mc.h bdk: mc: always on ahb arbitration 2022-01-29 01:29:02 +02:00
minerva.c bdk: sdram: adjust sdmmc1 la for l4t 2024-02-21 10:50:15 +02:00
minerva.h bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
mtc_table.h bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
sdram_config_t210b01.inl bdk: update copyright year 2024-01-07 12:38:10 +02:00
sdram_config.inl bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
sdram_param_t210.h
sdram_param_t210b01.h bdk: sdram: refactor patching offsets 2023-12-27 21:04:04 +02:00
sdram.c sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
sdram.h bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
smmu.c bdk: smmu: refactor and update driver 2024-03-14 09:21:06 +02:00
smmu.h bdk: smmu: refactor and update driver 2024-03-14 09:21:06 +02:00