CTCaer
547a3542ee
bdk: display: add more defines
2024-05-19 10:16:52 +03:00
CTCaer
4bc0a0591c
bdk: display: wait 2us for bl pwm config to take
...
Fixes the tiny blink showing up while pwm is still at max.
2024-05-19 10:15:52 +03:00
CTCaer
985c513770
bdk: hwinit: add arbiter config
2024-05-19 10:07:06 +03:00
CTCaer
16eb6a3c44
bdk: types: do not overflow on byte swaps
...
Addresses warning message.
2024-04-25 16:57:43 +03:00
CTCaer
856994e4f4
bdk: sprintf: add right padding support
2024-04-25 04:56:38 +03:00
CTCaer
ec2e62236a
bdk: pinmux: add i2s pin config
2024-04-25 04:52:13 +03:00
CTCaer
2648a2655c
bdk: sdram: add info about custom 8GB T210 config
...
That's a suggestion on which 4GB modules are certainly fine to use.
2024-04-25 04:50:07 +03:00
CTCaer
62153fdfbb
bdk: types: add likely/unlikely global macros
2024-04-25 04:48:09 +03:00
CTCaer
28960728f9
bdk: joycon: add bit numbers on the button struct
2024-04-25 04:46:27 +03:00
CTCaer
902ccede9a
bdk: joycon: use proper bits for batt levels
2024-04-25 04:45:50 +03:00
CTCaer
96efa7a002
bdk: vic: add support for P8 and R5G5B5
2024-04-25 04:44:22 +03:00
CTCaer
d92906db5e
bdk: display: correct some reg names and add more
2024-04-25 04:44:08 +03:00
CTCaer
e8d6516f43
bdk: display: use basic profile for OLED
...
That's the one with the accurate sRGB colors.
Anything else is over saturated.
2024-04-25 04:38:57 +03:00
CTCaer
a6727f6e32
bdk: display: update active regs on vsync for WinD
...
Doing that on hsync can cause issues on disable without actually syncing to it.
2024-04-25 04:38:04 +03:00
CTCaer
e846f4576e
bdk: minerva: l4t: adjust sdmmc1 la and freq table
...
- LA is tightened up
- Copied frequencies are now 204/408/800/1333/1600/OC (from 204/666/800/1600/OC)
2024-03-29 13:21:53 +02:00
CTCaer
42c02e97e8
bdk: display: add 6.2" panel clone
2024-03-29 13:21:53 +02:00
CTCaer
d687b53249
bdk: heap: add zalloc and utilize it
2024-03-27 09:00:53 +02:00
CTCaer
9e41aa7759
bdk: smmu: refactor and update driver
...
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
2024-03-14 09:21:06 +02:00
CTCaer
9ba7c44b89
bdk: clock: use real source clock dividers
...
Use CLK_SRC_DIV macro in order to have the actual divider showing.
2024-03-13 02:01:01 +02:00
CTCaer
9a520d63a6
bdk: smmu: refactor driver and allow other asid
2024-03-13 01:54:46 +02:00
CTCaer
20e661fc01
bdk: refactor flow control defines
2024-03-13 01:50:45 +02:00
CTCaer
3a4fa12f42
bdk: smmu: powergate ccplex after enabling smmu
2024-03-13 01:44:58 +02:00
CTCaer
fb31cb2926
bdk: ccplex: add no rst vector lock & powergating
...
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
2024-03-13 01:37:52 +02:00
CTCaer
f126486266
bdk: sdmmc: utilize block size defines
2024-03-12 15:47:14 +02:00
CTCaer
25b7ffecd1
bdk: fatfs: always align malloc to lba
2024-03-12 15:43:44 +02:00
CTCaer
7d1600b85c
bdk: consolidate ffsystem into bdk
2024-03-12 15:16:18 +02:00
CTCaer
83ac40c4b9
bdk: rtc: handle offset adjustment in-place
2024-03-12 15:08:55 +02:00
CTCaer
4131ff12d7
bdk: sdram: adjust sdmmc1 la for l4t
2024-02-21 10:50:15 +02:00
CTCaer
9ea847578e
bdk: display: add another oem clone
2024-02-21 10:40:46 +02:00
CTCaer
6d69ef3cf6
bdk: sprintf: allow padding > 9
2024-02-16 16:01:54 +02:00
CTCaer
f05563579e
bdk: max77620: raise sd1 max voltage
...
For T210.
2024-02-16 15:55:40 +02:00
CTCaer
644747230c
bdk: dram: add FPGA code for 3rd gen micron
2024-02-16 15:54:22 +02:00
CTCaer
1f30b8deb7
bdk: minerva: add custom option in table
2024-02-16 15:51:02 +02:00
CTCaer
bfc6069b2d
bdk: display: add OEM panel id
2024-02-14 00:08:06 +02:00
CTCaer
4576ed81ef
sdram: acquire per chip mrr info
2024-02-12 04:08:39 +02:00
CTCaer
b37430dc1d
bdk: update copyright year
2024-01-07 12:38:10 +02:00
CTCaer
75543875e2
bdk: mc: remove some redundant carveout cfg
2024-01-07 12:33:29 +02:00
CTCaer
30c320d6e7
bdk: sdram: update all ram info comments
2024-01-06 22:05:24 +02:00
CTCaer
eff27d92f2
bdk: sdram: update default wpr overrides
...
Since it's only used in L4T set them to the correct latest reg tool values.
HOS overrides them anyway.
2024-01-06 22:03:54 +02:00
CTCaer
3874840d77
bdk: sdram: update cfg for 8GB erista
2024-01-06 21:59:18 +02:00
CTCaer
74e252aaf2
bdk: sdram: update latest reg tool vpr overrides
...
Set them to default config and remove them from patching.
2024-01-06 21:58:51 +02:00
CTCaer
c7333e710c
bdk: strtol: support unsigned 32bit hex
...
If base is 16 and input is not negative allow unsigned 32bit parsing.
This allows parsing numbers of up to 4294967295 in that case.
2024-01-06 21:55:21 +02:00
CTCaer
dab5eb9aa0
bdk: sprintf: do not accept null chars
...
Skip NULL chars on putc since they break the resulted string.
2024-01-06 21:52:48 +02:00
CTCaer
92093ff08e
bdk: se: deduplicate sha hash extraction
2023-12-27 21:07:52 +02:00
CTCaer
2cc6cd45d9
bdk: dram: small refactor
2023-12-27 21:06:09 +02:00
CTCaer
a6ec41744b
bdk: sdram: refactor patching offsets
2023-12-27 21:04:04 +02:00
CTCaer
bb6e4deb4c
bdk: remove unused lp0 cfg from bdk
2023-12-27 21:02:33 +02:00
CTCaer
41d3565353
bdk: sdmmc: deduplicate function modes get
...
And parse the whole info
2023-12-27 15:01:20 +02:00
CTCaer
b584a3f53a
bdk: add several defines
2023-12-25 04:08:34 +02:00
CTCaer
7f98fb736a
bdk: hwinit: reorder sdmmc1 reg disable
2023-12-25 04:07:26 +02:00
