mirror of
https://github.com/bluekitchen/btstack.git
synced 2025-04-02 16:20:31 +00:00
360 lines
13 KiB
C
360 lines
13 KiB
C
#include <string.h>
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#include "esp_log.h"
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#include "driver/gpio.h"
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#include "es8388.h"
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#define ES8388_TAG "ES8388"
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#define ES_ASSERT(a, format, b, ...) \
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if ((a) != 0) { \
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ESP_LOGE(ES8388_TAG, format, ##__VA_ARGS__); \
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return b;\
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}
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#define LOG_8388(fmt, ...) ESP_LOGW(ES8388_TAG, fmt, ##__VA_ARGS__)
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static int es_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t data)
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{
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int res = 0;
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i2c_cmd_handle_t cmd = i2c_cmd_link_create();
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res |= i2c_master_start(cmd);
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res |= i2c_master_write_byte(cmd, slave_addr, 1 /*ACK_CHECK_EN*/);
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res |= i2c_master_write_byte(cmd, reg_addr, 1 /*ACK_CHECK_EN*/);
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res |= i2c_master_write_byte(cmd, data, 1 /*ACK_CHECK_EN*/);
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res |= i2c_master_stop(cmd);
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res |= i2c_master_cmd_begin(0, cmd, 1000 / portTICK_RATE_MS);
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i2c_cmd_link_delete(cmd);
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ES_ASSERT(res, "es8388_write_reg error", -1);
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return res;
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}
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static int es8388_read_reg(uint8_t reg_addr, uint8_t *pdata)
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{
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uint8_t data;
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int res = 0;
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i2c_cmd_handle_t cmd = i2c_cmd_link_create();
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res |= i2c_master_start(cmd);
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res |= i2c_master_write_byte(cmd, ES8388_ADDR, 1 /*ACK_CHECK_EN*/);
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res |= i2c_master_write_byte(cmd, reg_addr, 1 /*ACK_CHECK_EN*/);
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res |= i2c_master_stop(cmd);
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res |= i2c_master_cmd_begin(0, cmd, 1000 / portTICK_RATE_MS);
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i2c_cmd_link_delete(cmd);
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cmd = i2c_cmd_link_create();
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res |= i2c_master_start(cmd);
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res |= i2c_master_write_byte(cmd, ES8388_ADDR | 0x01, 1 /*ACK_CHECK_EN*/);
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res |= i2c_master_read_byte(cmd, &data, 0x01/*NACK_VAL*/);
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res |= i2c_master_stop(cmd);
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res |= i2c_master_cmd_begin(0, cmd, 1000 / portTICK_RATE_MS);
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i2c_cmd_link_delete(cmd);
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ES_ASSERT(res, "es8388_read_reg error", -1);
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*pdata = data;
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return res;
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}
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static int i2c_init(i2c_config_t *conf, int port)
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{
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int res;
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res = i2c_param_config(port, conf);
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res |= i2c_driver_install(port, conf->mode, 0, 0, 0);
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ES_ASSERT(res, "I2cInit error", -1);
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return res;
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}
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void es8388_read_all_regs()
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{
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for (int i = 0; i < 50; i++) {
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uint8_t reg = 0;
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es8388_read_reg(i, ®);
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ets_printf("%x: %x\n", i, reg);
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}
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}
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int es8388_write_reg(uint8_t regAdd, uint8_t data)
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{
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return es_write_reg(ES8388_ADDR, regAdd, data);
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}
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static int es8388_set_adc_dac_volume(int mode, int volume, int dot)
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{
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int res = 0;
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if ( volume < -96 || volume > 0 ) {
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LOG_8388("Warning: volume < -96! or > 0!\n");
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if (volume < -96)
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volume = -96;
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else
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volume = 0;
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}
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dot = (dot >= 5 ? 1 : 0);
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volume = (-volume << 1) + dot;
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if (mode == ES_MODULE_ADC || mode == ES_MODULE_ADC_DAC) {
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL8, volume);
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL9, volume); //ADC Right Volume=0db
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}
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if (mode == ES_MODULE_DAC || mode == ES_MODULE_ADC_DAC) {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL5, volume);
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL4, volume);
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}
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return res;
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}
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int es8388_start(es_codec_module_t mode)
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{
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int res = 0;
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uint8_t prev_data = 0, data = 0;
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es8388_read_reg(ES8388_DACCONTROL21, &prev_data);
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if (mode == ES_MODULE_LINE) {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL16, 0x09); // 0x00 audio on LIN1&RIN1, 0x09 LIN2&RIN2 by pass enable
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL17, 0x50); // left DAC to left mixer enable and LIN signal to left mixer enable 0db : bupass enable
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL20, 0x50); // right DAC to right mixer enable and LIN signal to right mixer enable 0db : bupass enable
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0xC0); //enable adc
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} else {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0x80); //enable dac
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}
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es8388_read_reg(ES8388_DACCONTROL21, &data);
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if (prev_data != data) {
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res |= es_write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0xF0); //start state machine
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// res |= es8388_write_reg(ES8388_ADDR, ES8388_CONTROL1, 0x16);
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// res |= es8388_write_reg(ES8388_ADDR, ES8388_CONTROL2, 0x50);
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res |= es_write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0x00); //start state machine
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}
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if (mode == ES_MODULE_ADC || mode == ES_MODULE_ADC_DAC || mode == ES_MODULE_LINE)
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0x00); //power up adc and line in
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//res |= es8388_set_adc_dac_volume(ES_MODULE_ADC, 0, 0); // 0db
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if (mode == ES_MODULE_DAC || mode == ES_MODULE_ADC_DAC || mode == ES_MODULE_LINE) {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACPOWER, 0x3c); //power up dac and line out
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res |= es8388_set_mute(false);
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//res |= es8388_set_adc_dac_volume(ES_MODULE_DAC, 0, 0); // 0db
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}
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return res;
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}
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int es8388_stop(es_codec_module_t mode)
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{
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int res = 0;
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if (mode == ES_MODULE_LINE) {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0x80); //enable dac
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL16, 0x00); // 0x00 audio on LIN1&RIN1, 0x09 LIN2&RIN2
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL17, 0x90); // only left DAC to left mixer enable 0db
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL20, 0x90); // only right DAC to right mixer enable 0db
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return res;
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}
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if (mode == ES_MODULE_DAC || mode == ES_MODULE_ADC_DAC) {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACPOWER, 0x00);
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res |= es8388_set_mute(true);
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//res |= es8388_set_adc_dac_volume(ES_MODULE_DAC, -96, 5); // 0db
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//res |= es8388_write_reg(ES8388_ADDR, ES8388_DACPOWER, 0xC0); //power down dac and line out
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}
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if (mode == ES_MODULE_ADC || mode == ES_MODULE_ADC_DAC) {
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//res |= es8388_set_adc_dac_volume(ES_MODULE_ADC, -96, 5); // 0db
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0xFF); //power down adc and line in
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}
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if (mode == ES_MODULE_ADC_DAC) {
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0x9C); //disable mclk
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// res |= es8388_write_reg(ES8388_ADDR, ES8388_CONTROL1, 0x00);
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// res |= es8388_write_reg(ES8388_ADDR, ES8388_CONTROL2, 0x58);
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// res |= es8388_write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0xF3); //stop state machine
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}
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return res;
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}
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int es8388_i2s_config_clock(es_codec_i2s_clock_t cfg)
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{
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int res = 0;
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res |= es_write_reg(ES8388_ADDR, ES8388_MASTERMODE, cfg.sclk_div);
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL5, cfg.lclk_div); //ADCFsMode,singel SPEED,RATIO=256
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL2, cfg.lclk_div); //ADCFsMode,singel SPEED,RATIO=256
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return res;
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}
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void es8388_uninit()
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{
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es_write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0xFF); //reset and stop es8388
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// i2c_driver_delete(cfg->i2c_port_num);
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}
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int es8388_init(es8388_config_t *cfg)
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{
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int res = 0;
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res = i2c_init(&cfg->i2c_cfg, cfg->i2c_port_num); // ESP32 in master mode
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL3, 0x04); // 0x04 mute/0x00 unmute&ramp;DAC unmute and disabled digital volume control soft ramp
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/* Chip Control and Power Management */
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res |= es_write_reg(ES8388_ADDR, ES8388_CONTROL2, 0x50);
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res |= es_write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0x00); //normal all and power up all
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res |= es_write_reg(ES8388_ADDR, ES8388_MASTERMODE, cfg->es_mode); //CODEC IN I2S SLAVE MODE
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/* dac */
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res |= es_write_reg(ES8388_ADDR, ES8388_DACPOWER, 0xC0); //disable DAC and disable Lout/Rout/1/2
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res |= es_write_reg(ES8388_ADDR, ES8388_CONTROL1, 0x12); //Enfr=0,Play&Record Mode,(0x17-both of mic&paly)
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// res |= es8388_write_reg(ES8388_ADDR, ES8388_CONTROL2, 0); //LPVrefBuf=0,Pdn_ana=0
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL1, 0x18);//1a 0x18:16bit iis , 0x00:24
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL2, 0x02); //DACFsMode,SINGLE SPEED; DACFsRatio,256
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL16, 0x00); // 0x00 audio on LIN1&RIN1, 0x09 LIN2&RIN2
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL17, 0x90); // only left DAC to left mixer enable 0db
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL20, 0x90); // only right DAC to right mixer enable 0db
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0x80); //set internal ADC and DAC use the same LRCK clock, ADC LRCK as internal LRCK
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL23, 0x00); //vroi=0
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res |= es8388_set_adc_dac_volume(ES_MODULE_DAC, 0, 0); // 0db
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res |= es_write_reg(ES8388_ADDR, ES8388_DACPOWER, cfg->dac_output); //0x3c Enable DAC and Enable Lout/Rout/1/2
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/* adc */
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0xFF);
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL1, 0x88); //0x88 MIC PGA =24DB
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL2, cfg->adc_input); //0x00 LINSEL & RINSEL, LIN1/RIN1 as ADC Input; DSSEL,use one DS Reg11; DSR, LINPUT1-RINPUT1
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL3, 0x02);
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL4, 0x0c); //0d 0x0c I2S-16BIT, LEFT ADC DATA = LIN1 , RIGHT ADC DATA =RIN1
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL5, 0x02); //ADCFsMode,singel SPEED,RATIO=256
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//ALC for Microphone
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res |= es8388_set_adc_dac_volume(ES_MODULE_ADC, 0, 0); // 0db
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0x09); //Power up ADC, Enable LIN&RIN, Power down MICBIAS, set int1lp to low power mode
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es8388_pa_power(true);
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ESP_LOGE(ES8388_TAG, "init, out:%02x, in:%02x", cfg->dac_output, cfg->adc_input);
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ESP_LOGE(ES8388_TAG, "res = %d", res);
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return res;
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}
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int es8388_config_fmt(es_codec_module_t mode, es_codec_i2s_fmt_t fmt)
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{
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int res = 0;
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uint8_t reg = 0;
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if (mode == ES_MODULE_ADC || mode == ES_MODULE_ADC_DAC) {
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res = es8388_read_reg(ES8388_ADCCONTROL4, ®);
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reg = reg & 0xfc;
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL4, reg | fmt);
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}
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if (mode == ES_MODULE_DAC || mode == ES_MODULE_ADC_DAC) {
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res = es8388_read_reg(ES8388_DACCONTROL1, ®);
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reg = reg & 0xf9;
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL1, reg | (fmt << 1));
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}
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return res;
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}
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int es8388_set_volume(int volume)
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{
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int res;
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if (volume < 0)
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volume = 0;
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else if (volume > 100)
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volume = 100;
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volume /= 3;
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res = es_write_reg(ES8388_ADDR, ES8388_DACCONTROL24, volume);
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL25, volume); //ADC Right Volume=0db
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL26, 0);
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL27, 0);
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return res;
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}
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int es8388_get_volume(int *volume)
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{
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int res;
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uint8_t reg = 0;
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res = es8388_read_reg(ES8388_DACCONTROL24, ®);
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if (res == ESP_FAIL) {
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*volume = 0;
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} else {
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*volume = reg;
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*volume *= 3;
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if (*volume == 99)
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*volume = 100;
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}
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return res;
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}
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int es8388_set_bits_per_sample(es_codec_module_t mode, es_codec_bits_len_t bitPerSample)
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{
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int res = 0;
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uint8_t reg = 0;
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int bits = (int)bitPerSample;
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if (mode == ES_MODULE_ADC || mode == ES_MODULE_ADC_DAC) {
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res = es8388_read_reg(ES8388_ADCCONTROL4, ®);
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reg = reg & 0xe3;
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL4, reg | (bits << 2));
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}
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if (mode == ES_MODULE_DAC || mode == ES_MODULE_ADC_DAC) {
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res = es8388_read_reg(ES8388_DACCONTROL1, ®);
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reg = reg & 0xc7;
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL1, reg | (bits << 3));
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}
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return res;
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}
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int es8388_set_mute(int enable)
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{
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int res;
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uint8_t reg = 0;
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res = es8388_read_reg(ES8388_DACCONTROL3, ®);
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reg = reg & 0xFB;
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res |= es_write_reg(ES8388_ADDR, ES8388_DACCONTROL3, reg | (((int)enable) << 2));
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return res;
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}
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int es8388_get_mute(int *mute)
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{
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int res = -1;
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uint8_t reg = 0;
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res = es8388_read_reg(ES8388_DACCONTROL3, ®);
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if (res == ESP_OK) {
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reg = (reg & 0x04) >> 2;
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}
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*mute = reg;
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return res;
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}
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int es8388_set_dac_ouput(int output)
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{
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int res;
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uint8_t reg = 0;
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res = es8388_read_reg(ES8388_DACPOWER, ®);
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reg = reg & 0xc3;
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res |= es_write_reg(ES8388_ADDR, ES8388_DACPOWER, reg | output);
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return res;
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}
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int es8388_set_adc_input(es_codec_adc_input_t input)
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{
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int res;
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uint8_t reg = 0;
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res = es8388_read_reg(ES8388_ADCCONTROL2, ®);
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reg = reg & 0x0f;
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res |= es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL2, reg | input);
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return res;
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}
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int es8388_set_mic_gain(es_codec_mic_gain_t gain)
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{
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int res, gain_n;
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gain_n = (int)gain / 3;
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res = es_write_reg(ES8388_ADDR, ES8388_ADCCONTROL1, gain_n); //MIC PGA
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return res;
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}
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void es8388_pa_power(bool enable)
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{
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gpio_config_t io_conf;
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memset(&io_conf, 0, sizeof(io_conf));
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io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
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io_conf.mode = GPIO_MODE_OUTPUT;
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io_conf.pin_bit_mask = 1UL << GPIO_NUM_21;
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io_conf.pull_down_en = 0;
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io_conf.pull_up_en = 0;
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gpio_config(&io_conf);
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if (enable) {
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gpio_set_level(GPIO_NUM_21, 1);
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} else {
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gpio_set_level(GPIO_NUM_21, 0);
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}
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}
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