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csr: don't enable parity for H5 with PS Keys. doesn't help, only breaks H5

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Matthias Ringwald 2017-04-07 12:13:09 +02:00
parent 834bce8cfd
commit ca93b47d3c
1 changed files with 0 additions and 3 deletions
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chipset/csr/btstack_chipset_csr.c
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@ -76,9 +76,6 @@ static const uint8_t init_script[] = {
// Enable RTS/CTS for BCSP (0806 -> 080e) // Enable RTS/CTS for BCSP (0806 -> 080e)
0x01, 0x00, 0xFC, 0x13, 0xc2, 0x02, 0x00, 0x09, 0x00, 0x01, 0x00, 0x03, 0x70, 0x00, 0x00, 0xbf, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0e, 0x08, 0x01, 0x00, 0xFC, 0x13, 0xc2, 0x02, 0x00, 0x09, 0x00, 0x01, 0x00, 0x03, 0x70, 0x00, 0x00, 0xbf, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0e, 0x08,
// Enable RTS/CTS for H5 (1806 -> 180e, even parity still on)
0x01, 0x00, 0xFC, 0x13, 0xc2, 0x02, 0x00, 0x09, 0x00, 0x01, 0x00, 0x03, 0x70, 0x00, 0x00, 0xc1, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0e, 0x18,
// Set UART baudrate to 115200 // Set UART baudrate to 115200
0x01, 0x00, 0xFC, 0x15, 0xc2, 0x02, 0x00, 0x0a, 0x00, 0x02, 0x00, 0x03, 0x70, 0x00, 0x00, 0xea, 0x01, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x00, 0xFC, 0x15, 0xc2, 0x02, 0x00, 0x0a, 0x00, 0x02, 0x00, 0x03, 0x70, 0x00, 0x00, 0xea, 0x01, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc2,