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msp432p401lp-cc256x: update driverlib to 3.40.01.02

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This commit is contained in:
Matthias Ringwald 2020-11-11 18:31:26 +01:00
parent 8ba100b5c3
commit 5fd0122a3e
114 changed files with 109793 additions and 16128 deletions
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474
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/cmsis_ccs.h → port/msp432p401lp-cc256x/CMSIS/cmsis_ccs.h
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@ -1,237 +1,237 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family CMSIS Definitions
//
//****************************************************************************
#ifndef CMSIS_CCS_H_
#define CMSIS_CCS_H_
//*****************************************************************************
// CMSIS-compatible instruction calls
//*****************************************************************************
#ifndef __cplusplus
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
__attribute__( ( always_inline ) ) static inline void __NOP(void)
{
__asm(" nop");
}
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
__asm(" wfi");
}
// Wait For Event
__attribute__( ( always_inline ) ) static inline void __wfe(void)
{
__asm(" wfe");
}
#endif
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
{
__asm(" cpsie i");
}
// Disable Interrupts
__attribute__( ( always_inline ) ) static inline void __disable_irq(void)
{
__asm(" cpsid i");
}
// Data Synchronization Barrier
__attribute__( ( always_inline ) ) static inline void __DSB(void)
{
__asm(" dsb");
}
#if (0)
// Get Main Stack Pointer
static inline uint32_t __get_MSP(void)
{
register uint32_t result;
//__asm (" mrs result, msp");
return(result);
}
// Set Main Stack Pointer
static inline void __set_MSP(uint32_t topOfMainStack)
{
asm(" .global topOfMainStack");
__asm (" msr msp, topOfMainStack");
}
// Get Priority Mask
static inline uint32_t __get_PRIMASK(void)
{
uint32_t result;
__asm (" mrs result, primask");
return(result);
}
// Set Priority Mask
static inline void __set_PRIMASK(uint32_t priMask)
{
__asm (" msr primask, priMask");
}
#endif
//
// v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __CLZ _norm
#define __SXTB _sxtb
#define __SXTH _sxth
#define __UXTB _uxtb
#define __UXTH _uxth
// CCS supports intrinsics to take advantage of the shift operand left/right
// before saturation extension of SSAT, but CMSIS does not take advantage
// of those, so tell the compiler to use a sat & shift left with a shift
// value of 0 whenever it encounters an SSAT
#define __SSAT(VAL, BITPOS) \
_ssatl(VAL , 0, BITPOS)
//
// Only define M4 based intrinsics if we're not using an M4
//
#if defined (__TI_TMS470_V7M4__)
//
// V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __QADD _sadd
#define __QDADD _sdadd
#define __QDSUB _sdsub
#define __SMLABB _smlabb
#define __SMLABT _smlabt
#define __SMLALBB _smlalbb
#define __SMLALBT _smlalbt
#define __SMLALTB _smlaltb
#define __SMLALTT _smlaltt
#define __SMLATB _smlatb
#define __SMLATT _smlatt
#define __SMLAWB _smlawb
#define __SMLAWT _smlawt
#define __SMULBB _smulbb
#define __SMULBT _smulbt
#define __SMULTB _smultb
#define __SMULTT _smultt
#define __SMULWB _smulwb
#define __SMULWT _smulwt
#define __QSUB _ssub
#define __SUBC _subc
//
// v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __SHASX _shaddsubx
#define __SHSAX _shsubaddx
#define __PKHBT _pkhbt
#define __PKHTB _pkhtb
#define __QADD16 _qadd16
#define __QADD8 _qadd8
#define __QSUB16 _qsub16
#define __QSUB8 _qsub8
#define __QASX _saddsubx
#define __QSAX _qsubaddx
#define __SADD16 _sadd16
#define __SADD8 _sadd8
#define __SASX _saddsubx
#define __SEL _sel
#define __SHADD16 _shadd16
#define __SHADD8 _shadd8
#define __SHSUB16 _shsub16
#define __SHSUB8 _shsub8
#define __SMLAD _smlad
#define __SMLADX _smladx
#define __SMLALD _smlald
#define __SMLALDX _smlaldx
#define __SMLSD _smlsd
#define __SMLSDX _smlsdx
#define __SMLSLD _smlsld
#define __SMLSLDX _smlsldx
#define __SMMLA _smmla
#define __SMMLAR _smmlar
#define __SMMLS _smmls
#define __SMMLSR _smmlsr
#define __SMMUL _smmul
#define __SMMULR _smmulr
#define __SMUAD _smuad
#define __SMUADX _smuadx
#define __SMUSD _smusd
#define __SMUSDX _smusdx
#define __SSAT16 _ssat16
#define __SSUB16 _ssub16
#define __SSUB8 _ssub8
#define __SSAX _ssubaddx
#define __SXTAB _sxtab
#define __SXTAB16 _sxtab16
#define __SXTAH _sxtah
#define __UMAAL _umaal
#define __UADD16 _uadd16
#define __UADD8 _uadd8
#define __UHADD16 _uhadd16
#define __UHADD8 _uhadd8
#define __UASX _uaddsubx
#define __UHSUB16 _uhsub16
#define __UHSUB8 _uhsub8
#define __UQADD16 _uqadd16
#define __UQADD8 _uqadd8
#define __UQASX _uqaddsubx
#define __UQSUB16 _uqsub16
#define __UQSUB8 _uqsub8
#define __UQSAX _uqsubaddx
#define __USAD8 _usad8
#define __USAT16 _usat16
#define __USUB16 _usub16
#define __USUB8 _usub8
#define __USAX _usubaddx
#define __UXTAB _uxtab
#define __UXTAB16 _uxtab16
#define __UXTAH _uxtah
#define __UXTB16 _uxtb16
#endif /*__TI_TMS470_V7M4__*/
#endif /*CMSIS_CCS_H_*/
//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family CMSIS Definitions
//
//****************************************************************************
#ifndef CMSIS_CCS_H_
#define CMSIS_CCS_H_
//*****************************************************************************
// CMSIS-compatible instruction calls
//*****************************************************************************
#ifndef __cplusplus
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
__attribute__( ( always_inline ) ) static inline void __NOP(void)
{
__asm(" nop");
}
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
__asm(" wfi");
}
// Wait For Event
__attribute__( ( always_inline ) ) static inline void __wfe(void)
{
__asm(" wfe");
}
#endif
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
{
__asm(" cpsie i");
}
// Disable Interrupts
__attribute__( ( always_inline ) ) static inline void __disable_irq(void)
{
__asm(" cpsid i");
}
// Data Synchronization Barrier
__attribute__( ( always_inline ) ) static inline void __DSB(void)
{
__asm(" dsb");
}
#if (0)
// Get Main Stack Pointer
static inline uint32_t __get_MSP(void)
{
register uint32_t result;
//__asm (" mrs result, msp");
return(result);
}
// Set Main Stack Pointer
static inline void __set_MSP(uint32_t topOfMainStack)
{
asm(" .global topOfMainStack");
__asm (" msr msp, topOfMainStack");
}
// Get Priority Mask
static inline uint32_t __get_PRIMASK(void)
{
uint32_t result;
__asm (" mrs result, primask");
return(result);
}
// Set Priority Mask
static inline void __set_PRIMASK(uint32_t priMask)
{
__asm (" msr primask, priMask");
}
#endif
//
// v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __CLZ _norm
#define __SXTB _sxtb
#define __SXTH _sxth
#define __UXTB _uxtb
#define __UXTH _uxth
// CCS supports intrinsics to take advantage of the shift operand left/right
// before saturation extension of SSAT, but CMSIS does not take advantage
// of those, so tell the compiler to use a sat & shift left with a shift
// value of 0 whenever it encounters an SSAT
#define __SSAT(VAL, BITPOS) \
_ssatl(VAL , 0, BITPOS)
//
// Only define M4 based intrinsics if we're not using an M4
//
#if defined (__TI_TMS470_V7M4__)
//
// V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __QADD _sadd
#define __QDADD _sdadd
#define __QDSUB _sdsub
#define __SMLABB _smlabb
#define __SMLABT _smlabt
#define __SMLALBB _smlalbb
#define __SMLALBT _smlalbt
#define __SMLALTB _smlaltb
#define __SMLALTT _smlaltt
#define __SMLATB _smlatb
#define __SMLATT _smlatt
#define __SMLAWB _smlawb
#define __SMLAWT _smlawt
#define __SMULBB _smulbb
#define __SMULBT _smulbt
#define __SMULTB _smultb
#define __SMULTT _smultt
#define __SMULWB _smulwb
#define __SMULWT _smulwt
#define __QSUB _ssub
#define __SUBC _subc
//
// v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __SHASX _shaddsubx
#define __SHSAX _shsubaddx
#define __PKHBT _pkhbt
#define __PKHTB _pkhtb
#define __QADD16 _qadd16
#define __QADD8 _qadd8
#define __QSUB16 _qsub16
#define __QSUB8 _qsub8
#define __QASX _saddsubx
#define __QSAX _qsubaddx
#define __SADD16 _sadd16
#define __SADD8 _sadd8
#define __SASX _saddsubx
#define __SEL _sel
#define __SHADD16 _shadd16
#define __SHADD8 _shadd8
#define __SHSUB16 _shsub16
#define __SHSUB8 _shsub8
#define __SMLAD _smlad
#define __SMLADX _smladx
#define __SMLALD _smlald
#define __SMLALDX _smlaldx
#define __SMLSD _smlsd
#define __SMLSDX _smlsdx
#define __SMLSLD _smlsld
#define __SMLSLDX _smlsldx
#define __SMMLA _smmla
#define __SMMLAR _smmlar
#define __SMMLS _smmls
#define __SMMLSR _smmlsr
#define __SMMUL _smmul
#define __SMMULR _smmulr
#define __SMUAD _smuad
#define __SMUADX _smuadx
#define __SMUSD _smusd
#define __SMUSDX _smusdx
#define __SSAT16 _ssat16
#define __SSUB16 _ssub16
#define __SSUB8 _ssub8
#define __SSAX _ssubaddx
#define __SXTAB _sxtab
#define __SXTAB16 _sxtab16
#define __SXTAH _sxtah
#define __UMAAL _umaal
#define __UADD16 _uadd16
#define __UADD8 _uadd8
#define __UHADD16 _uhadd16
#define __UHADD8 _uhadd8
#define __UASX _uaddsubx
#define __UHSUB16 _uhsub16
#define __UHSUB8 _uhsub8
#define __UQADD16 _uqadd16
#define __UQADD8 _uqadd8
#define __UQASX _uqaddsubx
#define __UQSUB16 _uqsub16
#define __UQSUB8 _uqsub8
#define __UQSAX _uqsubaddx
#define __USAD8 _usad8
#define __USAT16 _usat16
#define __USUB16 _usub16
#define __USUB8 _usub8
#define __USAX _usubaddx
#define __UXTAB _uxtab
#define __UXTAB16 _uxtab16
#define __UXTAH _uxtah
#define __UXTB16 _uxtb16
#endif /*__TI_TMS470_V7M4__*/
#endif /*CMSIS_CCS_H_*/

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port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/cmsis_gcc.h → port/msp432p401lp-cc256x/CMSIS/cmsis_gcc.h
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3858
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/core_cm4.h → port/msp432p401lp-cc256x/CMSIS/core_cm4.h
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port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/core_cm4_simd.h → port/msp432p401lp-cc256x/CMSIS/core_cm4_simd.h
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160
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/core_cmFunc.h → port/msp432p401lp-cc256x/CMSIS/core_cmFunc.h
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@ -1,80 +1,80 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

160
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/core_cmInstr.h → port/msp432p401lp-cc256x/CMSIS/core_cmInstr.h
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@ -1,80 +1,80 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

0
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/CMSIS/core_cmSimd.h → port/msp432p401lp-cc256x/CMSIS/core_cmSimd.h
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port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/driverlib.h
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@ -1,70 +0,0 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __DRIVERLIB__H_
#define __DRIVERLIB__H_
#include "adc14.h"
#include "aes256.h"
#include "comp_e.h"
#include "cpu.h"
#include "crc32.h"
#include "cs.h"
#include "dma.h"
#include "eusci.h"
#include "flash.h"
#include "fpu.h"
#include "gpio.h"
#include "i2c.h"
#include "interrupt.h"
#include "mpu.h"
#include "pcm.h"
#include "pmap.h"
#include "pss.h"
#include "ref_a.h"
#include "reset.h"
#include "rom.h"
#include "rom_map.h"
#include "rtc_c.h"
#include "spi.h"
#include "sysctl.h"
#include "systick.h"
#include "timer32.h"
#include "timer_a.h"
#include "uart.h"
#include "wdt_a.h"
#endif

87
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/hw_memmap.h
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@ -1,87 +0,0 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __HW_MEMMAP__
#define __HW_MEMMAP__
#define __DRIVERLIB_MSP432P4XX_FAMILY__
//*****************************************************************************
//
// Include device specific header file
//
//*****************************************************************************
//*****************************************************************************
//
// SUCCESS and FAILURE for API return value
//
//*****************************************************************************
#define STATUS_SUCCESS 0x01
#define STATUS_FAIL 0x00
//*****************************************************************************
//
// Macros for hardware access
//
//*****************************************************************************
#define HWREG8(x) (*((volatile uint8_t *)(x)))
#define HWREG16(x) (*((volatile uint16_t *)(x)))
#define HWREG32(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (HWREG16(x))
#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
/******************************************************************************
* Device memory map *
******************************************************************************/
#define __MAIN_MEMORY_START__ (0x00000000) /**< Main Flash memory start address */
#define __MAIN_MEMORY_END__ (0x0003FFFF) /**< Main Flash memory end address */
#define __BSL_MEMORY_START__ (0x00202000) /**< BSL memory start address */
#define __BSL_MEMORY_END__ (0x00203FFF) /**< BSL memory end address */
#define __SRAM_START__ (0x20000000) /**< SRAM memory start address */
#define __SRAM_END__ (0x2000FFFF) /**< SRAM memory end address */
/******************************************************************************
* Definitions for 8/16/32-bit wide bit band access *
******************************************************************************/
#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#endif // #ifndef __HW_MEMMAP__

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port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/rom.h
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190
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/inc/msp_compatibility.h
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@ -1,190 +0,0 @@
//*****************************************************************************
//
// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP430 intrinsic redefinitions for use with MSP432 Family Devices
//
//****************************************************************************
/******************************************************************************
* Definitions for 8/16/32-bit wide memory access *
******************************************************************************/
#define HWREG8(x) (*((volatile uint8_t *)(x)))
#define HWREG16(x) (*((volatile uint16_t *)(x)))
#define HWREG32(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (HWREG16(x))
#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
/******************************************************************************
* Definitions for 8/16/32-bit wide bit band access *
******************************************************************************/
#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
// Intrinsics with ARM equivalents
#if defined ( __TI_ARM__ ) /* TI CGT Compiler */
#include <cmsis_ccs.h>
#define __sleep() __wfi()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register(x) __set_MSP(x)
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() _enable_interrupts()
#define __enable_interrupts() _enable_interrupts()
#define __disable_interrupt() _disable_interrupts()
#define __disable_interrupts() _disable_interrupts()
#define __no_operation() __asm(" nop")
#elif defined ( __ICCARM__ ) /* IAR Compiler */
#include <stdint.h>
#define __INLINE inline
#include <cmsis_iar.h>
#define __sleep() __WFI()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register() __set_MSP()
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() __asm(" cpsie i")
#define __enable_interrupts() __asm(" cpsie i")
#define __disable_interrupt() __asm(" cpsid i")
#define __disable_interrupts() __asm(" cpsid i")
#define __no_operation() __asm(" nop")
// Intrinsics without ARM equivalents
#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#elif defined ( __CC_ARM ) /* ARM Compiler */
#define __sleep() __wfi
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register(x) __set_MSP(x)
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() __asm(" cpsie i")
#define __enable_interrupts() __asm(" cpsie i")
#define __disable_interrupt() __asm(" cpsid i")
#define __disable_interrupts() __asm(" cpsid i")
#define __no_operation() __asm(" nop")
// Intrinsics without ARM equivalents
#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#elif defined ( __GNUC__ ) /* GCC Compiler */
#undef __wfi
#define __wfi() asm(" wfi")
#define __sleep() __wfi()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register(x) __set_MSP(x)
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() __asm(" cpsie i")
#define __enable_interrupts() __asm(" cpsie i")
#define __disable_interrupt() __asm(" cpsid i")
#define __disable_interrupts() __asm(" cpsid i")
#define __no_operation() __asm(" nop")
// Intrinsics without ARM equivalents
#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#endif
// Intrinsics without ARM equivalents
#define __low_power_mode_0() { __sleep(); }
#define __low_power_mode_1() { __sleep(); }
#define __low_power_mode_2() { __sleep(); }
#define __low_power_mode_3() { __deep_sleep(); }
#define __low_power_mode_4() { __deep_sleep(); }
#define __data16_read_addr(x) (*((volatile uint32_t *)(x)))
#define __data20_read_char(x) (*((volatile uint8_t *)(x)))
#define __data20_read_short(x) (*((volatile uint16_t *)(x)))
#define __data20_read_long(x) (*((volatile uint32_t *)(x)))
#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) }
#define __get_SR_register() 0
#define __get_SR_register_on_exit() 0

12
port/msp432p401lp-cc256x/Makefile
View File

@ -6,7 +6,7 @@ PART=__MSP432P401R__
#
# The base directory for MSPWare.
#
ROOT=MSP432_DriverLib_3_10_00_09
ROOT=ti/devices/msp432p4xx/
#
# Include the common make definitions.
@ -16,10 +16,8 @@ include Makefile.defs
#
# Where to find header files that do not live in the source directory.
#
#IPATH=../../../..
IPATH+=${ROOT}/inc/
IPATH+=${ROOT}/inc/CMSIS/
IPATH+=${ROOT}/driverlib/MSP432P4xx
IPATH+=CMSIS
IPATH+=${ROOT}/driverlib
# BTstack
BTSTACK_ROOT=../..
@ -218,14 +216,12 @@ $(COMPILER)/%.jdebug: ozone.jdebug | $(COMPILER)
# pick up sources
OBJECTS = $(BTSTACK_SOURCES:%.c=$(COMPILER)/%.o) $(PORT_SOURCES:%.o=$(COMPILER)/%.o)
CFLAGSgcc=-DTARGET_IS_MSP432P4XX
LDFLAGS2 = ${CPU} ${FPU} -specs=nano.specs -lc -lm -lnosys -Wl,--gc-sections
# #
# # The rule for linking the application.
# #
${COMPILER}${SUFFIX}/%.elf: ${OBJECTS} ${COMPILER}/%.o ${ROOT}/driverlib/MSP432P4xx/${COMPILER}/msp432p4xx_driverlib.a
${COMPILER}${SUFFIX}/%.elf: ${OBJECTS} ${COMPILER}/%.o ti/devices/msp432p4xx/driverlib/${COMPILER}/msp432p4xx_driverlib.a
@ \
ldname="linker_script_gcc.ld"; \
if [ 'x${VERBOSE}' = x ]; \

16
port/msp432p401lp-cc256x/main.c
View File

@ -219,7 +219,7 @@ Pin 37: BTCTS=GPIO-P5.6
* at:
* http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html
*/
static eUSCI_UART_Config uartConfig =
static eUSCI_UART_ConfigV1 uartConfig =
{
EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
13, // BRDIV = 13
@ -229,10 +229,11 @@ static eUSCI_UART_Config uartConfig =
EUSCI_A_UART_LSB_FIRST, // MSB First
EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
EUSCI_A_UART_MODE, // UART mode
EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling
EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION, // Oversampling
EUSCI_A_UART_8_BIT_LEN, // 8 bit
};
// table
// table
static struct baudrate_config {
uint32_t baudrate;
uint8_t clock_prescalar;
@ -430,6 +431,7 @@ int hal_uart_dma_set_baud(uint32_t baud){
for (i=0;i<sizeof(baudrate_configs)/sizeof(struct baudrate_config);i++){
if (baudrate_configs[i].baudrate == baud){
index = i;
break;
}
}
if (index < 0) return -1;
@ -497,14 +499,6 @@ int main(void)
/* Halting the Watchdog */
MAP_WDT_A_holdTimer();
#if 1
/* Setting our MCLK to 48MHz - directly setting it in system_msp432p401r didn't work */
MAP_PCM_setCoreVoltageLevel(PCM_VCORE1);
FlashCtl_setWaitState(FLASH_BANK0, 2);
FlashCtl_setWaitState(FLASH_BANK1, 2);
MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
#endif
init_systick();
// start with BTstack init - especially configure HCI Transport

155
port/msp432p401lp-cc256x/system_msp432p401r.c
View File

@ -1,52 +1,16 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/**************************************************************************//**
/******************************************************************************
* @file system_msp432p401r.c
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
* MSP432P401R
* @version V1.00
* @date 20-Oct-2015
* @version 3.231
* @date 01/26/18
*
* @note View configuration instructions embedded in comments
*
******************************************************************************/
//*****************************************************************************
//
// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
// Copyright (C) 2015 - 2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@ -79,13 +43,13 @@
//*****************************************************************************
#include <stdint.h>
#include "msp.h"
#include <ti/devices/msp432p4xx/inc/msp.h>
/*--------------------- Configuration Instructions ----------------------------
1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
#define __HALT_WDT 1
2. Insert your desired CPU frequency in Hz at:
#define __SYSTEM_CLOCK 3000000
#define __SYSTEM_CLOCK 12000000
3. If you prefer the DC-DC power regulator (more efficient at higher
frequencies), set the __REGULATOR to 1:
#define __REGULATOR 1
@ -104,13 +68,13 @@
// <12000000> 12 MHz
// <24000000> 24 MHz
// <48000000> 48 MHz
#define __SYSTEM_CLOCK 24000000
#define __SYSTEM_CLOCK 48000000
/*--------------------- Power Regulator Configuration -----------------------*/
// Power Regulator Mode
// <0> LDO
// <1> DC-DC
#define __REGULATOR 1
#define __REGULATOR 0
/*----------------------------------------------------------------------------
Define clocks, used for SystemCoreClockUpdate()
@ -136,13 +100,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Cl
*/
void SystemCoreClockUpdate(void)
{
uint32_t source, divider;
uint8_t dividerValue;
float dcoConst;
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
uint32_t source = 0, divider = 0, dividerValue = 0, centeredFreq = 0, calVal = 0;
int16_t dcoTune = 0;
float dcoConst = 0.0;
divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
dividerValue = 1 << divider;
@ -194,7 +154,7 @@ void SystemCoreClockUpdate(void)
break;
case CS_CTL1_SELM__DCOCLK:
dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
case CS_CTL0_DCORSEL_0:
@ -231,13 +191,13 @@ void SystemCoreClockUpdate(void)
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
dcoConst = *((volatile const float *) &TLV->DCOER_CONSTK_RSEL04);
calVal = TLV->DCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
dcoConst = *((volatile const float *) &TLV->DCOIR_CONSTK_RSEL04);
calVal = TLV->DCOIR_FCAL_RSEL04;
}
@ -302,18 +262,18 @@ void SystemCoreClockUpdate(void)
void SystemInit(void)
{
// Enable FPU if used
#if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
(3UL << 11 * 2)); /* Set CP11 Full Access */
#if (__FPU_USED == 1) // __FPU_USED is defined in core_cm4.h
SCB->CPACR |= ((3UL << 10 * 2) | // Set CP10 Full Access
(3UL << 11 * 2)); // Set CP11 Full Access
#endif
#if (__HALT_WDT == 1)
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
#endif
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
@ -326,16 +286,17 @@ void SystemInit(void)
// No flash wait states necessary
// DCO = 1.5 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
@ -348,16 +309,17 @@ void SystemInit(void)
// No flash wait states necessary
// DCO = 3 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
@ -370,16 +332,17 @@ void SystemInit(void)
// No flash wait states necessary
// DCO = 12 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
@ -390,20 +353,21 @@ void SystemInit(void)
#endif
// 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
// DCO = 24 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
// Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
@ -416,19 +380,22 @@ void SystemInit(void)
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
// 1 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
// DCO = 48 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#endif
}

190
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/adc14.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/adc14.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -39,9 +34,9 @@
#include <stdbool.h>
/* DriverLib Includes */
#include <adc14.h>
#include <debug.h>
#include <interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/adc14.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
/* Statics */
static volatile uint32_t* const _ctlRegs[32] =
@ -330,26 +325,34 @@ bool repeatMode)
BITBAND_PERI(*(_ctlRegs[ii]), ADC14_MCTLN_EOS_OFS) = 0;
}
/* Setting Start/Stop locations */
BITBAND_PERI(
(*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
ADC14_MCTLN_EOS_OFS) = 1;
uint_fast8_t memEndIndex = _getIndexForMemRegister(memoryEnd);
if (memEndIndex != ADC_INVALID_MEM)
{
/* Setting Start/Stop locations */
BITBAND_PERI(
(*(_ctlRegs[memEndIndex])),
ADC14_MCTLN_EOS_OFS) = 1;
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryStart) << 16);
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryStart) << 16);
/* Setting multiple sample mode */
if (!repeatMode)
{
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_1);
} else
{
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_3);
}
/* Setting multiple sample mode */
if (!repeatMode)
{
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_1);
} else
{
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_3);
}
return true;
return true;
}
else
{
return false;
}
}
bool ADC14_configureSingleSampleMode(uint32_t memoryDestination,
@ -439,21 +442,28 @@ bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
memorySelect &= ~ii;
ii = ii << 1;
curReg = (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
if (differntialMode)
{
(*curReg) = ((*curReg)
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF))
| (channelSelect | refSelect | ADC14_MCTLN_DIF);
} else
{
(*curReg) = ((*curReg)
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF)) | (channelSelect | refSelect);
}
uint_fast8_t currRegIndex = _getIndexForMemRegister(currentReg);
if (currRegIndex != ADC_INVALID_MEM)
{
curReg = (uint32_t*) _ctlRegs[currRegIndex];
if (differntialMode)
{
(*curReg) = ((*curReg)
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF))
| (channelSelect | refSelect | ADC14_MCTLN_DIF);
} else
{
(*curReg) = ((*curReg)
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF)) | (channelSelect | refSelect);
}
}
else
{
return false;
}
}
return true;
@ -483,18 +493,26 @@ bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect)
memorySelect &= ~ii;
ii = ii << 1;
curRegPoint =
(uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
uint_fast8_t currRegIndex = _getIndexForMemRegister(currentReg);
if (currRegIndex != ADC_INVALID_MEM)
{
curRegPoint =
(uint32_t*) _ctlRegs[currRegIndex];
if (windowSelect == ADC_COMP_WINDOW0)
{
(*curRegPoint) = ((*curRegPoint)
& ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH))
| (ADC14_MCTLN_WINC);
} else if (windowSelect == ADC_COMP_WINDOW1)
{
(*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH;
}
if (windowSelect == ADC_COMP_WINDOW0)
{
(*curRegPoint) = ((*curRegPoint)
& ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH))
| (ADC14_MCTLN_WINC);
} else if (windowSelect == ADC_COMP_WINDOW1)
{
(*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH;
}
}
else
{
return false;
}
}
@ -536,7 +554,7 @@ bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high)
{
if (ADCIsConversionRunning())
return false;
if(BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS))
{
low = ((low << 2) | (0x8000 & low)) & 0xFFFC;
@ -583,31 +601,32 @@ bool ADC14_setResultFormat(uint32_t resultFormat)
uint_fast16_t ADC14_getResult(uint32_t memorySelect)
{
return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
+ 0x20));
uint_fast8_t memSelIndex = _getIndexForMemRegister(memorySelect);
if (memSelIndex != ADC_INVALID_MEM)
{
return *((uint16_t*) (_ctlRegs[memSelIndex]
+ 0x20));
}
else
{
return 0;
}
}
void ADC14_getMultiSequenceResult(uint16_t* res)
{
uint32_t *startAddr, *curAddr;
uint32_t ii;
startAddr = (uint32_t*) _ctlRegs[(ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK)
>> 16];
uint32_t startIndex, ii;
curAddr = startAddr;
startIndex = (ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK)>>16;
for (ii = 0; ii < 32; ii++)
for (ii = startIndex; ii < 32; ii++)
{
res[ii] = *(((uint16_t*) curAddr) + 0x40);
res[ii] = ADC14->MEM[ii];
if (BITBAND_PERI((*curAddr), ADC14_MCTLN_EOS_OFS))
if(ADC14->MCTL[ii] & ADC14_MCTLN_EOS)
break;
if (curAddr == _ctlRegs[31])
curAddr = (uint32_t*) _ctlRegs[0];
else
curAddr += 0x04;
}
}
@ -620,27 +639,34 @@ void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
bool foundEnd = false;
uint_fast8_t memStartIndex, memEndIndex;
memStartIndex = _getIndexForMemRegister(memoryStart);
memEndIndex = _getIndexForMemRegister(memoryEnd);
ASSERT(
_getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
&& _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
firstPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryStart)];
secondPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryEnd)];
if (memStartIndex != ADC_INVALID_MEM && memEndIndex!= ADC_INVALID_MEM) {
firstPoint = (uint32_t*) _ctlRegs[memStartIndex];
secondPoint = (uint32_t*) _ctlRegs[memEndIndex];
while (!foundEnd)
{
if (firstPoint == secondPoint)
{
foundEnd = true;
}
while (!foundEnd)
{
if (firstPoint == secondPoint)
{
foundEnd = true;
}
res[ii] = *(((uint16_t*) firstPoint) + 0x40);
res[ii] = *(((uint16_t*) firstPoint) + 0x40);
if (firstPoint == _ctlRegs[31])
firstPoint = (uint32_t*) _ctlRegs[0];
else
firstPoint += 0x04;
}
if (firstPoint == _ctlRegs[31])
firstPoint = (uint32_t*) _ctlRegs[0];
else
firstPoint += 0x04;
}
}
}
bool ADC14_enableReferenceBurst(void)

15
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/adc14.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/adc14.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,8 +52,8 @@ extern "C"
#endif
#include <stdint.h>
#include <msp.h>
#include <stdbool.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
@ -571,12 +566,12 @@ extern bool ADC14_isBusy(void);
//!
//! \param differntialMode selects if the channel selected by the
//! channelSelect will be configured in differential mode. If this
//! parameter is given for false, the configured channel will be paired
//! parameter is given as true, the configured channel will be paired
//! with its neighbor in differential mode. for example, if channel A0 or A1
//! is selected, the channel configured will be the difference between A0
//! and A1. If A2 or A3 are selected, the channel configured will be the
//! difference between A2 and A3 (and so on). Users can enter true or false,
//! or one ofl the following values:
//! or one of the following values:
//! - ADC_NONDIFFERENTIAL_INPUTS
//! - ADC_DIFFERENTIAL_INPUTS
//!

15
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/aes256.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/aes256.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,9 +29,9 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <aes256.h>
#include <interrupt.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/aes256.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint_fast16_t keyLength)

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/aes256.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/aes256.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +52,7 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/* Module Defines and macro for easy access */
#define AES256_CMSIS(x) ((AES256_Type *) x)

27
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/gcc/Makefile → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/ccs/Makefile
View File

@ -1,31 +1,28 @@
SDK_ROOT_INCLUDE = ../../../../../../
include $(SDK_ROOT_INCLUDE)/imports.mak
CC = $(GCC_ARMCOMPILER)/bin/arm-none-eabi-gcc
AR = $(GCC_ARMCOMPILER)/bin/arm-none-eabi-ar
MSP432LIB = msp432p4xx_driverlib.a
MSP432LIB = msp432p4xx_driverlib.lib
ARFLAGS=$(MSP432LIB)
CFLAGS=-mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mcpu=cortex-m4 -O4 -ffunction-sections -fdata-sections -MD -std=c99 -c
CFLAGS=-mv7M4 -mt --fp_mode=strict --gcc --endian=little --enum_type=packed \
--elf --sat_reassoc=off --fp_reassoc=off --gen_func_subsections=on --abi=eabi \
--code_state=16 --plain_char=unsigned -eo=.o -mf0 -O2 -oi0
CFLAGS+=-I$(SDK_ROOT_INCLUDE)/source/
CFLAGS+=-I$(SDK_ROOT_INCLUDE)/source/third_party/CMSIS/Include/
CFLAGS+=-I$(SDK_ROOT_INCLUDE)/source/ti/devices/msp432p4xx/inc/
CFLAGS+=-I$(GCC_ARMCOMPILER)/arm-none-eabi/include/
CFLAGS_401=$(CFLAGS) -D__MSP432P401R__
CFLAGS_4111=$(CFLAGS) -D__MSP432P4111__
CFLAGS+=-I$(CGTOOLS)/include/
OBJ = ../adc14.o ../aes256.o ../comp_e.o ../cpu.o ../crc32.o ../cs.o ../dma.o ../fpu.o \
../gpio.o ../i2c.o ../interrupt.o ../mpu.o ../pmap.o ../pcm.o ../pss.o ../ref_a.o ../reset.o ../rtc_c.o \
../spi.o ../systick.o ../timer_a.o ../timer32.o ../uart.o ../wdt_a.o
OBJ_401 = ../flash.o ../sysctl.o
OBJ_4111 = $(OBJ) ../flash_a.o ../sysctl_a.o ../lcd_f.o
CFLAGS_401=$(CFLAGS) -D__MSP432P401R__
CFLAGS_4111=$(CFLAGS) -D__MSP432P4111__
LINKOBJS = adc14.o aes256.o comp_e.o cpu.o crc32.o cs.o dma.o fpu.o gpio.o \
i2c.o interrupt.o mpu.o pmap.o pcm.o pss.o ref_a.o reset.o rtc_c.o flash.o \
sysctl.o sysctl_a.o flash_a.o lcd_f.o
.PHONY: all
all: $(MSP432LIB)
$(OBJ_401): %.o: %.c
@ -40,8 +37,6 @@ $(MSP432LIB): $(OBJ_401) $(OBJ_4111)
@echo " AR $(MSP432LIB)"
@$(AR) rs $(MSP432LIB) $(LINKOBJS) > /dev/null
.PHONY: clean
clean:
@rm -f *.o
@rm -f *.d
@rm -f $(MSP432LIB)
rm -f *.o
rm -f $(MSP432LIB)

BIN
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/ccs/msp432p4xx_driverlib.lib Normal file
View File

Binary file not shown.

65
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/ccs/msp432p4xx_driverlib.projectspec Normal file
View File

@ -0,0 +1,65 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectSpec>
<project
title="MSP432 DriverLib"
name="msp432_driverlib"
toolChain="TI"
products="com.ti.SIMPLELINK_MSP432_SDK"
device="Custom MSP432 Device"
outputType="staticLibrary"
ignoreDefaultDeviceSettings="true"
autoGenerateMakefiles="false"
buildCommand="${CCS_UTILS_DIR}/bin/gmake"
buildCommandFlags="CC=${CG_TOOL_CL} AR=${CG_TOOL_AR} SDK_ROOT_INCLUDE=${COM_TI_SIMPLELINK_MSP432_SDK_INSTALL_DIR} CGTOOLS=${CG_TOOL_ROOT} -k -j 4"
buildLocation="${COM_TI_SIMPLELINK_MSP432_SDK_INSTALL_DIR}/source/ti/devices/msp432p4xx/driverlib/ccs">
<file path="../adc14.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../aes256.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../comp_e.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../cpu.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../crc32.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../cs.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../dma.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../fpu.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../gpio.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../i2c.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../interrupt.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../mpu.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../pmap.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../pcm.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../pss.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../reset.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../rtc_c.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../flash.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../sysctl.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../sysctl_a.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../ref_a.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../flash_a.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
<file path="../lcd_f.c" openOnCreation="false" excludeFromBuild="false" action="link">
</file>
</project>
</projectSpec>

25
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/comp_e.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/comp_e.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,9 +29,9 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <comp_e.h>
#include <interrupt.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/comp_e.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
static uint16_t __getRegisterSettingForInput(uint32_t input)
{
@ -106,7 +101,7 @@ bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+ positiveTerminalInput;
+ positiveTerminalInput;
// Disable the input buffer
COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
@ -146,8 +141,8 @@ void COMP_E_setReferenceVoltage(uint32_t comparator,
{
ASSERT(supplyVoltageReferenceBase <= COMP_E_VREFBASE2_5V);
ASSERT(upperLimitSupplyVoltageFractionOf32 <= 32);
ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32); ASSERT(
upperLimitSupplyVoltageFractionOf32
ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32);
ASSERT(upperLimitSupplyVoltageFractionOf32
>= lowerLimitSupplyVoltageFractionOf32);
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_MRVS_OFS) = 0;
@ -271,9 +266,9 @@ void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
// Set the edge direction that will trigger an interrupt
if (COMP_E_RISINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1;
else if (COMP_E_FALLINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 0;
else if (COMP_E_FALLINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1;
}
void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)

21
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/comp_e.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/comp_e.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +52,7 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/* Module defines for Comp */
#define COMP_E_CMSIS(x) ((COMP_E_Type *) x)
@ -109,8 +104,8 @@ extern "C"
#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (COMP_E_INT_IIFG)
#define COMP_E_INTERRUPT_FLAG_READY (COMP_E_INT_RDYIFG)
#define COMP_E_FALLINGEDGE (!(COMP_E_CTL1_IES))
#define COMP_E_RISINGEDGE (COMP_E_CTL1_IES)
#define COMP_E_FALLINGEDGE (COMP_E_CTL1_IES)
#define COMP_E_RISINGEDGE (!(COMP_E_CTL1_IES))
#define COMP_E_LOW (0x0)
#define COMP_E_HIGH (COMP_E_CTL1_OUT)
@ -121,7 +116,7 @@ extern "C"
//! \brief Type definition for \link _COMP_E_Config \endlink structure
//!
//! \struct _COMP_E_Config
//! \brief Configuration structure for Comparator module. See
//! \brief Configuration structure for Comparator module. See
//! \link COMP_E_initModule \endlink for parameter documentation.
//
//*****************************************************************************
@ -241,10 +236,10 @@ extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config);
//! - \b COMP_E_VREFBASE2_5V
//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the
//! equation to generate the reference voltage for the upper limit
//! reference voltage. Valid values are between 0 and 32.
//! reference voltage. Valid values are between 1 and 32.
//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the
//! equation to generate the reference voltage for the lower limit
//! reference voltage. Valid values are between 0 and 32.
//! reference voltage. Valid values are between 1 and 32.
//! <br>Modified bits are \b CEREF0 of \b CECTL2 register.
//!
//! Use this function to generate a voltage to serve as a reference to the

13
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/cpu.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/cpu.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,8 +29,8 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <cpu.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/driverlib/cpu.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdint.h>
//*****************************************************************************

9
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/cpu.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/cpu.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

25
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/crc32.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/crc32.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,10 +29,10 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include "crc32.h"
#include <msp.h>
#include <debug.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/crc32.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
{
@ -59,7 +54,7 @@ void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType)
if (CRC16_MODE == crcType)
HWREG8(&(CRC32->DI16)) = dataIn;
else
HWREG8(&(CRC32->DI32)) = dataIn;
HWREG8(&(CRC32->DI32)) = dataIn;
}
void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
@ -89,7 +84,7 @@ void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType)
if (CRC16_MODE == crcType)
HWREG8(&(CRC32->DIRB16)) = dataIn;
else
HWREG8(&(CRC32->DIRB32)) = dataIn;
HWREG8(&(CRC32->DIRB32)) = dataIn;
}
void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
@ -124,7 +119,7 @@ uint32_t CRC32_getResult(uint_fast8_t crcType)
{
result = CRC32->INIRES32_HI;
result = (result << 16);
result |= CRC32->INIRES32_LO;
result |= (uint32_t) CRC32->INIRES32_LO;
return (result);
}
}
@ -140,7 +135,7 @@ uint32_t CRC32_getResultReversed(uint_fast8_t crcType)
{
result = CRC32->RESR32_HI;
result = (result << 16);
result |= CRC32->RESR32_LO;
result |= (uint32_t) CRC32->RESR32_LO;
return (result);
}
}

9
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/crc32.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/crc32.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

180
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/cs.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/cs.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,10 +33,15 @@
#include <stdint.h>
/* DriverLib Includes */
#include <cs.h>
#include <debug.h>
#include <sysctl.h>
#include <interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/cs.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#ifdef __MCU_HAS_SYSCTL_A__
#include <ti/devices/msp432p4xx/driverlib/sysctl_a.h>
#else
#include <ti/devices/msp432p4xx/driverlib/sysctl.h>
#endif
/* Statics */
static uint32_t hfxtFreq;
@ -74,7 +74,7 @@ static uint32_t _CSGetHFXTFrequency()
else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ)
return CS_CTL2_HFXTFREQ_5;
else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ)
return CS_CTL2_HFXTFREQ_5;
return CS_CTL2_HFXTFREQ_6;
else
{
ASSERT(false);
@ -347,8 +347,13 @@ bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
#ifdef __MCU_HAS_SYSCTL_A__
bNMIStatus = SysCtl_A_getNMISourceStatus() & SYSCTL_A_CS_SRC;
SysCtl_A_disableNMISource(SYSCTL_A_CS_SRC);
#else
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
SysCtl_disableNMISource(SYSCTL_CS_SRC);
#endif
/* Determining which frequency range to use */
wHFFreqRange = _CSGetHFXTFrequency();
@ -375,7 +380,7 @@ bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_HFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!bypassMode)
{
@ -389,9 +394,13 @@ bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
#ifdef __MCU_HAS_SYSCTL_A__
SysCtl_A_enableNMISource(bNMIStatus);
#else
SysCtl_enableNMISource(bNMIStatus);
if(boolTimeout && timeout == 0)
#endif
if (boolTimeout && timeout == 0)
return false;
return true;
@ -418,8 +427,13 @@ bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
#ifdef __MCU_HAS_SYSCTL_A__
bNMIStatus = SysCtl_A_getNMISourceStatus() & SYSCTL_A_CS_SRC;
SysCtl_A_disableNMISource(SYSCTL_A_CS_SRC);
#else
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
SysCtl_disableNMISource(SYSCTL_CS_SRC);
#endif
boolBypassMode = (xtDrive == CS_LFXT_BYPASS) ? true : false;
boolTimeout = (timeout == 0) ? false : true;
@ -454,9 +468,13 @@ bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
#ifdef __MCU_HAS_SYSCTL_A__
SysCtl_A_enableNMISource(bNMIStatus);
#else
SysCtl_enableNMISource(bNMIStatus);
if(boolTimeout && timeout == 0)
#endif
if (boolTimeout && timeout == 0)
return false;
return true;
@ -518,30 +536,29 @@ void CS_enableDCOExternalResistor(void)
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_setDCOExternalResistorCalibration(uint_fast8_t calData,
uint_fast8_t freqRange)
void CS_setDCOExternalResistorCalibration(uint_fast8_t calData,
uint_fast8_t freqRange)
{
uint_fast8_t rselVal;
/* Unlocking the module */
CS->KEY = CS_KEY;
rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK)>>CS_CTL0_DCORSEL_OFS;
rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK) >> CS_CTL0_DCORSEL_OFS;
CS->CTL0 &= ~CS_CTL0_DCORSEL_MASK;
if( (freqRange == CS_OVER32MHZ) && ( TLV->HWREV > DEVICE_PG1_1))
if ((freqRange == CS_OVER32MHZ))
{
CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK;
CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK;
CS->DCOERCAL1 |= (calData);
}
else
} else
{
CS->DCOERCAL0 &= ~CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK;
CS->DCOERCAL0 |= (calData)<<CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS;
CS->DCOERCAL0 |= (calData) << CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS;
}
CS->CTL0 |= (rselVal)<<CS_CTL0_DCORSEL_OFS;
CS->CTL0 |= (rselVal) << CS_CTL0_DCORSEL_OFS;
/* Locking the module */
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
@ -585,23 +602,19 @@ void CS_tuneDCOFrequency(int16_t tuneParameter)
uint16_t dcoTuneMask = 0x1FFF;
uint16_t dcoTuneSigned = 0x1000;
if (TLV->HWREV > DEVICE_PG1_1) {
dcoTuneMask = 0x3FF;
dcoTuneSigned = 0x200;
}
dcoTuneMask = 0x3FF;
dcoTuneSigned = 0x200;
if (tuneParameter < 0)
{
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
& dcoTuneMask) | dcoTuneSigned);
}
else
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter & dcoTuneMask)
| dcoTuneSigned);
} else
{
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
& dcoTuneMask));
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter & dcoTuneMask));
}
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
uint32_t CS_getDCOFrequency(void)
@ -611,44 +624,40 @@ uint32_t CS_getDCOFrequency(void)
uint32_t centeredFreq;
int16_t dcoTune;
uint_fast8_t tlvLength;
SysCtl_CSCalTLV_Info *csInfo;
uint32_t retVal;
#ifdef __MCU_HAS_SYSCTL_A__
SysCtl_A_CSCalTLV_Info *csInfo;
/* Parsing the TLV and getting the trim information */
SysCtl_A_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo);
#else
SysCtl_CSCalTLV_Info *csInfo;
/* Parsing the TLV and getting the trim information */
SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo);
#endif
centeredFreq = _CSGetDOCFrequency();
/* Parsing the TLV and getting the maximum erase pulses */
SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**)&csInfo);
if(tlvLength == 0)
if (tlvLength == 0)
{
return centeredFreq;
}
/* Checking to see if we need to do signed conversion */
if ( TLV->HWREV > DEVICE_PG1_1)
dcoTune = CS->CTL0 & 0x3FF;
if (dcoTune & 0x200)
{
dcoTune = CS->CTL0 & 0x3FF;
if (dcoTune & 0x200)
{
dcoTune = dcoTune | 0xFE00;
}
dcoTune = dcoTune | 0xFE00;
}
else
{
dcoTune = CS->CTL0 & 0x1FFF;
if (dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
}
if (dcoTune == 0)
return (uint32_t) centeredFreq;
/* DCORSEL = 5 */
if ((centeredFreq == 48000000) && ( TLV->HWREV > DEVICE_PG1_1))
if ((centeredFreq == 48000000))
{
/* External Resistor */
/* External Resistor */
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
@ -677,19 +686,9 @@ uint32_t CS_getDCOFrequency(void)
calVal = csInfo->rDCOIR_FCAL_RSEL04;
}
}
retVal = (uint32_t) ((centeredFreq)
/ (1 - ((dcoConst * dcoTune) / ((1 + dcoConst * (768 - calVal))))));
if( TLV->HWREV > DEVICE_PG1_1 )
{
retVal = (uint32_t) (centeredFreq)
/ (1 - ((dcoConst * dcoTune)
/ ((1 + dcoConst * (768 - calVal)))));
}
else
{
retVal = (uint32_t) (centeredFreq)
/ (1 - ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal)))));
}
return retVal;
}
@ -701,7 +700,19 @@ void CS_setDCOFrequency(uint32_t dcoFrequency)
bool rsel5 = false;
dcoSigned = (int32_t) dcoFrequency;
uint_fast8_t tlvLength;
SysCtl_CSCalTLV_Info *csInfo;
#ifdef __MCU_HAS_SYSCTL_A__
SysCtl_A_CSCalTLV_Info *csInfo;
/* Parsing the TLV and getting the trim information */
SysCtl_A_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo);
#else
SysCtl_CSCalTLV_Info *csInfo;
/* Parsing the TLV and getting the trim information */
SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo);
#endif
if (dcoFrequency < 2000000)
{
@ -733,17 +744,14 @@ void CS_setDCOFrequency(uint32_t dcoFrequency)
ASSERT(false);
return;
}
/* Parsing the TLV and getting the maximum erase pulses */
SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**)&csInfo);
if(dcoFrequency == nomFreq || tlvLength == 0)
if (dcoFrequency == nomFreq || tlvLength == 0)
{
CS_tuneDCOFrequency(0);
return;
CS_tuneDCOFrequency(0);
return;
}
if ((rsel5) && ( TLV->HWREV > DEVICE_PG1_1))
if (rsel5)
{
/* External Resistor*/
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
@ -775,14 +783,8 @@ void CS_setDCOFrequency(uint32_t dcoFrequency)
}
}
if ( TLV->HWREV > DEVICE_PG1_1)
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0f + dcoConst * (768.0f - calVal)))
/ (dcoSigned * dcoConst));
else
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0f + dcoConst * (768.0f - calVal)) * 8.0f)
/ (dcoSigned * dcoConst));
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0f + dcoConst * (768.0f - calVal))) / (dcoSigned * dcoConst));
CS_tuneDCOFrequency(dcoTune);

21
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/cs.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/cs.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +52,7 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
@ -110,8 +105,6 @@ extern "C"
#define CS_STARTCOUNT_HFXT_FAULT CS_IE_FCNTHFIE
#define CS_DCO_SHORT_FAULT CS_IFG_DCOR_SHTIFG
//#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
//#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
#define CS_HFXT_DRIVE CS_CTL2_HFXTDRIVE
#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
@ -160,8 +153,6 @@ extern "C"
#define CS_OVER32MHZ 0x01
#define CS_UNDER32MHZ 0x02
#define DEVICE_PG1_1 0x42
//******************************************************************************
//
//! This function sets the external clock sources LFXT and HFXT crystal
@ -185,7 +176,7 @@ extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
//! that this function is called for each clock signal. If not, the default
//! state is assumed for the particular clock signal. Refer to DriverLib
//! documentation for CS module or Device Family User's Guide for details of
//! default clock signal states.
//! default clock signal states.
//!
//! Note that this function is blocking and will wait on the appropriate bit
//! to be set in the CSSTAT READY register to be set before setting the clock
@ -489,7 +480,7 @@ extern void CS_setDCOFrequency(uint32_t dcoFrequency);
//!
//! \note This function is not currently available on pre-release MSP432 devices.
//! On early release versions of MSP432, the DCO calibration information has not been
//! populated making the DCO only able to operate at the pre-calibrated centered
//! populated making the DCO only able to operate at the pre-calibrated centered
//! frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
//! function. While this function will be added on the final devices being released,
//! for early silicon please default to the pre-calibrated DCO center frequencies.
@ -565,7 +556,7 @@ extern uint32_t CS_getDCOFrequency(void);
//!
//! \note This function is not currently available on pre-release MSP432 devices.
//! On early release versions of MSP432, the DCO calibration information has not been
//! populated making the DCO only able to operate at the pre-calibrated centered
//! populated making the DCO only able to operate at the pre-calibrated centered
//! frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
//! function. While this function will be added on the final devices being released,
//! for early silicon please default to the pre-calibrated DCO center frequencies.

9
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/debug.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/debug.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

105
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/dma.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/dma.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -36,24 +31,34 @@
* --/COPYRIGHT--*/
#include <stdint.h>
#include <debug.h>
#include <interrupt.h>
#include <dma.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/dma.h>
void DMA_enableModule(void)
{
//
// Set the master enable bit in the config register.
//
DMA_Control->CFG = DMA_CFG_MASTEN;
DMA_Control->CFG = DMA_CFG_MASTEN;
}
void DMA_disableModule(void)
{
uint32_t i;
//
// Clear the master enable bit in the config register.
//
DMA_Control->CFG = 0;
DMA_Control->CFG = 0;
//
// Clear all source configuration registers
//
i = DMA_Channel->DEVICE_CFG & 0xff;
while (i--) {
DMA_Channel->CH_SRCCFG[i] = 0;
}
}
uint32_t DMA_getErrorStatus(void)
@ -69,7 +74,7 @@ void DMA_clearErrorStatus(void)
//
// Clear the DMA error interrupt.
//
DMA_Control->ERRCLR = 1;
DMA_Control->ERRCLR = 1;
}
void DMA_enableChannel(uint32_t channelNum)
@ -141,7 +146,7 @@ void* DMA_getControlAlternateBase(void)
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA_Control->ATLBASE);
return ((void *) DMA_Control->ALTBASE);
}
void DMA_requestChannel(uint32_t channelNum)
@ -181,7 +186,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA_Control->USEBURSTSET = 1 << channelNum;
DMA_Control->USEBURSTSET = 1 << channelNum;
}
//
@ -190,7 +195,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA_Control->ALTSET = 1 << channelNum;
DMA_Control->ALTSET = 1 << channelNum;
}
//
@ -198,7 +203,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA_Control->PRIOSET = 1 << channelNum;
DMA_Control->PRIOSET = 1 << channelNum;
}
//
@ -206,7 +211,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA_Control->REQMASKSET = 1 << channelNum;
DMA_Control->REQMASKSET = 1 << channelNum;
}
}
@ -234,7 +239,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA_Control->USEBURSTCLR = 1 << channelNum;
DMA_Control->USEBURSTCLR = 1 << channelNum;
}
//
@ -243,7 +248,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA_Control->ALTCLR = 1 << channelNum;
DMA_Control->ALTCLR = 1 << channelNum;
}
//
@ -251,7 +256,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA_Control->PRIOCLR = 1 << channelNum;
DMA_Control->PRIOCLR = 1 << channelNum;
}
//
@ -259,7 +264,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA_Control->REQMASKCLR = 1 << channelNum;
DMA_Control->REQMASKCLR = 1 << channelNum;
}
}
@ -415,8 +420,8 @@ void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
if (increment != UDMA_SRC_INC_NONE)
{
increment = increment >> 26;
bufferBytes = transferSize << increment;
srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes - 1);
bufferBytes = (transferSize - 1) << increment;
srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes);
}
//
@ -455,8 +460,8 @@ void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
else
{
increment = increment >> 30;
bufferBytes = transferSize << increment;
dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes - 1);
bufferBytes = (transferSize - 1) << increment;
dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes);
}
}
@ -649,7 +654,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH0_EUSCIB1TX3:
case DMA_CH0_TIMERA0CCR0:
case DMA_CH0_AESTRIGGER0:
DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F;
break;
case DMA_CH1_RESERVED0:
case DMA_CH1_EUSCIA0RX:
@ -659,7 +664,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH1_EUSCIB1RX3:
case DMA_CH1_TIMERA0CCR2:
case DMA_CH1_AESTRIGGER1:
DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F;
break;
case DMA_CH2_RESERVED0:
case DMA_CH2_EUSCIA1TX:
@ -669,7 +674,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH2_EUSCIB2TX3:
case DMA_CH2_TIMERA1CCR0:
case DMA_CH2_AESTRIGGER2:
DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F;
break;
case DMA_CH3_RESERVED0:
case DMA_CH3_EUSCIA1RX:
@ -679,7 +684,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH3_EUSCIB2RX3:
case DMA_CH3_TIMERA1CCR2:
case DMA_CH3_RESERVED1:
DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F;
break;
case DMA_CH4_RESERVED0:
case DMA_CH4_EUSCIA2TX:
@ -689,7 +694,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH4_EUSCIB3TX3:
case DMA_CH4_TIMERA2CCR0:
case DMA_CH4_RESERVED1:
DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F;
break;
case DMA_CH5_RESERVED0:
case DMA_CH5_EUSCIA2RX:
@ -699,7 +704,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH5_EUSCIB3RX3:
case DMA_CH5_TIMERA2CCR2:
case DMA_CH5_RESERVED1:
DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F;
break;
case DMA_CH6_RESERVED0:
case DMA_CH6_EUSCIA3TX:
@ -709,7 +714,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH6_EUSCIB0TX3:
case DMA_CH6_TIMERA3CCR0:
case DMA_CH6_EXTERNALPIN:
DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F;
break;
case DMA_CH7_RESERVED0:
case DMA_CH7_EUSCIA3RX:
@ -719,7 +724,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH7_EUSCIB0RX3:
case DMA_CH7_TIMERA3CCR2:
case DMA_CH7_ADC14:
DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F;
break;
default:
ASSERT(false);
@ -735,16 +740,16 @@ void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
if (interruptNumber == DMA_INT1)
{
DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT2)
{
DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT3)
{
DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
}
/* Enabling the assigned interrupt */
@ -753,7 +758,7 @@ void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
void DMA_requestSoftwareTransfer(uint32_t channel)
{
DMA_Channel->SW_CHTRIG |= (1 << channel);
DMA_Channel->SW_CHTRIG |= (1 << channel);
}
uint32_t DMA_getInterruptStatus(void)
@ -763,25 +768,25 @@ uint32_t DMA_getInterruptStatus(void)
void DMA_clearInterruptFlag(uint32_t channel)
{
DMA_Channel->INT0_CLRFLG |= (1 << channel);
DMA_Channel->INT0_CLRFLG |= (1 << channel);
}
void DMA_enableInterrupt(uint32_t interruptNumber)
{
ASSERT(
(interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
(interruptNumber == DMA_INT1)
|| (interruptNumber == DMA_INT2)
|| (interruptNumber == DMA_INT3));
if (interruptNumber == DMA_INT1)
{
DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN;
DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN;
DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN;
DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN;
}
}
@ -789,19 +794,19 @@ void DMA_enableInterrupt(uint32_t interruptNumber)
void DMA_disableInterrupt(uint32_t interruptNumber)
{
ASSERT(
(interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
(interruptNumber == DMA_INT1)
|| (interruptNumber == DMA_INT2)
|| (interruptNumber == DMA_INT3));
if (interruptNumber == DMA_INT1)
{
DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN;
DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN;
DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN;
DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN;
}
}

42
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/dma.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/dma.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -56,7 +51,8 @@ extern "C"
#endif
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
//*****************************************************************************
//
@ -167,11 +163,11 @@ typedef struct _DMA_ControlTable
mode) \
{ \
(((srcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(srcAddr) : \
((void *)(&((uint8_t *)(srcAddr))[((transferCount) << \
((srcIncrement) >> 26)) - 1]))), \
((void *)(&((uint8_t *)(srcAddr))[((transferCount - 1) << \
((srcIncrement) >> 26))]))), \
(((dstIncrement) == UDMA_DST_INC_NONE) ? (void *)(dstAddr) : \
((void *)(&((uint8_t *)(dstAddr))[((transferCount) << \
((dstIncrement) >> 30)) - 1]))), \
((void *)(&((uint8_t *)(dstAddr))[((transferCount - 1) << \
((dstIncrement) >> 30))]))), \
(srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) | \
(((transferCount) - 1) << 4) | \
((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
@ -431,10 +427,6 @@ extern void DMA_clearErrorStatus(void);
//!
//! \param channelNum is the channel number to enable.
//!
//! This function enables a specific DMA channel for use. This function must
//! be used to enable a channel before it can be used to perform a DMA
//! transfer.
//!
//! When a DMA transfer is completed, the channel is automatically disabled by
//! the DMA controller. Therefore, this function should be called prior to
//! starting up any new transfer.
@ -868,11 +860,9 @@ extern void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel);
//! \param interruptNumber identifies which DMA interrupt is to be enabled.
//! This interrupt should be one of the following:
//!
//! - \b DMA_INT0 the master DMA interrupt handler
//! - \b DMA_INT1 the first configurable DMA interrupt handler
//! - \b DMA_INT2 the second configurable DMA interrupt handler
//! - \b DMA_INT3 the third configurable DMA interrupt handler
//! - \b DMA_INTERR the third configurable DMA interrupt handler
//!
//!
//! \return None.
@ -887,11 +877,9 @@ extern void DMA_enableInterrupt(uint32_t interruptNumber);
//! \param interruptNumber identifies which DMA interrupt is to be disabled.
//! This interrupt should be one of the following:
//!
//! - \b DMA_INT0 the master DMA interrupt handler
//! - \b DMA_INT1 the first configurable DMA interrupt handler
//! - \b DMA_INT2 the second configurable DMA interrupt handler
//! - \b DMA_INT3 the third configurable DMA interrupt handler
//! - \b DMA_INTERR the third configurable DMA interrupt handler
//!
//! Note for interrupts that are associated with a specific DMA channel
//! (DMA_INT1 - DMA_INT3), this function will also enable that specific
@ -933,13 +921,13 @@ extern uint32_t DMA_getInterruptStatus(void);
//! This function is used to clear the interrupt status of the DMA controller.
//! Note that only interrupts that weren't assigned to DMA interrupts one
//! through three using the DMA_assignInterrupt function will be affected by
//! thisfunctions. For other DMA interrupts, only one channel can be associated
//! and therefore clearing in unnecessary.
//! this function. For other DMA interrupts, only one channel can be associated
//! and therefore clearing is unnecessary.
//!
//! \return None
//
//*****************************************************************************
extern void DMA_clearInterruptFlag(uint32_t intChannel);
extern void DMA_clearInterruptFlag(uint32_t channel);
//*****************************************************************************
//
@ -957,7 +945,7 @@ extern void DMA_clearInterruptFlag(uint32_t intChannel);
//! - \b DMA_INT1 the first configurable DMA interrupt handler
//! - \b DMA_INT2 the second configurable DMA interrupt handler
//! - \b DMA_INT3 the third configurable DMA interrupt handler
//! - \b DMA_INTERR the third configurable DMA interrupt handler
//! - \b DMA_INTERR the DMA error interrupt handler
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
@ -965,7 +953,7 @@ extern void DMA_clearInterruptFlag(uint32_t intChannel);
//! \return None.
//
//*****************************************************************************
extern void DMA_registerInterrupt(uint32_t intChannel,
extern void DMA_registerInterrupt(uint32_t interruptNumber,
void (*intHandler)(void));
//*****************************************************************************
@ -979,7 +967,7 @@ extern void DMA_registerInterrupt(uint32_t intChannel,
//! \b the parameters as documented for the function
//! DMA_registerInterrupt().
//!
//! Note fore interrupts that are associated with a specific DMA channel
//! Note for interrupts that are associated with a specific DMA channel
//! (DMA_INT1 - DMA_INT3), this function will also disable that specific
//! channel for interrupts.
//!
@ -989,7 +977,7 @@ extern void DMA_registerInterrupt(uint32_t intChannel,
//! \return None.
//
//*****************************************************************************
extern void DMA_unregisterInterrupt(uint32_t intChannel);
extern void DMA_unregisterInterrupt(uint32_t interruptNumber);
//*****************************************************************************
//

96
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/driverlib.h Normal file
View File

@ -0,0 +1,96 @@
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __DRIVERLIB__H_
#define __DRIVERLIB__H_
/* Common Modules */
#include <ti/devices/msp432p4xx/driverlib/adc14.h>
#include <ti/devices/msp432p4xx/driverlib/aes256.h>
#include <ti/devices/msp432p4xx/driverlib/comp_e.h>
#include <ti/devices/msp432p4xx/driverlib/cpu.h>
#include <ti/devices/msp432p4xx/driverlib/crc32.h>
#include <ti/devices/msp432p4xx/driverlib/cs.h>
#include <ti/devices/msp432p4xx/driverlib/dma.h>
#include <ti/devices/msp432p4xx/driverlib/eusci.h>
#include <ti/devices/msp432p4xx/driverlib/fpu.h>
#include <ti/devices/msp432p4xx/driverlib/gpio.h>
#include <ti/devices/msp432p4xx/driverlib/i2c.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/mpu.h>
#include <ti/devices/msp432p4xx/driverlib/pcm.h>
#include <ti/devices/msp432p4xx/driverlib/pmap.h>
#include <ti/devices/msp432p4xx/driverlib/pss.h>
#include <ti/devices/msp432p4xx/driverlib/ref_a.h>
#include <ti/devices/msp432p4xx/driverlib/reset.h>
#include <ti/devices/msp432p4xx/driverlib/rom.h>
#include <ti/devices/msp432p4xx/driverlib/rom_map.h>
#include <ti/devices/msp432p4xx/driverlib/rtc_c.h>
#include <ti/devices/msp432p4xx/driverlib/spi.h>
#include <ti/devices/msp432p4xx/driverlib/systick.h>
#include <ti/devices/msp432p4xx/driverlib/timer32.h>
#include <ti/devices/msp432p4xx/driverlib/timer_a.h>
#include <ti/devices/msp432p4xx/driverlib/uart.h>
#include <ti/devices/msp432p4xx/driverlib/wdt_a.h>
/* Device specific modules */
#if defined(__MCU_HAS_SYSCTL_A__)
#include <ti/devices/msp432p4xx/driverlib/sysctl_a.h>
#endif
#if defined(__MCU_HAS_SYSCTL__)
#include <ti/devices/msp432p4xx/driverlib/sysctl.h>
#endif
#if defined(__MCU_HAS_FLCTL_A__)
#include <ti/devices/msp432p4xx/driverlib/flash_a.h>
#endif
#if defined(__MCU_HAS_FLCTL__)
#include <ti/devices/msp432p4xx/driverlib/flash.h>
#endif
#if defined(__MCU_HAS_LCD_F__)
#include <ti/devices/msp432p4xx/driverlib/lcd_f.h>
#endif
/* Offset Definitions */
#define HWREG8(x) (*((volatile uint8_t *)(x)))
#define HWREG16(x) (*((volatile uint16_t *)(x)))
#define HWREG32(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (HWREG16(x))
#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
#endif

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/eusci.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/eusci.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,7 +32,7 @@
#ifndef EUSCI_H_
#define EUSCI_H_
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x)
#define EUSCI_B_CMSIS(x) ((EUSCI_B_Type *) x)

89
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/flash.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/flash.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,14 +33,15 @@
#include <stdint.h>
/* DriverLib Includes */
#include <flash.h>
#include <debug.h>
#include <interrupt.h>
#include <msp.h>
#include <cpu.h>
#include <rom.h>
#include <sysctl.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/flash.h>
#include <ti/devices/msp432p4xx/driverlib/sysctl.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/cpu.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
/* Define to ensure that our current MSP432 has the FLCTL module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_FLCTL__
static const uint32_t MAX_ERASE_NO_TLV = 50;
static const uint32_t MAX_PROGRAM_NO_TLV = 5;
@ -139,8 +135,8 @@ static uint32_t getUserFlashSector(uint32_t addr)
}
}
void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
uint32_t *bankNum)
void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *bankNum,
uint32_t *sectorNum)
{
uint32_t bankLimit;
@ -148,14 +144,14 @@ void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
if (addr > bankLimit)
{
*(sectorNum) = FLASH_BANK1;
*(bankNum) = FLASH_BANK1;
addr = (addr - bankLimit);
} else
{
*(sectorNum) = FLASH_BANK0;
*(bankNum) = FLASH_BANK0;
}
*(bankNum) = (addr - __MAIN_MEMORY_START__) / 4096;
*(sectorNum) = (addr) / 4096;
}
static bool _FlashCtl_Program8(uint32_t src, uint32_t dest, uint32_t mTries)
@ -301,7 +297,7 @@ static bool _FlashCtl_ProgramBurst(uint32_t src, uint32_t dest, uint32_t length,
}
/* Setting/clearing INFO flash flags as appropriate */
if (dest > __MAIN_MEMORY_END__)
if (dest > SysCtl_getFlashSize())
{
FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
& ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_1;
@ -310,7 +306,7 @@ static bool _FlashCtl_ProgramBurst(uint32_t src, uint32_t dest, uint32_t length,
{
FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
& ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_0;
otpOffset = __MAIN_MEMORY_START__;
otpOffset = 0;
}
bCalc = 0;
@ -493,11 +489,11 @@ bool FlashCtl_protectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
FLCTL->BANK1_MAIN_WEPROT |= sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sectorMask <= 0x04);
ASSERT(sectorMask <= 0x03);
FLCTL->BANK0_INFO_WEPROT |= sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sectorMask <= 0x04);
ASSERT(sectorMask <= 0x03);
FLCTL->BANK1_INFO_WEPROT |= sectorMask;
break;
@ -549,7 +545,7 @@ bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
/* Casting and determining the memory that we need to use */
addr = (uint32_t) verifyAddr;
memoryType =
(addr > __MAIN_MEMORY_END__) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
(addr > SysCtl_getFlashSize()) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
/* Assuming Failure */
res = false;
@ -625,7 +621,7 @@ bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
if (length > 63)
{
/* Setting/clearing INFO flash flags as appropriate */
if (addr > __MAIN_MEMORY_END__)
if (addr > SysCtl_getFlashSize())
{
FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT
& ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK)
@ -636,7 +632,7 @@ bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT
& ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK)
| FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0;
otpOffset = __MAIN_MEMORY_START__;
otpOffset = 0;
}
/* Clearing any lingering fault flags and preparing burst verify*/
@ -722,15 +718,15 @@ bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode)
{
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL
& ~FLCTL_BANK0_RDCTL_RD_MODE_MASK) | readMode;
while ((FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_MASK)
!= readMode)
while ((FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK)
!= (readMode<<16))
;
} else if (flashBank == FLASH_BANK1)
{
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL
& ~FLCTL_BANK1_RDCTL_RD_MODE_MASK) | readMode;
while ((FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_MASK)
!= readMode)
while ((FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK)
!= (readMode<<16))
;
} else
{
@ -745,10 +741,10 @@ uint32_t FlashCtl_getReadMode(uint32_t flashBank)
{
if (flashBank == FLASH_BANK0)
{
return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_MASK);
return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK) >> 16;
} else if (flashBank == FLASH_BANK1)
{
return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_MASK);
return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK) >> 16;
} else
{
ASSERT(false);
@ -802,7 +798,7 @@ bool FlashCtl_performMassErase(void)
/* Changing to erase verify */
userFlash = SysCtl_getFlashSize() / 2;
for (ii = __MAIN_MEMORY_START__; ii < userFlash; ii += 4096)
for (ii = 0; ii < userFlash; ii += 4096)
{
sector = getUserFlashSector(ii);
@ -877,12 +873,12 @@ bool FlashCtl_eraseSector(uint32_t addr)
*/
intStatus = CPU_primask();
Interrupt_disableMaster();
/* Assuming Failure */
res = false;
memoryType =
addr > __MAIN_MEMORY_END__ ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
addr > SysCtl_getFlashSize() ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
/* Parsing the TLV and getting the maximum erase pulses */
SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo);
@ -912,7 +908,7 @@ bool FlashCtl_eraseSector(uint32_t addr)
} else
{
otpOffset = __MAIN_MEMORY_START__;
otpOffset = 0;
FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
& ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0;
}
@ -957,7 +953,7 @@ bool FlashCtl_eraseSector(uint32_t addr)
SectorEraseCleanup:
BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
if(intStatus == 0)
Interrupt_enableMaster();
@ -970,7 +966,7 @@ void FlashCtl_initiateSectorErase(uint32_t addr)
uint32_t otpOffset = 0;
memoryType =
addr > __MAIN_MEMORY_END__ ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
addr > SysCtl_getFlashSize() ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
/* We can only erase on 4KB boundaries */
while (addr & 0xFFF)
@ -989,7 +985,7 @@ void FlashCtl_initiateSectorErase(uint32_t addr)
} else
{
otpOffset = __MAIN_MEMORY_START__;
otpOffset = 0;
FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
& ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0;
}
@ -1487,9 +1483,9 @@ void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size)
size = (size / 4);
for (ii = 0; ii < size; ii++)
{
HWREG32(__getBurstProgramRegs[ii]) |=
~(HWREG32(__getBurstProgramRegs[ii])
| HWREG32(addr));
uint32_t temp1 = HWREG32(__getBurstProgramRegs[ii]);
uint32_t temp2 = HWREG32(addr);
HWREG32(__getBurstProgramRegs[ii]) |= ~(temp1 | temp2);
addr += 4;
}
@ -1551,8 +1547,9 @@ void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size)
size = (size / 4);
for (ii = 0; ii < size; ii++)
{
HWREG32(__getBurstProgramRegs[ii]) = ~(~(HWREG32(
__getBurstProgramRegs[ii])) & HWREG32(addr));
uint32_t temp1 = (HWREG32(__getBurstProgramRegs[ii]));
uint32_t temp2 = HWREG32(addr);
HWREG32(__getBurstProgramRegs[ii]) = ~(~temp1 & temp2);
addr += 4;
}
@ -1567,3 +1564,5 @@ void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size)
FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
}
}
#endif /* __MCU_HAS_FLCTL__ */

49
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/flash.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/flash.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,6 +32,13 @@
#ifndef __FLASH_H__
#define __FLASH_H__
#include <stdbool.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/* Define to ensure that our current MSP432 has the FLCTL module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_FLCTL__
//*****************************************************************************
//
//! \addtogroup flash_api
@ -55,9 +57,6 @@ extern "C"
{
#endif
#include <msp.h>
#include <stdbool.h>
//*****************************************************************************
//
// Control specific variables
@ -158,17 +157,17 @@ extern "C"
//*****************************************************************************
//
//! Calculates the flash bank and sector number given an address. Stores the
//! Calculates the flash bank and sector number given an address. Stores the
//! results into the two pointers given as parameters. The user must provide
//! a valid memory address (an address in SRAM for example will give an invalid
//! result).
//!
//! \param addr Address to calculate the bank/sector information for
//!
//! \param sectorNum The sector number will be stored in here after the function
//! \param bankNum The bank number will be stored in here after the function
//! completes.
//!
//! \param sectorNum The bank number will be stored in here after the function
//! \param sectorNum The sector number will be stored in here after the function
//! completes.
//!
//! \note For simplicity, this API only works with address in MAIN flash memory.
@ -178,8 +177,8 @@ extern "C"
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
uint32_t *bankNum);
extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *bankNum,
uint32_t *sectorNum);
//*****************************************************************************
//
@ -274,7 +273,7 @@ extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection disabled false otherwise.
@ -336,7 +335,7 @@ extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace,
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection enabled false otherwise.
@ -397,7 +396,7 @@ extern bool FlashCtl_protectSector(uint_fast8_t memorySpace,
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection enabled false otherwise.
@ -433,7 +432,7 @@ extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace,
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot verify a memory adress in the same flash bank that it
//! function cannot verify a memory address in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
@ -459,7 +458,7 @@ extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! function cannot erase a memory address in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
@ -476,7 +475,7 @@ extern bool FlashCtl_performMassErase(void);
//! Initiates a mass erase and returns control back to the program. This is a
//! non-blocking function, however it is the user's responsibility to perform
//! the necessary verification requirements after the interrupt is set to
//! signify completion.
//! signify completion.
//!
//! \return None
//
@ -501,7 +500,7 @@ extern void FlashCtl_initiateMassErase(void);
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! function cannot erase a memory addressin the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
@ -536,7 +535,7 @@ extern bool FlashCtl_eraseSector(uint32_t addr);
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot program a memory adress in the same flash bank that it
//! function cannot program a memory addressin the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
@ -893,7 +892,7 @@ extern void FlashCtl_unregisterInterrupt(void);
//*****************************************************************************
//
//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
//! function simply initaites the sector erase, but does no verification
//! which is required by the flash controller. The user must manually set
//! and enable interrupts on the flash controller to fire on erase completion
@ -940,4 +939,6 @@ extern void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size);
//
//*****************************************************************************
#endif /* __MCU_HAS_FLCTL__ */
#endif // __FLASH_H__

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/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __FLASH_A_H__
#define __FLASH_A_H__
#include <stdbool.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/* Define to ensure that our current MSP432 has the FLCTL_A module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_FLCTL_A__
//*****************************************************************************
//
//! \addtogroup flash_a_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define FLASH_A_BURST_PRG_BIT 0x03
#define FLASH_A_SECTOR_SIZE 4096
/* Interrupts */
#define FLASH_A_PROGRAM_ERROR FLCTL_A_IFG_PRG_ERR
#define FLASH_A_BENCHMARK_INT FLCTL_A_IFG_BMRK
#define FLASH_A_ERASE_COMPLETE FLCTL_A_IFG_ERASE
#define FLASH_A_BRSTPRGM_COMPLETE FLCTL_A_IFG_PRGB
#define FLASH_A_WRDPRGM_COMPLETE FLCTL_A_IFG_PRG
#define FLASH_A_POSTVERIFY_FAILED FLCTL_A_IFG_AVPST
#define FLASH_A_PREVERIFY_FAILED FLCTL_A_IFG_AVPRE
#define FLASH_A_BRSTRDCMP_COMPLETE FLCTL_A_IFG_RDBRST
#define FLASH_A_NORMAL_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_0
#define FLASH_A_MARGIN0_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_1
#define FLASH_A_MARGIN1_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_2
#define FLASH_A_PROGRAM_VERIFY_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_3
#define FLASH_A_ERASE_VERIFY_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_4
#define FLASH_A_LEAKAGE_VERIFY_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_5
#define FLASH_A_MARGIN0B_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_9
#define FLASH_A_MARGIN1B_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_10
#define FLASH_A_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7
#define FLASH_A_BANK0 0x00
#define FLASH_A_BANK1 0x01
#define FLASH_A_DATA_READ 0x00
#define FLASH_A_INSTRUCTION_FETCH 0x01
#define FLASH_A_MAIN_MEMORY_SPACE_BANK0 0x01
#define FLASH_A_MAIN_MEMORY_SPACE_BANK1 0x02
#define FLASH_A_INFO_MEMORY_SPACE_BANK0 0x03
#define FLASH_A_INFO_MEMORY_SPACE_BANK1 0x04
#define FLASH_A_MAIN_SPACE FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0
#define FLASH_A_INFO_SPACE FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1
#define FLASH_A_1_PATTERN FLCTL_A_RDBRST_CTLSTAT_DATA_CMP
#define FLASH_A_0_PATTERN 0x00
#define FLASH_A_SECTOR0 FLCTL_A_BANK0_MAIN_WEPROT_PROT0
#define FLASH_A_SECTOR1 FLCTL_A_BANK0_MAIN_WEPROT_PROT1
#define FLASH_A_SECTOR2 FLCTL_A_BANK0_MAIN_WEPROT_PROT2
#define FLASH_A_SECTOR3 FLCTL_A_BANK0_MAIN_WEPROT_PROT3
#define FLASH_A_SECTOR4 FLCTL_A_BANK0_MAIN_WEPROT_PROT4
#define FLASH_A_SECTOR5 FLCTL_A_BANK0_MAIN_WEPROT_PROT5
#define FLASH_A_SECTOR6 FLCTL_A_BANK0_MAIN_WEPROT_PROT6
#define FLASH_A_SECTOR7 FLCTL_A_BANK0_MAIN_WEPROT_PROT7
#define FLASH_A_SECTOR8 FLCTL_A_BANK0_MAIN_WEPROT_PROT8
#define FLASH_A_SECTOR9 FLCTL_A_BANK0_MAIN_WEPROT_PROT9
#define FLASH_A_SECTOR10 FLCTL_A_BANK0_MAIN_WEPROT_PROT10
#define FLASH_A_SECTOR11 FLCTL_A_BANK0_MAIN_WEPROT_PROT11
#define FLASH_A_SECTOR12 FLCTL_A_BANK0_MAIN_WEPROT_PROT12
#define FLASH_A_SECTOR13 FLCTL_A_BANK0_MAIN_WEPROT_PROT13
#define FLASH_A_SECTOR14 FLCTL_A_BANK0_MAIN_WEPROT_PROT14
#define FLASH_A_SECTOR15 FLCTL_A_BANK0_MAIN_WEPROT_PROT15
#define FLASH_A_SECTOR16 FLCTL_A_BANK0_MAIN_WEPROT_PROT16
#define FLASH_A_SECTOR17 FLCTL_A_BANK0_MAIN_WEPROT_PROT17
#define FLASH_A_SECTOR18 FLCTL_A_BANK0_MAIN_WEPROT_PROT18
#define FLASH_A_SECTOR19 FLCTL_A_BANK0_MAIN_WEPROT_PROT19
#define FLASH_A_SECTOR20 FLCTL_A_BANK0_MAIN_WEPROT_PROT20
#define FLASH_A_SECTOR21 FLCTL_A_BANK0_MAIN_WEPROT_PROT21
#define FLASH_A_SECTOR22 FLCTL_A_BANK0_MAIN_WEPROT_PROT22
#define FLASH_A_SECTOR23 FLCTL_A_BANK0_MAIN_WEPROT_PROT23
#define FLASH_A_SECTOR24 FLCTL_A_BANK0_MAIN_WEPROT_PROT24
#define FLASH_A_SECTOR25 FLCTL_A_BANK0_MAIN_WEPROT_PROT25
#define FLASH_A_SECTOR26 FLCTL_A_BANK0_MAIN_WEPROT_PROT26
#define FLASH_A_SECTOR27 FLCTL_A_BANK0_MAIN_WEPROT_PROT27
#define FLASH_A_SECTOR28 FLCTL_A_BANK0_MAIN_WEPROT_PROT28
#define FLASH_A_SECTOR29 FLCTL_A_BANK0_MAIN_WEPROT_PROT29
#define FLASH_A_SECTOR30 FLCTL_A_BANK0_MAIN_WEPROT_PROT30
#define FLASH_A_SECTOR31 FLCTL_A_BANK0_MAIN_WEPROT_PROT31
#define FLASH_A_NOVER 0
#define FLASH_A_BURSTPOST FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST
#define FLASH_A_BURSTPRE FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE
#define FLASH_A_REGPRE FLCTL_A_PRG_CTLSTAT_VER_PRE
#define FLASH_A_REGPOST FLCTL_A_PRG_CTLSTAT_VER_PST
#define FLASH_A_FULLVER (FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST | \
FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_A_PRG_CTLSTAT_VER_PRE \
| FLCTL_A_PRG_CTLSTAT_VER_PST)
#define FLASH_A_COLLATED_WRITE_MODE 0x01
#define FLASH_A_IMMEDIATE_WRITE_MODE 0x02
/* Internal parameters/definitions */
#define __INFO_FLASH_A_TECH_START__ 0x00200000
#define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000
typedef struct __sFlashCtl_ProtectionRegister
{
uint32_t B0_MAIN_R0;
uint32_t B0_MAIN_R1;
uint32_t B0_MAIN_R2;
uint32_t B0_MAIN_R3;
uint32_t B0_MAIN_R4;
uint32_t B0_MAIN_R5;
uint32_t B0_MAIN_R6;
uint32_t B0_MAIN_R7;
uint32_t B1_MAIN_R0;
uint32_t B1_MAIN_R1;
uint32_t B1_MAIN_R2;
uint32_t B1_MAIN_R3;
uint32_t B1_MAIN_R4;
uint32_t B1_MAIN_R5;
uint32_t B1_MAIN_R6;
uint32_t B1_MAIN_R7;
uint32_t B0_INFO_R0;
uint32_t B1_INFO_R0;
} __FlashCtl_ProtectionRegister;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Calculates the flash bank and sector number given an address. Stores the
//! results into the two pointers given as parameters. The user must provide
//! a valid memory address (an address in SRAM for example will give an invalid
//! result).
//!
//! \param addr Address to calculate the bank/sector information for
//!
//! \param bankNum The bank number will be stored in here after the function
//! completes.
//!
//! \param sectorNum The sector number will be stored in here after the function
//! completes.
//!
//! \note For simplicity, this API only works with address in MAIN flash memory.
//! For calculating the sector/bank number of an address in info memory,
//! please refer to your device datasheet/
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_getMemoryInfo(uint32_t addr, uint32_t *bankNum,
uint32_t *sectorNum);
//*****************************************************************************
//
//! Enables read buffering on accesses to a specified bank of flash memory
//!
//! \param memoryBank is the value of the memory bank to enable read
//! buffering. Must be only one of the following values:
//! - \b FLASH_A_BANK0,
//! - \b FLASH_A_BANK1
//!
//! \param accessMethod is the value of the access type to enable read
//! buffering. Must be only one of the following values:
//! - \b FLASH_A_DATA_READ,
//! - \b FLASH_A_INSTRUCTION_FETCH
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_enableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod);
//*****************************************************************************
//
//! Disables read buffering on accesses to a specified bank of flash memory
//!
//! \param memoryBank is the value of the memory bank to disable read
//! buffering. Must be only one of the following values:
//! - \b FLASH_A_BANK0,
//! - \b FLASH_A_BANK1
//!
//! \param accessMethod is the value of the access type to disable read
//! buffering. Must ne only one of the following values:
//! - \b FLASH_A_DATA_READ,
//! - \b FLASH_A_INSTRUCTION_FETCH
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_disableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod);
//*****************************************************************************
//
//! Enables protection on the given flash memory range from writes. Note that
//! this function only works on flash memory and giving in an address to ROM
//! or SRAM will result in unreliable behavior.
//!
//! \param startAddr is the start address of the memory to protect
//!
//! \param endAddr is the end address of the memory to protect
//!
//! \note Flash memory is organized by protection by sector sizes. This means
//! that you will only be able to protect/unprotect memory based off
//! 4096 aligned boundaries.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_A_protectMemory(uint32_t startAddr, uint32_t endAddr);
//*****************************************************************************
//
//! Disables protection on the given flash memory range from writes. Note that
//! this function only works on flash memory and giving in an address to ROM
//! or SRAM will result in unreliable behavior.
//!
//! \param startAddr is the start address of the memory to unprotect
//!
//! \param endAddr is the end address of the memory to unprotect
//!
//! \note Flash memory is organized by protection by sector sizes. This means
//! that you will only be able to protect/unprotect memory based off
//! 4096 aligned boundaries.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_A_unprotectMemory(uint32_t startAddr, uint32_t endAddr);
//*****************************************************************************
//
//! Scans over the given memory range and returns false if any of the inclusive
//! memory addresses is protect from writes.
//!
//! \param startAddr is the start address to scan
//!
//! \param endAddr is the end address to scan
//!
//! \return true if sector protection enabled on any of the incluseive memory
//! addresses, false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_A_isMemoryRangeProtected(uint32_t startAddr,
uint32_t endAddr);
//*****************************************************************************
//
//! Scans over the given memory range and returns false if any of the inclusive
//! memory addresses is protect from writes.
//!
//! \param startAddr is the start address to scan
//!
//! \param endAddr is the end address to scan
//!
//! \return true if sector protection enabled on any of the incluseive memory
//! addresses, false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_A_isMemoryProtected(uint32_t addr);
//*****************************************************************************
//
//! Verifies a given segment of memory based off either a high (1) or low (0)
//! state.
//!
//! \param verifyAddr Start address where verification will begin
//!
//! \param length Length in bytes to verify based off the pattern
//!
//! \param pattern The pattern which verification will check versus. This can
//! either be a low pattern (each register will be checked versus a pattern
//! of 32 zeros, or a high pattern (each register will be checked versus a
//! pattern of 32 ones). Valid values are: FLASH_A_0_PATTERN, FLASH_A_1_PATTERN
//!
//! \note There are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot verify a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if memory verification is successful, false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_A_verifyMemory(void* verifyAddr, uint32_t length,
uint_fast8_t pattern);
//*****************************************************************************
//
//! Performs a mass erase on all unprotected flash sectors. Protected sectors
//! are ignored.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if mass erase completes successfully, false otherwise
//
//*****************************************************************************
extern bool FlashCtl_A_performMassErase(void);
//*****************************************************************************
//
//! Initiates a mass erase and returns control back to the program. This is a
//! non-blocking function, however it is the user's responsibility to perform
//! the necessary verification requirements after the interrupt is set to
//! signify completion.
//!
//! \return None
//
//*****************************************************************************
extern void FlashCtl_A_initiateMassErase(void);
//*****************************************************************************
//
//! Erases a sector of MAIN or INFO flash memory.
//!
//! \param addr The start of the sector to erase. Note that with flash,
//! the minimum allowed size that can be erased is a flash sector
//! (which is 4KB on the MSP432 family). If an address is provided to
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if sector erase is successful, false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_A_eraseSector(uint32_t addr);
//*****************************************************************************
//
//! Program a portion of flash memory with the provided data
//!
//! \param src Pointer to the data source to program into flash
//!
//! \param dest Pointer to the destination in flash to program
//!
//! \param length Length in bytes to program
//!
//! \note There are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot program a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return Whether or not the program succeeded
//
//*****************************************************************************
extern bool FlashCtl_A_programMemory(void* src, void* dest,
uint32_t length);
//*****************************************************************************
//
//! Setups pre/post verification of burst and regular flash programming
//! instructions. Note that this API is for advanced users that are programming
//! their own flash drivers. The program/erase APIs are not affected by this
//! setting and take care of the verification requirements.
//!
//! \param verificationSetting Verification setting to set. This value can
//! be a bitwise OR of the following values:
//! - \b FLASH_A_BURSTPOST,
//! - \b FLASH_A_BURSTPRE,
//! - \b FLASH_A_REGPRE,
//! - \b FLASH_A_REGPOST
//! - \b FLASH_A_NOVER No verification enabled
//! - \b FLASH_A_FULLVER Full verification enabled
//!
//! \return none
//
//*****************************************************************************
extern void FlashCtl_A_setProgramVerification(uint32_t verificationSetting);
//*****************************************************************************
//
//! Clears pre/post verification of burst and regular flash programming
//! instructions. Note that this API is for advanced users that are programming
//! their own flash drivers. The program/erase APIs are not affected by this
//! setting and take care of the verification requirements.
//!
//! \param verificationSetting Verification setting to clear. This value can
//! be a bitwise OR of the following values:
//! - \b FLASH_A_BURSTPOST,
//! - \b FLASH_A_BURSTPRE,
//! - \b FLASH_A_REGPRE,
//! - \b FLASH_A_REGPOST
//! - \b FLASH_A_NOVER No verification enabled
//! - \b FLASH_A_FULLVER Full verification enabled
//!
//! \return none
//
//*****************************************************************************
extern void FlashCtl_A_clearProgramVerification(
uint32_t verificationSetting);
//*****************************************************************************
//
//! Enables word programming of flash memory.
//!
//! This function will enable word programming of the flash memory and set the
//! mode of behavior when the flash write occurs.
//!
//! \param mode The mode specifies the behavior of the flash controller when
//! programming words to flash. In \b FLASH_A_IMMEDIATE_WRITE_MODE, the
//! program operation happens immediately on the write to flash while
//! in \b FLASH_A_COLLATED_WRITE_MODE the write will be delayed until a full
//! 128-bits have been collated. Possible values include:
//! - \b FLASH_A_IMMEDIATE_WRITE_MODE
//! - \b FLASH_A_COLLATED_WRITE_MODE
//!
//!
//! Refer to the user's guide for further documentation.
//!
//! \return none
//
//*****************************************************************************
extern void FlashCtl_A_enableWordProgramming(uint32_t mode);
//*****************************************************************************
//
//! Disables word programming of flash memory.
//!
//! Refer to FlashCtl_A_enableWordProgramming and the user's guide for description
//! on the difference between full word and immediate programming
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_disableWordProgramming(void);
//*****************************************************************************
//
//! Returns if word programming mode is enabled (and if it is, the specific mode)
//!
//! Refer to FlashCtl_A_enableWordProgramming and the user's guide for description
//! on the difference between full word and immediate programming
//!
//! \return a zero value if word programming is disabled,
//! - \b FLASH_A_IMMEDIATE_WRITE_MODE
//! - \b FLASH_A_COLLATED_WRITE_MODE
//!
//
//*****************************************************************************
extern uint32_t FlashCtl_A_isWordProgrammingEnabled(void);
//*****************************************************************************
//
//! Sets the flash read mode to be used by default flash read operations.
//! Note that the proper wait states must be set prior to entering this
//! function.
//!
//! \param flashBank Flash bank to set read mode for. Valid values are:
//! - \b FLASH_A_BANK0
//! - \b FLASH_A_BANK1
//!
//! \param readMode The read mode to set. Valid values are:
//! - \b FLASH_A_NORMAL_READ_MODE,
//! - \b FLASH_A_MARGIN0_READ_MODE,
//! - \b FLASH_A_MARGIN1_READ_MODE,
//! - \b FLASH_A_PROGRAM_VERIFY_READ_MODE,
//! - \b FLASH_A_ERASE_VERIFY_READ_MODE,
//! - \b FLASH_A_LEAKAGE_VERIFY_READ_MODE,
//! - \b FLASH_A_MARGIN0B_READ_MODE,
//! - \b FLASH_A_MARGIN1B_READ_MODE
//!
//! \return None.
//
//*****************************************************************************
extern bool FlashCtl_A_setReadMode(uint32_t flashBank, uint32_t readMode);
//*****************************************************************************
//
//! Gets the flash read mode to be used by default flash read operations.
//!
//! \param flashBank Flash bank to set read mode for. Valid values are:
//! - \b FLASH_A_BANK0
//! - \b FLASH_A_BANK1
//!
//! \return Returns the read mode to set. Valid values are:
//! - \b FLASH_A_NORMAL_READ_MODE,
//! - \b FLASH_A_MARGIN0_READ_MODE,
//! - \b FLASH_A_MARGIN1_READ_MODE,
//! - \b FLASH_A_PROGRAM_VERIFY_READ_MODE,
//! - \b FLASH_A_ERASE_VERIFY_READ_MODE,
//! - \b FLASH_A_LEAKAGE_VERIFY_READ_MODE,
//! - \b FLASH_A_MARGIN0B_READ_MODE,
//! - \b FLASH_A_MARGIN1B_READ_MODE
//!
//
//*****************************************************************************
extern uint32_t FlashCtl_A_getReadMode(uint32_t flashBank);
//*****************************************************************************
//
//! Changes the number of wait states that are used by the flash controller
//! for read operations. When changing frequency ranges of the clock, this
//! functions must be used in order to allow for readable flash memory.
//!
//! \param waitState The number of wait states to set. Note that only
//! bits 0-3 are used.
//!
//! \param flashBank Flash bank to set wait state for. Valid values are:
//! - \b FLASH_A_BANK0
//! - \b FLASH_A_BANK1
//!
//
//*****************************************************************************
extern void FlashCtl_A_setWaitState(uint32_t bank, uint32_t waitState);
//*****************************************************************************
//
//! Returns the set number of flash wait states for the given flash bank.
//!
//! \param flashBank Flash bank to set wait state for. Valid values are:
//! - \b FLASH_A_BANK0
//! - \b FLASH_A_BANK1
//!
//! \return The wait state setting for the specified flash bank
//
//*****************************************************************************
extern uint32_t FlashCtl_A_getWaitState(uint32_t bank);
//*****************************************************************************
//
//! Enables individual flash control interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be enabled. Must
//! be a logical OR of:
//! - \b FLASH_A_PROGRAM_ERROR,
//! - \b FLASH_A_BENCHMARK_INT,
//! - \b FLASH_A_ERASE_COMPLETE,
//! - \b FLASH_A_BRSTPRGM_COMPLETE,
//! - \b FLASH_A_WRDPRGM_COMPLETE,
//! - \b FLASH_A_POSTVERIFY_FAILED,
//! - \b FLASH_A_PREVERIFY_FAILED,
//! - \b FLASH_A_BRSTRDCMP_COMPLETE
//!
//! This function enables the indicated flash system interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_enableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Disables individual flash system interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be disabled. Must
//! be a logical OR of:
//! - \b FLASH_A_PROGRAM_ERROR,
//! - \b FLASH_A_BENCHMARK_INT,
//! - \b FLASH_A_ERASE_COMPLETE,
//! - \b FLASH_A_BRSTPRGM_COMPLETE,
//! - \b FLASH_A_WRDPRGM_COMPLETE,
//! - \b FLASH_A_POSTVERIFY_FAILED,
//! - \b FLASH_A_PREVERIFY_FAILED,
//! - \b FLASH_A_BRSTRDCMP_COMPLETE
//!
//! This function disables the indicated flash system interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_disableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Gets the current interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list
//! of pending interrupts that are actually enabled and could have caused the
//! ISR.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! - \b FLASH_A_PROGRAM_ERROR,
//! - \b FLASH_A_BENCHMARK_INT,
//! - \b FLASH_A_ERASE_COMPLETE,
//! - \b FLASH_A_BRSTPRGM_COMPLETE,
//! - \b FLASH_A_WRDPRGM_COMPLETE,
//! - \b FLASH_A_POSTVERIFY_FAILED,
//! - \b FLASH_A_PREVERIFY_FAILED,
//! - \b FLASH_A_BRSTRDCMP_COMPLETE
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t FlashCtl_A_getEnabledInterruptStatus(void);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b FLASH_A_PROGRAM_ERROR,
//! - \b FLASH_A_BENCHMARK_INT,
//! - \b FLASH_A_ERASE_COMPLETE,
//! - \b FLASH_A_BRSTPRGM_COMPLETE,
//! - \b FLASH_A_WRDPRGM_COMPLETE,
//! - \b FLASH_A_POSTVERIFY_FAILED,
//! - \b FLASH_A_PREVERIFY_FAILED,
//! - \b FLASH_A_BRSTRDCMP_COMPLETE
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t FlashCtl_A_getInterruptStatus(void);
//*****************************************************************************
//
//! Clears flash system interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be cleared. Must
//! be a logical OR of:
//! - \b FLASH_A_PROGRAM_ERROR,
//! - \b FLASH_A_BENCHMARK_INT,
//! - \b FLASH_A_ERASE_COMPLETE,
//! - \b FLASH_A_BRSTPRGM_COMPLETE,
//! - \b FLASH_A_WRDPRGM_COMPLETE,
//! - \b FLASH_A_POSTVERIFY_FAILED,
//! - \b FLASH_A_PREVERIFY_FAILED,
//! - \b FLASH_A_BRSTRDCMP_COMPLETE
//!
//! The specified flash system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep it from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_clearInterruptFlag(uint32_t flags);
//*****************************************************************************
//
//! Registers an interrupt handler for flash clock system interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the clock
//! system interrupt occurs.
//!
//! This function registers the handler to be called when a clock system
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific flash controller interrupts must be enabled
//! via FlashCtl_A_enableInterrupt(). It is the interrupt handler's
//! responsibility to clear the interrupt source via
//! FlashCtl_A_clearInterruptFlag().
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash system.
//!
//! This function unregisters the handler to be called when a clock system
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_A_unregisterInterrupt(void);
//*****************************************************************************
//
//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
//! function simply initaites the sector erase, but does no verification
//! which is required by the flash controller. The user must manually set
//! and enable interrupts on the flash controller to fire on erase completion
//! and then use the FlashCtl_A_verifyMemory function to verify that the sector
//! was actually erased
//!
//! \param addr The start of the sector to erase. Note that with flash,
//! the minimum allowed size that can be erased is a flash sector
//! (which is 4KB on the MSP432 family). If an address is provided to
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! \return None
//
//*****************************************************************************
extern void FlashCtl_A_initiateSectorErase(uint32_t addr);
/* The following functions are advanced functions that are used by the flash
* driver to remask a failed bit in the event of a post or pre verification
* failure. They are meant to be advanced functions and should not be used
* by the majority of users (unless you are writing your own flash driver).
*/
extern uint8_t __FlashCtl_A_remaskData8Post(uint8_t data, uint32_t addr);
extern uint8_t __FlashCtl_A_remaskData8Pre(uint8_t data, uint32_t addr);
extern uint32_t __FlashCtl_A_remaskData32Post(uint32_t data, uint32_t addr);
extern uint32_t __FlashCtl_A_remaskData32Pre(uint32_t data, uint32_t addr);
extern void __FlashCtl_A_remaskBurstDataPost(uint32_t addr, uint32_t size);
extern void __FlashCtl_A_remaskBurstDataPre(uint32_t addr, uint32_t size);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* __MCU_HAS_FLCTL_A__ */
#endif // __FLASH_A_H__

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/fpu.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/fpu.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,7 +29,7 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <fpu.h>
#include <ti/devices/msp432p4xx/driverlib/fpu.h>
void FPU_enableModule(void)
{

13
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/fpu.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/fpu.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +52,7 @@ extern "C"
#endif
#include <stdint.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
@ -203,7 +198,7 @@ extern void FPU_setHalfPrecisionMode(uint32_t mode);
//
//! Selects the NaN mode.
//!
//! \param mode is the mode for NaN results; which is
//! \param mode is the mode for NaN results; which is
//! either \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
//!
//! This function selects the handling of NaN results during floating-point

BIN
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/gcc/msp432p4xx_driverlib.a Normal file
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Binary file not shown.

55
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/gpio.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/gpio.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,24 +33,10 @@
#include <stdint.h>
/* DriverLib Includes */
#include <gpio.h>
#include <debug.h>
#include <interrupt.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/gpio.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
/* DriverLib internal GPIO register offset for optimized performace */
#define OFS_LIB_PAIN ((uint32_t)&P1->IN - (uint32_t)P1)
#define OFS_LIB_PAOUT ((uint32_t)&P1->OUT - (uint32_t)P1)
#define OFS_LIB_PADIR ((uint32_t)&P1->DIR - (uint32_t)P1)
#define OFS_LIB_PAREN ((uint32_t)&P1->REN - (uint32_t)P1)
#define OFS_LIB_PADS ((uint32_t)&P1->DS - (uint32_t)P1)
#define OFS_LIB_PASEL0 ((uint32_t)&P1->SEL0 - (uint32_t)P1)
#define OFS_LIB_PASEL1 ((uint32_t)&P1->SEL1 - (uint32_t)P1)
#define OFS_LIB_PAIE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_PAIES ((uint32_t)&P1->IES - (uint32_t)P1)
#define OFS_LIB_PAIFG ((uint32_t)&P1->IFG - (uint32_t)P1)
#define OFS_LIB_P1IE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_P2IE ((uint32_t)&P2->IE - (uint32_t)P2)
static const uint32_t GPIO_PORT_TO_INT[] =
{ 0x00,
@ -66,20 +47,20 @@ INT_PORT4,
INT_PORT5,
INT_PORT6 };
static uint32_t GPIO_PORT_TO_BASE[] =
static const uint32_t GPIO_PORT_TO_BASE[] =
{ 0x00,
(uint32_t)P1,
(uint32_t)P1+1,
(uint32_t)P3,
(uint32_t)P3+1,
(uint32_t)P5,
(uint32_t)P5+1,
(uint32_t)P7,
(uint32_t)P7+1,
(uint32_t)P9,
(uint32_t)P9+1,
(uint32_t)PJ
};
(uint32_t)P1,
(uint32_t)P1+1,
(uint32_t)P3,
(uint32_t)P3+1,
(uint32_t)P5,
(uint32_t)P5+1,
(uint32_t)P7,
(uint32_t)P7+1,
(uint32_t)P9,
(uint32_t)P9+1,
(uint32_t)PJ
};
void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{

37
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/gpio.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/gpio.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -55,7 +50,7 @@ extern "C"
{
#endif
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdint.h>
#define GPIO_PORT_P1 1
@ -75,7 +70,7 @@ extern "C"
#define GPIO_PORT_PE 9
#define GPIO_PORT_PJ 11
#define GPIO_PIN0 (0x0001)
#define GPIO_PIN1 (0x0002)
#define GPIO_PIN2 (0x0004)
@ -105,6 +100,20 @@ extern "C"
#define GPIO_INPUT_PIN_HIGH (0x01)
#define GPIO_INPUT_PIN_LOW (0x00)
/* DriverLib internal GPIO register offset for optimized performance */
#define OFS_LIB_PAIN ((uint32_t)&P1->IN - (uint32_t)P1)
#define OFS_LIB_PAOUT ((uint32_t)&P1->OUT - (uint32_t)P1)
#define OFS_LIB_PADIR ((uint32_t)&P1->DIR - (uint32_t)P1)
#define OFS_LIB_PAREN ((uint32_t)&P1->REN - (uint32_t)P1)
#define OFS_LIB_PADS ((uint32_t)&P1->DS - (uint32_t)P1)
#define OFS_LIB_PASEL0 ((uint32_t)&P1->SEL0 - (uint32_t)P1)
#define OFS_LIB_PASEL1 ((uint32_t)&P1->SEL1 - (uint32_t)P1)
#define OFS_LIB_PAIE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_PAIES ((uint32_t)&P1->IES - (uint32_t)P1)
#define OFS_LIB_PAIFG ((uint32_t)&P1->IFG - (uint32_t)P1)
#define OFS_LIB_P1IE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_P2IE OFS_LIB_P1IE
//*****************************************************************************
//
// Prototypes for the APIs.
@ -693,8 +702,7 @@ extern void GPIO_disableInterrupt(uint_fast8_t selectedPort,
//
//! \brief This function gets the interrupt status of the selected pin
//!
//! This function gets the interrupt status of the selected pin. Note that only
//! Port 1,2, A have this capability.
//! This function gets the interrupt status of the selected pin.
//!
//! \param selectedPort is the selected port.
//! Valid values are:
@ -748,8 +756,7 @@ extern uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
//
//! \brief This function clears the interrupt flag on the selected pin
//!
//! This function clears the interrupt flag on the selected pin. Note that only
//! Port 1,2,A have this capability.
//! This function clears the interrupt flag on the selected pin.
//!
//! \param selectedPort is the selected port.
//! Valid values are:
@ -1002,11 +1009,11 @@ extern void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
//*****************************************************************************
extern void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
uint_fast8_t selectedPins);
/* Backwards Compatibility Layer */
#define GPIO_selectInterruptEdge GPIO_interruptEdgeSelect
#define GPIO_clearInterrupt GPIO_clearInterruptFlag
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.

449
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/i2c.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/i2c.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,40 +29,39 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <i2c.h>
#include <interrupt.h>
#include <debug.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/i2c.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
void I2C_initMaster(uint32_t moduleInstance,
const eUSCI_I2C_MasterConfig *config)
{
uint_fast16_t preScalarValue;
ASSERT(
(EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_B_I2C_CLOCKSOURCE_SMCLK
== config->selectClockSource));
|| (EUSCI_B_I2C_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
|| (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)
|| (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate));
|| (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)
|| (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate));
ASSERT(
(EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
|| (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
== config->autoSTOPGeneration)
|| (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
== config->autoSTOPGeneration));
|| (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
== config->autoSTOPGeneration)
|| (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
== config->autoSTOPGeneration));
/* Disable the USCI module and clears the other bits of control register */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
1;
/* Configure Automatic STOP condition generation */
EUSCI_B_CMSIS(moduleInstance)->CTLW1 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW1 & ~EUSCI_B_CTLW1_ASTP_MASK)
| (config->autoSTOPGeneration);
EUSCI_B_CMSIS(moduleInstance)->CTLW1 = (EUSCI_B_CMSIS(moduleInstance)->CTLW1
& ~EUSCI_B_CTLW1_ASTP_MASK) | (config->autoSTOPGeneration);
/* Byte Count Threshold */
EUSCI_B_CMSIS(moduleInstance)->TBCNT = config->byteCounterThreshold;
@ -78,11 +72,11 @@ void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *confi
* UCMODE_3 = I2C mode
* UCSYNC = Synchronous mode
*/
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_B_CTLW0_SSEL_MASK)
| (config->selectClockSource | EUSCI_B_CTLW0_MST
| EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC
| EUSCI_B_CTLW0_SWRST);
EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0
& ~EUSCI_B_CTLW0_SSEL_MASK)
| (config->selectClockSource | EUSCI_B_CTLW0_MST
| EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC
| EUSCI_B_CTLW0_SWRST);
/*
* Compute the clock divider that achieves the fastest speed less than or
@ -100,36 +94,38 @@ void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
{
ASSERT(
(EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
/* Disable the USCI module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
1;
/* Clear USCI master mode */
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_MST))
| (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC);
EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0
& (~EUSCI_B_CTLW0_MST))
| (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC);
/* Set up the slave address. */
HWREG16((uint32_t)&EUSCI_B_CMSIS(moduleInstance)->I2COA0 + slaveAddressOffset) =
slaveAddress + slaveOwnAddressEnable;
HWREG16(
(uint32_t) &EUSCI_B_CMSIS(moduleInstance)->I2COA0
+ slaveAddressOffset) = slaveAddress
+ slaveOwnAddressEnable;
}
void I2C_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
0;
}
void I2C_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
1;
;
}
@ -143,28 +139,72 @@ void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
{
ASSERT(
(EUSCI_B_I2C_TRANSMIT_MODE == mode)
|| (EUSCI_B_I2C_RECEIVE_MODE == mode));
|| (EUSCI_B_I2C_RECEIVE_MODE == mode));
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0
& (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0
& (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
}
void I2C_setTimeout(uint32_t moduleInstance, uint_fast16_t timeout)
{
uint_fast16_t swrstValue;
ASSERT(
(EUSCI_B_I2C_TIMEOUT_DISABLE == timeout)
|| (EUSCI_B_I2C_TIMEOUT_28_MS == timeout)
|| (EUSCI_B_I2C_TIMEOUT_31_MS == timeout)
|| (EUSCI_B_I2C_TIMEOUT_34_MS == timeout));
/* Save value of UCSWRST bit and disable USCI module */
swrstValue = BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS);
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
1;
/* Set timeout */
EUSCI_B_CMSIS(moduleInstance)->CTLW1 = (EUSCI_B_CMSIS(moduleInstance)->CTLW1
& (~EUSCI_B_CTLW1_CLTO_3)) | timeout;
/* Restore value of UCSWRST bit */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
swrstValue;
}
uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
{
uint_fast16_t rxieStatus;
//Store current RXIE status
rxieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_RXIE0;
//Disable receive interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS) = 0;
//Set USCI in Receive mode
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TR_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TR_OFS) =
0;
//Send start
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT + EUSCI_B_CTLW0_TXSTP);
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT
+ EUSCI_B_CTLW0_TXSTP);
//Poll for receive interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_RXIFG_OFS))
;
//Send single byte data.
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
//Receive single byte data.
uint8_t receivedByte = (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
//Clear receive interrupt flag before enabling interrupt again
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG0_OFS) =
0;
//Reinstate receive interrupt enable
EUSCI_B_CMSIS(moduleInstance)->IE |= rxieStatus;
return receivedByte;
}
void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
@ -183,7 +223,7 @@ uint8_t I2C_isBusBusy(uint32_t moduleInstance)
{
//Return the bus busy status.
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->STATW,
EUSCI_B_STATW_BBUSY_OFS);
EUSCI_B_STATW_BBUSY_OFS);
}
void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
@ -195,11 +235,14 @@ void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR
+ EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
;
//Poll for transmit interrupt flag and start condition flag.
while ((BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTT_OFS)
|| !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)));
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
@ -230,13 +273,15 @@ bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR
+ EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) && --timeout)
while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
&& --timeout)
;
//Check if transfer timed out
@ -247,8 +292,8 @@ bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout2)
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)) && --timeout2)
;
//Check if transfer timed out
@ -256,10 +301,12 @@ bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
//Clear transmit interrupt flag before enabling interrupt again
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,EUSCI_B_IFG_TXIFG0_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS) =
0;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
@ -276,11 +323,14 @@ void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR
+ EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
//Poll for transmit interrupt flag and start condition flag.
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTT_OFS)
|| !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS));
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
@ -300,15 +350,18 @@ bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR
+ EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag and start condition flag.
while ((BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTT_OFS)
|| !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)) && --timeout);
//Poll for transmit interrupt flag.
while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout))
;
//Check if transfer timed out
if (timeout == 0)
@ -329,8 +382,8 @@ void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS))
;
}
@ -362,14 +415,14 @@ bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
return true;
}
void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
{
bool I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS))
;
}
@ -377,11 +430,19 @@ void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)
&& !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_NACKIFG_OFS))
;
if(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_NACKIFG_OFS))
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
return true;
}
bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
@ -408,8 +469,10 @@ bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout2)
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)) && --timeout2
&& !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_NACKIFG_OFS))
;
//Check if transfer timed out
@ -417,7 +480,8 @@ bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
return true;
}
@ -428,13 +492,14 @@ void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
}
bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
@ -456,7 +521,8 @@ bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
return 0x01;
}
@ -464,9 +530,8 @@ bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
void I2C_masterReceiveStart(uint32_t moduleInstance)
{
//Set USCI in Receive mode
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_TR))
| EUSCI_B_CTLW0_TXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0
& (~EUSCI_B_CTLW0_TR)) | EUSCI_B_CTLW0_TXSTT;
}
uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
@ -477,14 +542,16 @@ uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
{
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS))
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTP_OFS))
{
// Wait for RX buffer
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_RXIFG_OFS))
;
}
@ -501,11 +568,12 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
ASSERT(timeout > 0);
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS)
&& --timeout)
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTP_OFS) && --timeout)
;
//Check if transfer timed out
@ -513,8 +581,8 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
return false;
// Wait for RX buffer
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
&& --timeout2)
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_RXIFG_OFS)) && --timeout2)
;
//Check if transfer timed out
@ -531,7 +599,8 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
{
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) =
1;
}
uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
@ -540,76 +609,78 @@ uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS))
{
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_RXIFG0_OFS))
EUSCI_B_IFG_RXIFG0_OFS))
;
}
//Read a byte.
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK) ;
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->RXBUF;
return (uint32_t) &EUSCI_B_CMSIS(moduleInstance)->RXBUF;
}
uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
return (uint32_t) &EUSCI_B_CMSIS(moduleInstance)->TXBUF;
}
uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
{
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTP_OFS);
EUSCI_B_CTLW0_TXSTP_OFS);
}
bool I2C_masterIsStartSent(uint32_t moduleInstance)
{
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTT_OFS);
EUSCI_B_CTLW0_TXSTT_OFS);
}
void I2C_masterSendStart(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTT_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS) =
1;
}
void I2C_enableMultiMasterMode(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_MM_OFS) =
1;
}
void I2C_disableMultiMasterMode(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_MM_OFS) =
0;
}
void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Enable the interrupt masked bit
EUSCI_B_CMSIS(moduleInstance)->IE |= mask;
@ -619,22 +690,22 @@ void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Disable the interrupt masked bit
EUSCI_B_CMSIS(moduleInstance)->IE &= ~(mask);
@ -644,22 +715,22 @@ void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Clear the I2C interrupt source.
EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(mask);
}
@ -668,22 +739,22 @@ uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Return the interrupt status of the request masked bit.
return EUSCI_B_CMSIS(moduleInstance)->IFG & mask;
}
@ -691,7 +762,7 @@ uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
{
return I2C_getInterruptStatus(moduleInstance,
EUSCI_B_CMSIS(moduleInstance)->IE);
EUSCI_B_CMSIS(moduleInstance)->IE);
}
uint_fast16_t I2C_getMode(uint32_t moduleInstance)
@ -713,13 +784,13 @@ void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_BASE
case EUSCI_B2_BASE:
case EUSCI_B2_BASE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_BASE
case EUSCI_B3_BASE:
case EUSCI_B3_BASE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
@ -742,13 +813,13 @@ void I2C_unregisterInterrupt(uint32_t moduleInstance)
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_BASE
case EUSCI_B2_BASE:
case EUSCI_B2_BASE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_BASE
case EUSCI_B3_BASE:
case EUSCI_B3_BASE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
@ -760,6 +831,6 @@ void I2C_unregisterInterrupt(uint32_t moduleInstance)
void I2C_slaveSendNAK(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXNACK_OFS)
= 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXNACK_OFS) =
1;
}

57
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/i2c.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/i2c.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,13 +52,13 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include "eusci.h"
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <ti/devices/msp432p4xx/driverlib/eusci.h>
#define EUSCI_B_I2C_NO_AUTO_STOP EUSCI_B_CTLW1_ASTP_0
#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG EUSCI_B_CTLW1_ASTP_1
#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD \
EUSCI_B_CTLW1_ASTP_2
EUSCI_B_CTLW1_ASTP_2
#define EUSCI_B_I2C_SET_DATA_RATE_1MBPS 1000000
#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000
@ -83,6 +78,11 @@ extern "C"
#define EUSCI_B_I2C_TRANSMIT_MODE EUSCI_B_CTLW0_TR
#define EUSCI_B_I2C_RECEIVE_MODE 0x00
#define EUSCI_B_I2C_TIMEOUT_DISABLE EUSCI_B_CTLW1_CLTO_0
#define EUSCI_B_I2C_TIMEOUT_28_MS EUSCI_B_CTLW1_CLTO_1
#define EUSCI_B_I2C_TIMEOUT_31_MS EUSCI_B_CTLW1_CLTO_2
#define EUSCI_B_I2C_TIMEOUT_34_MS EUSCI_B_CTLW1_CLTO_3
#define EUSCI_B_I2C_NAK_INTERRUPT EUSCI_B_IE_NACKIE
#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT EUSCI_B_IE_ALIE
#define EUSCI_B_I2C_STOP_INTERRUPT EUSCI_B_IE_STPIE
@ -194,7 +194,7 @@ extern void I2C_initMaster(uint32_t moduleInstance,
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
//! \param slaveAddress 7-bit or 10-bit slave address
//! \param slaveAddress 7-bit or 10-bit slave address
//! \param slaveAddressOffset Own address Offset referred to- 'x' value of
//! UCBxI2COAx. Valid values are:
//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0,
@ -319,6 +319,34 @@ extern void I2C_setSlaveAddress(uint32_t moduleInstance,
//*****************************************************************************
extern void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode);
//*****************************************************************************
//
//! Sets the timeout of the I2C device
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
//! \param timeout indicates desired timeout
//! - \b EUSCI_B_I2C_TIMEOUT_DISABLE [Default value]
//! - \b EUSCI_B_I2C_TIMEOUT_28_MS
//! - \b EUSCI_B_I2C_TIMEOUT_31_MS
//! - \b EUSCI_B_I2C_TIMEOUT_34_MS
//!
//! Modified bits are \b UCSWRST of \b UCBxCTL0 and \b UCCLTO of \b UCBxCTL1
//! registers
//!
//! \return None.
//
//*****************************************************************************
extern void I2C_setTimeout(uint32_t moduleInstance, uint_fast16_t timeout);
//*****************************************************************************
//
//! \brief Gets the mode of the I2C device
@ -624,10 +652,10 @@ extern bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
//!
//! Modified registers are \b UCBxTXBUF and \b UCBxCTL1.
//!
//! \return None.
//! \return false if NAK occurred, false otherwise
//
//*****************************************************************************
extern void I2C_masterSendMultiByteFinish(uint32_t moduleInstance,
extern bool I2C_masterSendMultiByteFinish(uint32_t moduleInstance,
uint8_t txData);
//*****************************************************************************
@ -991,7 +1019,8 @@ extern uint8_t I2C_masterIsStopSent(uint32_t moduleInstance);
//! This function checks the status of the bus via UCTXSTT bit in
//! UCBxCTL1 register.
//!
//! \return Returns true if the START has been sent, false if it is sending
//! \return Returns EUSCI_B_I2C_BUS_BUSY if the I2C Master is busy; otherwise,
//! returns EUSCI_B_I2C_BUS_NOT_BUSY.
//
//*****************************************************************************
extern bool I2C_masterIsStartSent(uint32_t moduleInstance);

984
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/iar/msp432_driverlib.dep Normal file
View File

@ -0,0 +1,984 @@
<?xml version="1.0" encoding="UTF-8"?>
<project>
<fileVersion>2</fileVersion>
<fileChecksum>2783424352</fileChecksum>
<configuration>
<name>Debug</name>
<outputs>
<file>$PROJ_DIR$\..\sysctl.c</file>
<file>$PROJ_DIR$\..\flash_a.c</file>
<file>$PROJ_DIR$\..\lcd_f.c</file>
<file>$PROJ_DIR$\..\flash.c</file>
<file>$PROJ_DIR$\..\sysctl_a.c</file>
<file>$PROJ_DIR$\..\adc14.c</file>
<file>$PROJ_DIR$\..\aes256.c</file>
<file>$PROJ_DIR$\..\comp_e.c</file>
<file>$PROJ_DIR$\..\cpu.c</file>
<file>$PROJ_DIR$\..\crc32.c</file>
<file>$PROJ_DIR$\..\cs.c</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</file>
<file>$PROJ_DIR$\lcd_f.o</file>
<file>$PROJ_DIR$\aes256.o</file>
<file>$PROJ_DIR$\sysctl_a.o</file>
<file>$PROJ_DIR$\adc14.o</file>
<file>$PROJ_DIR$\comp_e.o</file>
<file>$PROJ_DIR$\cpu.o</file>
<file>$PROJ_DIR$\crc32.o</file>
<file>$PROJ_DIR$\cs.o</file>
<file>$PROJ_DIR$\dma.o</file>
<file>$PROJ_DIR$\fpu.o</file>
<file>$PROJ_DIR$\gpio.o</file>
<file>$PROJ_DIR$\i2c.o</file>
<file>$PROJ_DIR$\interrupt.o</file>
<file>$PROJ_DIR$\mpu.o</file>
<file>$PROJ_DIR$\pcm.o</file>
<file>$PROJ_DIR$\pmap.o</file>
<file>$PROJ_DIR$\pss.o</file>
<file>$PROJ_DIR$\ref_a.o</file>
<file>$PROJ_DIR$\reset.o</file>
<file>$PROJ_DIR$\rtc_c.o</file>
<file>$PROJ_DIR$\spi.o</file>
<file>$PROJ_DIR$\systick.o</file>
<file>$PROJ_DIR$\timer32.o</file>
<file>$PROJ_DIR$\timer_a.o</file>
<file>$PROJ_DIR$\uart.o</file>
<file>$PROJ_DIR$\wdt_a.o</file>
<file>$PROJ_DIR$\..\..\inc\system_msp432p401r.h</file>
<file>$PROJ_DIR$\flash.pbi</file>
<file>$PROJ_DIR$\sysctl.pbi</file>
<file>$PROJ_DIR$\flash_a.pbi</file>
<file>$PROJ_DIR$\lcd_f.pbi</file>
<file>$PROJ_DIR$\sysctl_a.pbi</file>
<file>$PROJ_DIR$\adc14.pbi</file>
<file>$PROJ_DIR$\aes256.pbi</file>
<file>$PROJ_DIR$\comp_e.pbi</file>
<file>$PROJ_DIR$\cpu.pbi</file>
<file>$PROJ_DIR$\crc32.pbi</file>
<file>$PROJ_DIR$\cs.pbi</file>
<file>$PROJ_DIR$\dma.pbi</file>
<file>$PROJ_DIR$\fpu.pbi</file>
<file>$PROJ_DIR$\gpio.pbi</file>
<file>$PROJ_DIR$\i2c.pbi</file>
<file>$PROJ_DIR$\interrupt.pbi</file>
<file>$PROJ_DIR$\mpu.pbi</file>
<file>$PROJ_DIR$\..\dma.c</file>
<file>$PROJ_DIR$\..\fpu.c</file>
<file>$PROJ_DIR$\..\gpio.c</file>
<file>$PROJ_DIR$\..\i2c.c</file>
<file>$PROJ_DIR$\..\interrupt.c</file>
<file>$PROJ_DIR$\..\mpu.c</file>
<file>$PROJ_DIR$\..\pcm.c</file>
<file>$PROJ_DIR$\..\pmap.c</file>
<file>$PROJ_DIR$\..\pss.c</file>
<file>$PROJ_DIR$\..\ref_a.c</file>
<file>$PROJ_DIR$\..\reset.c</file>
<file>$PROJ_DIR$\..\rtc_c.c</file>
<file>$PROJ_DIR$\..\spi.c</file>
<file>$PROJ_DIR$\..\systick.c</file>
<file>$PROJ_DIR$\..\timer32.c</file>
<file>$PROJ_DIR$\..\timer_a.c</file>
<file>$PROJ_DIR$\..\uart.c</file>
<file>$PROJ_DIR$\..\wdt_a.c</file>
<file>$PROJ_DIR$\sysctl.o</file>
<file>$PROJ_DIR$\flash_a.o</file>
<file>$PROJ_DIR$\flash.o</file>
<file>$PROJ_DIR$\pcm.pbi</file>
<file>$PROJ_DIR$\pmap.pbi</file>
<file>$PROJ_DIR$\pss.pbi</file>
<file>$PROJ_DIR$\ref_a.pbi</file>
<file>$PROJ_DIR$\reset.pbi</file>
<file>$PROJ_DIR$\rtc_c.pbi</file>
<file>$PROJ_DIR$\spi.pbi</file>
<file>$PROJ_DIR$\systick.pbi</file>
<file>$PROJ_DIR$\timer32.pbi</file>
<file>$PROJ_DIR$\timer_a.pbi</file>
<file>$PROJ_DIR$\uart.pbi</file>
<file>$PROJ_DIR$\wdt_a.pbi</file>
<file>$PROJ_DIR$\msp432_driverlib.pbd</file>
<file>$PROJ_DIR$\msp432_driverlib.a</file>
<file>$PROJ_DIR$\..\crc32.h</file>
<file>$TOOLKIT_DIR$\inc\c\stdbool.h</file>
<file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
<file>$PROJ_DIR$\..\..\..\..\..\third_party\CMSIS\Include\cmsis_compiler.h</file>
<file>$PROJ_DIR$\..\rtc_c.h</file>
<file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
<file>$PROJ_DIR$\..\mpu.h</file>
<file>$PROJ_DIR$\..\flash.h</file>
<file>$PROJ_DIR$\..\..\inc\msp.h</file>
<file>$PROJ_DIR$\..\eusci.h</file>
<file>$PROJ_DIR$\..\adc14.h</file>
<file>$PROJ_DIR$\..\fpu.h</file>
<file>$PROJ_DIR$\..\ref_a.h</file>
<file>$PROJ_DIR$\..\timer_a.h</file>
<file>$PROJ_DIR$\..\debug.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
<file>$PROJ_DIR$\..\comp_e.h</file>
<file>$PROJ_DIR$\..\dma.h</file>
<file>$PROJ_DIR$\..\i2c.h</file>
<file>$PROJ_DIR$\..\pmap.h</file>
<file>$PROJ_DIR$\..\rom.h</file>
<file>$PROJ_DIR$\..\systick.h</file>
<file>$PROJ_DIR$\..\wdt_a.h</file>
<file>$PROJ_DIR$\..\..\inc\msp432p401r_classic.h</file>
<file>$PROJ_DIR$\..\driverlib.h</file>
<file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
<file>$PROJ_DIR$\..\aes256.h</file>
<file>$PROJ_DIR$\..\cpu.h</file>
<file>$PROJ_DIR$\..\cs.h</file>
<file>$PROJ_DIR$\..\gpio.h</file>
<file>$PROJ_DIR$\..\interrupt.h</file>
<file>$PROJ_DIR$\..\pcm.h</file>
<file>$PROJ_DIR$\..\pss.h</file>
<file>$PROJ_DIR$\..\reset.h</file>
<file>$PROJ_DIR$\..\rom_map.h</file>
<file>$PROJ_DIR$\..\spi.h</file>
<file>$PROJ_DIR$\..\timer32.h</file>
<file>$PROJ_DIR$\..\uart.h</file>
<file>$PROJ_DIR$\..\sysctl.h</file>
<file>$PROJ_DIR$\..\..\inc\msp432p401r.h</file>
<file>$PROJ_DIR$\..\..\inc\msp_compatibility.h</file>
<file>$PROJ_DIR$\..\..\..\..\..\third_party\CMSIS\Include\core_cm4.h</file>
<file>$PROJ_DIR$\..\..\..\..\..\third_party\CMSIS\Include\cmsis_iar.h</file>
<file>$TOOLKIT_DIR$\inc\c\intrinsics.h</file>
<file>$PROJ_DIR$\..\lcd_f.h</file>
<file>$PROJ_DIR$\sysctl.__cstat.et</file>
<file>$PROJ_DIR$\flash.__cstat.et</file>
<file>$PROJ_DIR$\flash_a.__cstat.et</file>
<file>$PROJ_DIR$\lcd_f.__cstat.et</file>
<file>$PROJ_DIR$\sysctl_a.__cstat.et</file>
<file>$PROJ_DIR$\adc14.__cstat.et</file>
<file>$PROJ_DIR$\aes256.__cstat.et</file>
<file>$PROJ_DIR$\comp_e.__cstat.et</file>
<file>$PROJ_DIR$\cpu.__cstat.et</file>
<file>$PROJ_DIR$\crc32.__cstat.et</file>
<file>$PROJ_DIR$\cs.__cstat.et</file>
<file>$PROJ_DIR$\dma.__cstat.et</file>
<file>$PROJ_DIR$\fpu.__cstat.et</file>
<file>$PROJ_DIR$\gpio.__cstat.et</file>
<file>$PROJ_DIR$\i2c.__cstat.et</file>
<file>$PROJ_DIR$\interrupt.__cstat.et</file>
<file>$PROJ_DIR$\mpu.__cstat.et</file>
<file>$PROJ_DIR$\pcm.__cstat.et</file>
<file>$PROJ_DIR$\pmap.__cstat.et</file>
<file>$PROJ_DIR$\pss.__cstat.et</file>
<file>$PROJ_DIR$\ref_a.__cstat.et</file>
<file>$PROJ_DIR$\reset.__cstat.et</file>
<file>$PROJ_DIR$\rtc_c.__cstat.et</file>
<file>$PROJ_DIR$\spi.__cstat.et</file>
<file>$PROJ_DIR$\systick.__cstat.et</file>
<file>$PROJ_DIR$\timer32.__cstat.et</file>
<file>$PROJ_DIR$\timer_a.__cstat.et</file>
<file>$PROJ_DIR$\uart.__cstat.et</file>
<file>$PROJ_DIR$\wdt_a.__cstat.et</file>
<file>$PROJ_DIR$\..\..\inc\system_msp432p4111.h</file>
<file>$PROJ_DIR$\..\..\inc\msp432p4111.h</file>
<file>$PROJ_DIR$\..\flash_a.h</file>
<file>$PROJ_DIR$\..\sysctl_a.h</file>
</outputs>
<file>
<name>[ROOT_NODE]</name>
<outputs>
<tool>
<name>IARCHIVE</name>
<file> 90</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\sysctl.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 74</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 40</file>
</tool>
<tool>
<name>__cstat</name>
<file> 137</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 92 130 99 131 132 134 135 115 133 94 38 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 115 93 117 130 38 134 92 105 96 106 107 99 131 132 133 135 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\flash_a.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 75</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 41</file>
</tool>
<tool>
<name>__cstat</name>
<file> 139</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 168 99 167 132 134 135 133 94 166 92 105 122 119 112 169</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 132 107 166 134 135 93 99 105 112 106 167 96 168 122 119 169 92 117 133 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\lcd_f.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 12</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 42</file>
</tool>
<tool>
<name>__cstat</name>
<file> 140</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 136 92 99 167 132 134 135 133 94 166 116 101 118 108 119 91 120 109 122 100 102 121 110 97 123 111 124 103 125 112 126 95 127 113 128 104 129 114 130 169 168</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 99 118 92 125 93 96 133 121 129 120 123 127 116 106 107 94 119 100 122 124 126 128 130 136 117 167 132 166 134 135 101 108 91 109 102 110 97 111 103 112 95 113 104 114 169 168</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\flash.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 76</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 39</file>
</tool>
<tool>
<name>__cstat</name>
<file> 138</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 116 101 99 131 132 134 135 115 133 94 38 92 118 108 119 91 120 109 122 100 102 121 110 97 123 111 124 103 125 112 126 95 127 113 128 104 129 114 130 98 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 91 92 93 94 95 96 97 98 99 100 101 102 103 104 38 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\sysctl_a.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 14</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 43</file>
</tool>
<tool>
<name>__cstat</name>
<file> 141</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 92 169 99 167 132 134 135 133 94 166 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 92 107 106 134 135 169 96 133 93 105 117 99 167 132 166 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\adc14.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 15</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 44</file>
</tool>
<tool>
<name>__cstat</name>
<file> 142</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 92 101 99 131 132 134 135 115 133 94 38 105 122</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 96 38 93 131 122 132 101 106 107 99 94 92 105 117 115 133 134 135</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\aes256.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 13</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 45</file>
</tool>
<tool>
<name>__cstat</name>
<file> 143</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 118 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 99 134 135 117 115 96 105 93 133 94 122 92 106 107 131 132 38 118</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\comp_e.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 16</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 46</file>
</tool>
<tool>
<name>__cstat</name>
<file> 144</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 108 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 93 92 133 96 105 106 107 131 132 94 122 99 117 115 38 108 134 135</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\cpu.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 17</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 47</file>
</tool>
<tool>
<name>__cstat</name>
<file> 145</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 119 93 117 96 106 11 107 99 131 132 134 135 115 133 94 38</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 93 94 117 131 132 38 99 96 106 107 115 133 134 135 119</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\crc32.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 18</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 48</file>
</tool>
<tool>
<name>__cstat</name>
<file> 146</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 91 93 117 96 106 11 107 99 131 132 134 135 115 133 94 38 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 93 38 131 132 105 117 99 96 106 107 115 133 134 135 91 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\cs.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 19</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 49</file>
</tool>
<tool>
<name>__cstat</name>
<file> 147</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 116 101 99 131 132 134 135 115 133 94 38 92 118 108 119 91 120 109 122 100 102 121 110 97 123 111 124 103 125 112 126 95 127 113 128 104 129 114 130 98 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 103 101 38 122 99 102 104 92 100 93 96 91 97 95 98 94 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 124 125 126 127 128 129 130 131 132 133 134 135</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\dma.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 20</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 50</file>
</tool>
<tool>
<name>__cstat</name>
<file> 148</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 105 122 92 99 131 132 134 135 115 133 94 38 109</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 117 132 93 92 131 122 133 134 105 109 96 106 107 99 115 38 135 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\fpu.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 21</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 51</file>
</tool>
<tool>
<name>__cstat</name>
<file> 149</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 102 93 117 96 106 11 107 99 131 132 134 135 115 133 94 38</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 96 94 133 93 106 107 115 134 135 99 117 131 132 38 102</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\gpio.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 22</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 52</file>
</tool>
<tool>
<name>__cstat</name>
<file> 150</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 121 99 131 132 134 135 115 133 94 38 105 122 92</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 132 134 135 96 99 131 105 106 107 93 133 92 121 122 117 115 38 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\i2c.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 23</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 53</file>
</tool>
<tool>
<name>__cstat</name>
<file> 151</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 110 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 100 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 117 115 96 100 134 135 94 105 92 133 93 122 99 106 107 131 132 38 110</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\interrupt.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 24</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 54</file>
</tool>
<tool>
<name>__cstat</name>
<file> 152</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 105 119 122 92 99 131 132 134 135 115 133 94 38</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 94 132 117 131 38 119 92 93 105 122 96 106 107 99 115 133 134 135</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\mpu.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 25</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 55</file>
</tool>
<tool>
<name>__cstat</name>
<file> 153</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 105 122 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 97</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 99 96 93 97 106 107 131 132 38 122 92 117 115 133 134 135 105 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\pcm.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 26</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 77</file>
</tool>
<tool>
<name>__cstat</name>
<file> 154</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 123 92 99 131 132 134 135 115 133 94 38 105 122 114 130 95 119</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 107 115 96 114 106 99 105 119 93 38 134 135 123 122 95 117 92 131 132 133 94 130</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\pmap.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 27</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 78</file>
</tool>
<tool>
<name>__cstat</name>
<file> 155</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 105 111 93 117 96 106 11 107 99 131 132 134 135 115 133 94 38</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 96 94 133 93 106 107 115 134 135 111 99 117 131 132 38 105</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\pss.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 28</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 79</file>
</tool>
<tool>
<name>__cstat</name>
<file> 156</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 124 99 131 132 134 135 115 133 94 38 92 122 105 119</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 133 99 93 119 122 117 115 134 135 96 92 124 105 106 107 131 132 38 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\ref_a.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 29</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 80</file>
</tool>
<tool>
<name>__cstat</name>
<file> 157</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 103 99 131 93 117 96 106 11 107 132 134 135 115 133 94 38 92 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 115 96 94 92 133 106 107 105 99 93 131 132 38 117 134 135 103</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\reset.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 30</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 81</file>
</tool>
<tool>
<name>__cstat</name>
<file> 158</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 125 99 131 93 117 96 106 11 107 132 134 135 115 133 94 38 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 107 93 133 106 115 96 105 99 131 132 38 117 134 135 125 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\rtc_c.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 31</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 82</file>
</tool>
<tool>
<name>__cstat</name>
<file> 159</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 95 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 133 93 105 92 117 115 134 135 96 94 122 99 106 107 131 132 38 95</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\spi.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 32</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 83</file>
</tool>
<tool>
<name>__cstat</name>
<file> 160</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 127 92 93 117 96 106 11 107 99 131 132 134 135 115 133 94 38 100 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 100 117 93 133 96 105 131 132 134 135 99 122 92 106 107 115 38 127 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\systick.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 33</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 84</file>
</tool>
<tool>
<name>__cstat</name>
<file> 161</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 105 122 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 113</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 133 93 113 92 117 115 134 135 96 122 99 106 107 131 132 38 94 105</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\timer32.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 34</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 85</file>
</tool>
<tool>
<name>__cstat</name>
<file> 162</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 128 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 96 93 105 99 106 107 131 132 38 94 122 92 117 115 133 134 135 128</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\timer_a.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 35</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 86</file>
</tool>
<tool>
<name>__cstat</name>
<file> 163</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 104 93 117 96 106 11 107 99 131 132 134 135 115 133 94 38 92 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 134 135 107 115 92 106 105 93 96 38 122 99 117 131 132 133 104 94</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\uart.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 36</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 87</file>
</tool>
<tool>
<name>__cstat</name>
<file> 164</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 129 93 117 96 106 11 107 92 99 131 132 134 135 115 133 94 38 100 122 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 38 92 94 105 100 117 115 122 93 99 96 106 107 131 132 133 129 134 135</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\wdt_a.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 37</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 88</file>
</tool>
<tool>
<name>__cstat</name>
<file> 165</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 93 117 96 106 11 107 116 101 99 131 132 134 135 115 133 94 38 92 118 108 119 91 120 109 122 100 102 121 110 97 123 111 124 103 125 112 126 95 127 113 128 104 129 114 130 98 105</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 92 93 111 107 109 113 99 106 108 110 112 114 115 100 105 96 101 91 102 97 103 95 104 98 38 94 122 116 117 118 119 120 121 123 124 125 126 127 128 129 130 131 132 133 134 135</file>
</tool>
</inputs>
</file>
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>IARCHIVE</tool>
</forcedrebuild>
</configuration>
<configuration>
<name>Release</name>
<outputs />
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>ILINK</tool>
</forcedrebuild>
</configuration>
</project>

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7
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@ -0,0 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\msp432_driverlib.ewp</path>
</project>
<batchBuild />
</workspace>

30
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/interrupt.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/interrupt.c Executable file → Normal file
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@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,10 +33,10 @@
#include <stdint.h>
/* DriverLib Includes */
#include <debug.h>
#include <cpu.h>
#include <interrupt.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/cpu.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
//*****************************************************************************
//
@ -139,10 +134,10 @@ static void IntDefaultHandler(void)
// address given in the corresponding location in this list.
//
//*****************************************************************************
#if defined(ewarm)
#if defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) @ "VTABLE";
#elif defined(ccs)
#elif defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
void (*g_pfnRAMVectors[NUM_INTERRUPTS + 1])(void);
@ -233,7 +228,14 @@ void Interrupt_setPriorityGrouping(uint32_t bits)
//
// Set the priority grouping.
//
SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits];
uint32_t reg_value;
uint32_t PriorityGroupTmp = g_pulPriority[bits];
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
uint32_t Interrupt_getPriorityGrouping(void)

22
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/interrupt.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/interrupt.h Executable file → Normal file
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@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -58,7 +53,7 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/******************************************************************************
* NVIC interrupts *
@ -116,8 +111,9 @@ extern "C"
#define INT_PORT4 (54) /* PORT4 IRQ */
#define INT_PORT5 (55) /* PORT5 IRQ */
#define INT_PORT6 (56) /* PORT6 IRQ */
#define INT_LCD_F (57) /* PORT6 IRQ */
#define NUM_INTERRUPTS (56)
#define NUM_INTERRUPTS (57)
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
@ -215,7 +211,7 @@ extern bool Interrupt_disableMaster(void);
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
//! \note This function is only used if the customer wants to specify the
//! \note This function is only used if the customer wants to specify the
//! interrupt handler at run time. In most cases, this is done through means
//! of the user setting the ISR function pointer in the startup file. Refer
//! Refer to the Module Operation section for more details.
@ -295,11 +291,7 @@ extern uint32_t Interrupt_getPriorityGrouping(void);
//!
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the MSP432 family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
//! hardware priority mechanism on a future part. This arrangement allows
//! priorities to migrate to different NVIC implementations without changing
//! the gross prioritization of the interrupts.
//! prioritization must be performed in those bits.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter

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@ -0,0 +1,540 @@
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739
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/keil/msp432_driverlib.uvprojx Normal file
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<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>1</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>../../../../../;../../../../../third_party/CMSIS/Include/;../../../../../ti/devices/msp432p4xx/inc/</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Shared Peripherals</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>2</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<VariousControls>
<MiscControls></MiscControls>
<Define>__MSP432P401R__</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>adc14.c</FileName>
<FileType>1</FileType>
<FilePath>..\adc14.c</FilePath>
</File>
<File>
<FileName>aes256.c</FileName>
<FileType>1</FileType>
<FilePath>..\aes256.c</FilePath>
</File>
<File>
<FileName>comp_e.c</FileName>
<FileType>1</FileType>
<FilePath>..\comp_e.c</FilePath>
</File>
<File>
<FileName>cpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\cpu.c</FilePath>
</File>
<File>
<FileName>crc32.c</FileName>
<FileType>1</FileType>
<FilePath>..\crc32.c</FilePath>
</File>
<File>
<FileName>cs.c</FileName>
<FileType>1</FileType>
<FilePath>..\cs.c</FilePath>
</File>
<File>
<FileName>dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\dma.c</FilePath>
</File>
<File>
<FileName>fpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\fpu.c</FilePath>
</File>
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\gpio.c</FilePath>
</File>
<File>
<FileName>i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\i2c.c</FilePath>
</File>
<File>
<FileName>interrupt.c</FileName>
<FileType>1</FileType>
<FilePath>..\interrupt.c</FilePath>
</File>
<File>
<FileName>mpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\mpu.c</FilePath>
</File>
<File>
<FileName>pcm.c</FileName>
<FileType>1</FileType>
<FilePath>..\pcm.c</FilePath>
</File>
<File>
<FileName>pmap.c</FileName>
<FileType>1</FileType>
<FilePath>..\pmap.c</FilePath>
</File>
<File>
<FileName>pss.c</FileName>
<FileType>1</FileType>
<FilePath>..\pss.c</FilePath>
</File>
<File>
<FileName>ref_a.c</FileName>
<FileType>1</FileType>
<FilePath>..\ref_a.c</FilePath>
</File>
<File>
<FileName>reset.c</FileName>
<FileType>1</FileType>
<FilePath>..\reset.c</FilePath>
</File>
<File>
<FileName>rtc_c.c</FileName>
<FileType>1</FileType>
<FilePath>..\rtc_c.c</FilePath>
</File>
<File>
<FileName>spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\spi.c</FilePath>
</File>
<File>
<FileName>systick.c</FileName>
<FileType>1</FileType>
<FilePath>..\systick.c</FilePath>
</File>
<File>
<FileName>timer_a.c</FileName>
<FileType>1</FileType>
<FilePath>..\timer_a.c</FilePath>
</File>
<File>
<FileName>timer32.c</FileName>
<FileType>1</FileType>
<FilePath>..\timer32.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\uart.c</FilePath>
</File>
<File>
<FileName>wdt_a.c</FileName>
<FileType>1</FileType>
<FilePath>..\wdt_a.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>msp432p401</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>2</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<VariousControls>
<MiscControls></MiscControls>
<Define>__MSP432P401R__</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\flash.c</FilePath>
</File>
<File>
<FileName>sysctl_a.c</FileName>
<FileType>1</FileType>
<FilePath>..\sysctl_a.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>msp432p4111</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>2</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<VariousControls>
<MiscControls></MiscControls>
<Define>__MSP432P4111__</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>flash_a.c</FileName>
<FileType>1</FileType>
<FilePath>..\flash_a.c</FilePath>
</File>
<File>
<FileName>lcd_f.c</FileName>
<FileType>1</FileType>
<FilePath>..\lcd_f.c</FilePath>
</File>
<File>
<FileName>sysctl_a.c</FileName>
<FileType>1</FileType>
<FilePath>..\sysctl_a.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>

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port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/keil/msp432p4xx_driverlib.lib Normal file
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port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/lcd_f.c Normal file
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@ -0,0 +1,263 @@
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <stdint.h>
#include <ti/devices/msp432p4xx/driverlib/lcd_f.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
/* Define to ensure that our current MSP432 has the LCD_F module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_LCD_F__
/* Configuration functions */
void LCD_F_initModule(LCD_F_Config *initParams)
{
BITBAND_PERI(LCD_F->CTL,LCD_F_CTL_ON_OFS) = 0;
LCD_F->CTL = (LCD_F->CTL
& ~(LCD_F_CTL_MX_MASK | LCD_F_CTL_SSEL_MASK | LCD_F_CTL_LP
| LCD_F_CTL_ON | LCD_F_CTL_DIV_MASK | LCD_F_CTL_PRE_MASK
| LCD_F_CTL_SON))
| (initParams->muxRate | initParams->clockSource
| initParams->waveforms | initParams->segments
| initParams->clockDivider | initParams->clockPrescaler);
}
void LCD_F_turnOn(void)
{
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 1;
}
void LCD_F_turnOff(void)
{
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
}
/* Memory management functions */
void LCD_F_clearAllMemory(void)
{
BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_CLRM_OFS) = 1;
}
void LCD_F_clearAllBlinkingMemory(void)
{
BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_CLRBM_OFS) = 1;
}
void LCD_F_selectDisplayMemory(uint_fast16_t displayMemory)
{
BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_DISP_OFS) = displayMemory;
}
void LCD_F_setBlinkingControl(uint_fast16_t clockPrescalar,
uint_fast16_t divider, uint_fast16_t mode)
{
LCD_F->BMCTL = (LCD_F->BMCTL
& ~(LCD_F_BMCTL_BLKPRE_MASK | LCD_F_BMCTL_BLKDIV_MASK
| LCD_F_BMCTL_BLKMOD_MASK)) | clockPrescalar | mode
| divider;
}
void LCD_F_setAnimationControl(uint_fast16_t clockPrescalar,
uint_fast16_t divider, uint_fast16_t frames)
{
LCD_F->ANMCTL = (LCD_F->ANMCTL
& ~(LCD_F_ANMCTL_ANMPRE_MASK | LCD_F_ANMCTL_ANMDIV_MASK
| LCD_F_ANMCTL_ANMSTP_MASK)) | clockPrescalar | divider
| frames;
}
void LCD_F_enableAnimation(void)
{
BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMEN_OFS) = 1;
}
void LCD_F_disableAnimation(void)
{
BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMEN_OFS) = 0;
}
void LCD_F_clearAllAnimationMemory(void)
{
BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMCLR_OFS) = 1;
}
/* Pin Configuration Functions */
void LCD_F_setPinAsLCDFunction(uint_fast8_t pin)
{
uint32_t val = (pin & 0x1F);
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
if((pin >> 5) == 0)
{
BITBAND_PERI(LCD_F->PCTL0, val) = 1;
}
else
{
BITBAND_PERI(LCD_F->PCTL1, val) = 1;
}
}
void LCD_F_setPinAsPortFunction(uint_fast8_t pin)
{
uint32_t val = (pin & 0x1F);
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
if((pin >> 5) == 0)
{
BITBAND_PERI(LCD_F->PCTL0, val) = 0;
}
else
{
BITBAND_PERI(LCD_F->PCTL1, val) = 0;
}
}
void LCD_F_setPinsAsLCDFunction(uint_fast8_t startPin, uint8_t endPin)
{
uint32_t startIdx = startPin >> 5;
uint32_t endIdx = endPin >> 5;
uint32_t startPos = startPin & 0x1F;
uint32_t endPos = endPin & 0x1F;
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
if (startIdx == endIdx)
{
if (startIdx == 0)
{
LCD_F->PCTL0 |= (0xFFFFFFFF >> (31 - endPos))
& (0xFFFFFFFF << startPos);
} else
{
LCD_F->PCTL1 |= (0xFFFFFFFF >> (31 - endPos))
& (0xFFFFFFFF << startPos);
}
} else
{
LCD_F->PCTL0 |= (0xFFFFFFFF << startPos);
LCD_F->PCTL1 |= (0xFFFFFFFF >> (31 - endPos));
}
}
void LCD_F_setPinAsCOM(uint8_t pin, uint_fast8_t com)
{
uint32_t val = (pin & 0x1F);
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
if((pin >> 5) == 0)
{
BITBAND_PERI(LCD_F->CSSEL0, val) = 1;
}
else
{
BITBAND_PERI(LCD_F->CSSEL1, val) = 1;
}
// Setting the relevant COM pin
HWREG8(LCD_F_BASE + OFS_LCDM0W + pin) |= com;
HWREG8(LCD_F_BASE + OFS_LCDBM0W + pin) |= com;
}
void LCD_F_setPinAsSEG(uint_fast8_t pin)
{
uint32_t val = (pin & 0x1F);
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
if((pin >> 5) == 0)
{
BITBAND_PERI(LCD_F->CSSEL0, val) = 0;
}
else
{
BITBAND_PERI(LCD_F->CSSEL1, val) = 0;
}
}
void LCD_F_selectBias(uint_fast16_t bias)
{
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
LCD_F->VCTL = (LCD_F->VCTL & ~LCD_F_VCTL_LCD2B) | bias;
}
void LCD_F_setVLCDSource(uint_fast16_t v2v3v4Source, uint_fast16_t v5Source)
{
BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
LCD_F->VCTL = (LCD_F->VCTL
& ~(LCD_F_VCTL_REXT | LCD_F_VCTL_EXTBIAS
| LCD_F_VCTL_R03EXT)) | v2v3v4Source | v5Source;
}
/* Interrupt Management */
void LCD_F_clearInterrupt(uint32_t mask)
{
LCD_F->CLRIFG |= mask;
}
uint32_t LCD_F_getInterruptStatus(void)
{
return LCD_F->IFG;
}
uint32_t LCD_F_getEnabledInterruptStatus(void)
{
uint32_t tempIE = LCD_F->IE;
return (LCD_F->IFG & tempIE);
}
void LCD_F_enableInterrupt(uint32_t mask)
{
LCD_F->IE |= mask;
}
void LCD_F_disableInterrupt(uint32_t mask)
{
LCD_F->IE &= ~mask;
}
void LCD_F_registerInterrupt(void (*intHandler)(void))
{
Interrupt_registerInterrupt(INT_LCD_F, intHandler);
Interrupt_enableInterrupt(INT_LCD_F);
}
void LCD_F_unregisterInterrupt(void)
{
Interrupt_disableInterrupt(INT_LCD_F);
Interrupt_unregisterInterrupt(INT_LCD_F);
}
#endif /* __MCU_HAS_LCD_F__ */

1203
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/lcd_f.h Normal file
View File

File diff suppressed because it is too large Load Diff

15
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/mpu.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/mpu.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,9 +29,9 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <debug.h>
#include <interrupt.h>
#include <mpu.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/mpu.h>
void MPU_enableModule(uint32_t mpuConfig)
{

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/mpu.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/mpu.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -56,7 +51,7 @@ extern "C"
{
#endif
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdint.h>
//*****************************************************************************

39
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/pcm.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/pcm.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,12 +33,12 @@
#include <stdint.h>
/* DriverLib Includes */
#include <pcm.h>
#include <debug.h>
#include <interrupt.h>
#include <wdt_a.h>
#include <rtc_c.h>
#include <cpu.h>
#include <ti/devices/msp432p4xx/driverlib/pcm.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/wdt_a.h>
#include <ti/devices/msp432p4xx/driverlib/rtc_c.h>
#include <ti/devices/msp432p4xx/driverlib/cpu.h>
static bool __PCM_setCoreVoltageLevelAdvanced(uint_fast8_t voltageLevel,
uint32_t timeOut, bool blocking)
@ -405,7 +400,7 @@ bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState)
bool PCM_shutdownDevice(uint32_t shutdownMode)
{
uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ?
PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
ASSERT(
shutdownMode == PCM_SHUTDOWN_PARTIAL
@ -440,7 +435,7 @@ bool PCM_gotoLPM4InterruptSafe(void)
{
bool slHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
@ -472,7 +467,7 @@ bool PCM_gotoLPM0InterruptSafe(void)
{
bool slHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
@ -498,13 +493,13 @@ bool PCM_gotoLPM3(void)
/* If we are in the middle of a shutdown, return false */
if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
|| (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
|| (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
return false;
currentPowerMode = PCM_getPowerMode();
bCurrentPowerState = PCM_getPowerState();
if (currentPowerMode == PCM_DCDC_MODE || currentPowerMode == PCM_LF_MODE)
if (currentPowerMode == PCM_DCDC_MODE)
PCM_setPowerMode(PCM_LDO_MODE);
/* Clearing the SDR */
@ -524,7 +519,7 @@ bool PCM_gotoLPM3InterruptSafe(void)
{
bool lpmHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
@ -541,20 +536,20 @@ bool PCM_gotoLPM3InterruptSafe(void)
uint8_t PCM_getPowerState(void)
{
return (PCM->CTL0 | PCM_CTL0_CPM_MASK);
return (PCM->CTL0 & PCM_CTL0_CPM_MASK) >> PCM_CTL0_CPM_OFS;
}
void PCM_enableRudeMode(void)
{
PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK)) | PCM_KEY
| PCM_CTL1_FORCE_LPM_ENTRY;
| PCM_CTL1_FORCE_LPM_ENTRY;
}
void PCM_disableRudeMode(void)
{
PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK | PCM_CTL1_FORCE_LPM_ENTRY))
| PCM_KEY;
| PCM_KEY;
}
void PCM_enableInterrupt(uint32_t flags)

41
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/pcm.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/pcm.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,11 +52,11 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
// Control specific variables
// Control specific variables
//
//*****************************************************************************
#define PCM_KEY 0x695A0000
@ -419,7 +414,7 @@ extern bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState);
//! - \b PCM_LPM45
//!
//!
//! \return false if shutdown state cannot be entered, true otherwise.
//! \return false if LPM state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_shutdownDevice(uint32_t shutdownMode);
@ -430,7 +425,7 @@ extern bool PCM_shutdownDevice(uint32_t shutdownMode);
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//! \return false if LPM0 state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM0(void);
@ -441,10 +436,10 @@ extern bool PCM_gotoLPM0(void);
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//! Note that since LPM3 cannot be entered from a DCDC power modes, the
//! power mode is first switched to LDO operation (if in DCDC mode), the deep
//! sleep is entered, and the DCDC mode is restored on wake up.
//! power mode is first switched to LDO operation (if in DCDC mode),
//! LPM3 is entered, and the DCDC mode is restored on wake up.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//! \return false if LPM3 state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM3(void);
@ -453,14 +448,14 @@ extern bool PCM_gotoLPM3(void);
//
//! Transitions the device into LPM0 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to sleep, however does not want
//! situations where the user wants to go to LPM0, however does not want
//! to go to "miss" any interrupts due to the fact that going to LPM0 is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//! \return false if LPM0 state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM0InterruptSafe(void);
@ -476,10 +471,10 @@ extern bool PCM_gotoLPM0InterruptSafe(void);
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//! Note that since LPM3 cannot be entered from a DCDC power modes, the
//! power mode is first switched to LDO operation (if in DCDC mode), the deep
//! sleep is entered, and the DCDC mode is restored on wake up.
//! power mode is first switched to LDO operation (if in DCDC mode), the LPM3
//! is entered, and the DCDC mode is restored on wake up.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//! \return false if LPM3 cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM3InterruptSafe(void);
@ -490,7 +485,7 @@ extern bool PCM_gotoLPM3InterruptSafe(void);
//! with RTC_C and WDT_A disabled. When waking up, RTC_C and WDT_A will remain
//! disabled until reconfigured by the user.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//! \return false if LPM4 state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM4(void);
@ -506,10 +501,10 @@ extern bool PCM_gotoLPM4(void);
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//! Note that since LPM3 cannot be entered from a DCDC power modes, the
//! power mode is first switched to LDO operation (if in DCDC mode), the deep
//! sleep is entered, and the DCDC mode is restored on wake up.
//! power mode is first switched to LDO operation (if in DCDC mode),
//! LPM4 is entered, and the DCDC mode is restored on wake up.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//! \return false if LPM4 state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM4InterruptSafe(void);

17
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/pmap.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/pmap.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,9 +29,9 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <debug.h>
#include <pmap.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/pmap.h>
void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
uint8_t numberOfPorts, uint8_t portMapReconfigure)
@ -54,7 +49,7 @@ void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
PMAP->CTL = (PMAP->CTL & ~PMAP_CTL_PRECFG) | portMapReconfigure;
//Configure Port Mapping:
for (i = 0; i < numberOfPorts * 8; i++)
{
HWREG8(PMAP_BASE + i + pxMAPy) = portMapping[i];

13
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/pmap.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/pmap.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -56,7 +51,7 @@ extern "C"
#endif
#include <stdint.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
@ -70,7 +65,7 @@ extern "C"
//*****************************************************************************
//
//The following are values that can be passed to the PMAP_configurePorts() API
//as the portMapReconfigure parameter.
//as the pxMAPy parameter.
//
//*****************************************************************************
#define PMAP_P1MAP ((uint32_t)P1MAP - PMAP_BASE)

21
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/pss.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/pss.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,10 +33,10 @@
#include <stdint.h>
/* DriverLib Includes */
#include <pss.h>
#include <interrupt.h>
#include <debug.h>
#include <cpu.h>
#include <ti/devices/msp432p4xx/driverlib/pss.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/cpu.h>
static void __PSSUnlock()
{
@ -168,7 +163,7 @@ void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage)
uint_fast8_t PSS_getHighSideVoltageTrigger(void)
{
return (uint_fast8_t)((PSS->CTL0 & PSS_CTL0_SVSMHTH_MASK)
>> PSS_CTL0_SVSMHTH_OFS);
>> PSS_CTL0_SVSMHTH_OFS);
}
void PSS_enableInterrupt(void)
@ -193,7 +188,7 @@ uint32_t PSS_getInterruptStatus(void)
void PSS_clearInterruptFlag(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->CLRIFG,PSS_CLRIFG_CLRSVSMHIFG_OFS) = 0;
BITBAND_PERI(PSS->CLRIFG,PSS_CLRIFG_CLRSVSMHIFG_OFS) = 1;
__PSSLock();
}

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/pss.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/pss.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -56,7 +51,7 @@ extern "C"
#endif
#include <stdint.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdbool.h>
//*****************************************************************************

13
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/ref_a.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/ref_a.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,8 +29,8 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <ref_a.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/ref_a.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect)
{

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/ref_a.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/ref_a.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -44,7 +39,7 @@
//
//*****************************************************************************
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdbool.h>
#include <stdint.h>

13
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/reset.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/reset.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,8 +29,8 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <reset.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/reset.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
void ResetCtl_initiateSoftReset(void)
{

23
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/reset.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/reset.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -55,12 +50,12 @@ extern "C"
{
#endif
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdint.h>
//*****************************************************************************
//
// Control specific variables
// Control specific variables
//
//*****************************************************************************
#define RESET_KEY 0x6900
@ -84,12 +79,12 @@ extern "C"
#define RESET_SRC_14 RSTCTL_HARDRESET_CLR_SRC14
#define RESET_SRC_15 RSTCTL_HARDRESET_CLR_SRC15
#define RESET_VCCDET RSTCTL_PSSRESET_CLR_BGREF
#define RESET_SVSH_TRIP RSTCTL_PSSRESET_CLR_SVSMH
#define RESET_BGREF_BAD RSTCTL_PSSRESET_CLR_BGREF
#define RESET_VCCDET RSTCTL_PSSRESET_STAT_VCCDET
#define RESET_SVSH_TRIP RSTCTL_PSSRESET_STAT_SVSMH
#define RESET_BGREF_BAD RSTCTL_PSSRESET_STAT_BGREF
#define RESET_LPM35 RSTCTL_PCMRESET_CLR_LPM35
#define RESET_LPM45 RSTCTL_PCMRESET_CLR_LPM45
#define RESET_LPM35 RSTCTL_PCMRESET_STAT_LPM35
#define RESET_LPM45 RSTCTL_PCMRESET_STAT_LPM45
//*****************************************************************************
//

2689
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/rom.h Normal file
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File diff suppressed because it is too large Load Diff

633
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/rom_map.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/rom_map.h
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@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,17 +29,6 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
//*****************************************************************************
//
// rom_map.h - Macros to facilitate calling functions in the ROM when they are
// available and in flash otherwise.
//
// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
// TI Information - Selective Disclosure
//
//
//*****************************************************************************
#ifndef __ROM_MAP_H__
#define __ROM_MAP_H__
@ -1083,6 +1067,13 @@
// Macros for the Flash API.
//
//*****************************************************************************
#ifdef ROM_FlashCtl_enableReadParityCheck
#define MAP_FlashCtl_enableReadParityCheck \
ROM_FlashCtl_enableReadParityCheck
#else
#define MAP_FlashCtl_enableReadParityCheck \
FlashCtl_enableReadParityCheck
#endif
#ifdef ROM_FlashCtl_disableReadParityCheck
#define MAP_FlashCtl_disableReadParityCheck \
ROM_FlashCtl_disableReadParityCheck
@ -1591,6 +1582,13 @@
#define MAP_I2C_setMode \
I2C_setMode
#endif
#ifdef ROM_I2C_setTimeout
#define MAP_I2C_setTimeout \
ROM_I2C_setTimeout
#else
#define MAP_I2C_setTimeout \
I2C_setTimeout
#endif
#ifdef ROM_I2C_slavePutData
#define MAP_I2C_slavePutData \
ROM_I2C_slavePutData
@ -2314,6 +2312,20 @@
#define MAP_PSS_disableHighSide \
PSS_disableHighSide
#endif
#ifdef ROM_PSS_enableLowSide
#define MAP_PSS_enableLowSide \
ROM_PSS_enableLowSide
#else
#define MAP_PSS_enableLowSide \
PSS_enableLowSide
#endif
#ifdef ROM_PSS_disableLowSide
#define MAP_PSS_disableLowSide \
ROM_PSS_disableLowSide
#else
#define MAP_PSS_disableLowSide \
PSS_disableLowSide
#endif
#ifdef ROM_PSS_setHighSidePerformanceMode
#define MAP_PSS_setHighSidePerformanceMode \
ROM_PSS_setHighSidePerformanceMode
@ -2328,6 +2340,20 @@
#define MAP_PSS_getHighSidePerformanceMode \
PSS_getHighSidePerformanceMode
#endif
#ifdef ROM_PSS_setLowSidePerformanceMode
#define MAP_PSS_setLowSidePerformanceMode \
ROM_PSS_setLowSidePerformanceMode
#else
#define MAP_PSS_setLowSidePerformanceMode \
PSS_setLowSidePerformanceMode
#endif
#ifdef ROM_PSS_getLowSidePerformanceMode
#define MAP_PSS_getLowSidePerformanceMode \
ROM_PSS_getLowSidePerformanceMode
#else
#define MAP_PSS_getLowSidePerformanceMode \
PSS_getLowSidePerformanceMode
#endif
#ifdef ROM_PSS_enableHighSideMonitor
#define MAP_PSS_enableHighSideMonitor \
ROM_PSS_enableHighSideMonitor
@ -3607,4 +3633,575 @@
WDT_A_setTimeoutReset
#endif
//*****************************************************************************
//
// Macros for the SysCtl_A API.
//
//*****************************************************************************
#ifdef ROM_SysCtl_A_getSRAMSize
#define MAP_SysCtl_A_getSRAMSize \
ROM_SysCtl_A_getSRAMSize
#else
#define MAP_SysCtl_A_getSRAMSize \
SysCtl_A_getSRAMSize
#endif
#ifdef ROM_SysCtl_A_getFlashSize
#define MAP_SysCtl_A_getFlashSize \
ROM_SysCtl_A_getFlashSize
#else
#define MAP_SysCtl_A_getFlashSize \
SysCtl_A_getFlashSize
#endif
#ifdef ROM_SysCtl_A_rebootDevice
#define MAP_SysCtl_A_rebootDevice \
ROM_SysCtl_A_rebootDevice
#else
#define MAP_SysCtl_A_rebootDevice \
SysCtl_A_rebootDevice
#endif
#ifdef ROM_SysCtl_A_enableSRAM
#define MAP_SysCtl_A_enableSRAM \
ROM_SysCtl_A_enableSRAM
#else
#define MAP_SysCtl_A_enableSRAM \
SysCtl_A_enableSRAM
#endif
#ifdef ROM_SysCtl_A_disableSRAM
#define MAP_SysCtl_A_disableSRAM \
ROM_SysCtl_A_disableSRAM
#else
#define MAP_SysCtl_A_disableSRAM \
SysCtl_A_disableSRAM
#endif
#ifdef ROM_SysCtl_A_enableSRAMRetention
#define MAP_SysCtl_A_enableSRAMRetention \
ROM_SysCtl_A_enableSRAMRetention
#else
#define MAP_SysCtl_A_enableSRAMRetention \
SysCtl_A_enableSRAMRetention
#endif
#ifdef ROM_SysCtl_A_disableSRAMRetention
#define MAP_SysCtl_A_disableSRAMRetention \
ROM_SysCtl_A_disableSRAMRetention
#else
#define MAP_SysCtl_A_disableSRAMRetention \
SysCtl_A_disableSRAMRetention
#endif
#ifdef ROM_SysCtl_A_enablePeripheralAtCPUHalt
#define MAP_SysCtl_A_enablePeripheralAtCPUHalt \
ROM_SysCtl_A_enablePeripheralAtCPUHalt
#else
#define MAP_SysCtl_A_enablePeripheralAtCPUHalt \
SysCtl_A_enablePeripheralAtCPUHalt
#endif
#ifdef ROM_SysCtl_A_disablePeripheralAtCPUHalt
#define MAP_SysCtl_A_disablePeripheralAtCPUHalt \
ROM_SysCtl_A_disablePeripheralAtCPUHalt
#else
#define MAP_SysCtl_A_disablePeripheralAtCPUHalt \
SysCtl_A_disablePeripheralAtCPUHalt
#endif
#ifdef ROM_SysCtl_A_setWDTTimeoutResetType
#define MAP_SysCtl_A_setWDTTimeoutResetType \
ROM_SysCtl_A_setWDTTimeoutResetType
#else
#define MAP_SysCtl_A_setWDTTimeoutResetType \
SysCtl_A_setWDTTimeoutResetType
#endif
#ifdef ROM_SysCtl_A_setWDTPasswordViolationResetType
#define MAP_SysCtl_A_setWDTPasswordViolationResetType \
ROM_SysCtl_A_setWDTPasswordViolationResetType
#else
#define MAP_SysCtl_A_setWDTPasswordViolationResetType \
SysCtl_A_setWDTPasswordViolationResetType
#endif
#ifdef ROM_SysCtl_A_disableNMISource
#define MAP_SysCtl_A_disableNMISource \
ROM_SysCtl_A_disableNMISource
#else
#define MAP_SysCtl_A_disableNMISource \
SysCtl_A_disableNMISource
#endif
#ifdef ROM_SysCtl_A_enableNMISource
#define MAP_SysCtl_A_enableNMISource \
ROM_SysCtl_A_enableNMISource
#else
#define MAP_SysCtl_A_enableNMISource \
SysCtl_A_enableNMISource
#endif
#ifdef ROM_SysCtl_A_getNMISourceStatus
#define MAP_SysCtl_A_getNMISourceStatus \
ROM_SysCtl_A_getNMISourceStatus
#else
#define MAP_SysCtl_A_getNMISourceStatus \
SysCtl_A_getNMISourceStatus
#endif
#ifdef ROM_SysCtl_A_getTempCalibrationConstant
#define MAP_SysCtl_A_getTempCalibrationConstant \
ROM_SysCtl_A_getTempCalibrationConstant
#else
#define MAP_SysCtl_A_getTempCalibrationConstant \
SysCtl_A_getTempCalibrationConstant
#endif
#ifdef ROM_SysCtl_A_enableGlitchFilter
#define MAP_SysCtl_A_enableGlitchFilter \
ROM_SysCtl_A_enableGlitchFilter
#else
#define MAP_SysCtl_A_enableGlitchFilter \
SysCtl_A_enableGlitchFilter
#endif
#ifdef ROM_SysCtl_A_disableGlitchFilter
#define MAP_SysCtl_A_disableGlitchFilter \
ROM_SysCtl_A_disableGlitchFilter
#else
#define MAP_SysCtl_A_disableGlitchFilter \
SysCtl_A_disableGlitchFilter
#endif
#ifdef ROM_SysCtl_A_getTLVInfo
#define MAP_SysCtl_A_getTLVInfo \
ROM_SysCtl_A_getTLVInfo
#else
#define MAP_SysCtl_A_getTLVInfo \
SysCtl_A_getTLVInfo
#endif
#ifdef ROM_SysCtl_A_getInfoFlashSize
#define MAP_SysCtl_A_getInfoFlashSize \
ROM_SysCtl_A_getInfoFlashSize
#else
#define MAP_SysCtl_A_getInfoFlashSize \
SysCtl_A_getInfoFlashSize
#endif
//*****************************************************************************
//
// Macros for the Flash_A API.
//
//*****************************************************************************
#ifdef ROM_FlashCtl_A_enableReadParityCheck
#define MAP_FlashCtl_A_enableReadParityCheck \
ROM_FlashCtl_A_enableReadParityCheck
#else
#define MAP_FlashCtl_A_enableReadParityCheck \
FlashCtl_A_enableReadParityCheck
#endif
#ifdef ROM_FlashCtl_A_disableReadParityCheck
#define MAP_FlashCtl_A_disableReadParityCheck \
ROM_FlashCtl_A_disableReadParityCheck
#else
#define MAP_FlashCtl_A_disableReadParityCheck \
FlashCtl_A_disableReadParityCheck
#endif
#ifdef ROM_FlashCtl_A_enableReadBuffering
#define MAP_FlashCtl_A_enableReadBuffering \
ROM_FlashCtl_A_enableReadBuffering
#else
#define MAP_FlashCtl_A_enableReadBuffering \
FlashCtl_A_enableReadBuffering
#endif
#ifdef ROM_FlashCtl_A_disableReadBuffering
#define MAP_FlashCtl_A_disableReadBuffering \
ROM_FlashCtl_A_disableReadBuffering
#else
#define MAP_FlashCtl_A_disableReadBuffering \
FlashCtl_A_disableReadBuffering
#endif
#ifdef ROM_FlashCtl_A_unprotectMemory
#define MAP_FlashCtl_A_unprotectMemory \
ROM_FlashCtl_A_unprotectMemory
#else
#define MAP_FlashCtl_A_unprotectMemory \
FlashCtl_A_unprotectMemory
#endif
#ifdef ROM_FlashCtl_A_protectMemory
#define MAP_FlashCtl_A_protectMemory \
ROM_FlashCtl_A_protectMemory
#else
#define MAP_FlashCtl_A_protectMemory \
FlashCtl_A_protectMemory
#endif
#ifdef ROM_FlashCtl_A_isMemoryRangeProtected
#define MAP_FlashCtl_A_isMemoryRangeProtected \
ROM_FlashCtl_A_isMemoryRangeProtected
#else
#define MAP_FlashCtl_A_isMemoryRangeProtected \
FlashCtl_A_isMemoryRangeProtected
#endif
#ifdef ROM_FlashCtl_A_verifyMemory
#define MAP_FlashCtl_A_verifyMemory \
ROM_FlashCtl_A_verifyMemory
#else
#define MAP_FlashCtl_A_verifyMemory \
FlashCtl_A_verifyMemory
#endif
#ifdef ROM_FlashCtl_A_performMassErase
#define MAP_FlashCtl_A_performMassErase \
ROM_FlashCtl_A_performMassErase
#else
#define MAP_FlashCtl_A_performMassErase \
FlashCtl_A_performMassErase
#endif
#ifdef ROM_FlashCtl_A_eraseSector
#define MAP_FlashCtl_A_eraseSector \
ROM_FlashCtl_A_eraseSector
#else
#define MAP_FlashCtl_A_eraseSector \
FlashCtl_A_eraseSector
#endif
#ifdef ROM_FlashCtl_A_programMemory
#define MAP_FlashCtl_A_programMemory \
ROM_FlashCtl_A_programMemory
#else
#define MAP_FlashCtl_A_programMemory \
FlashCtl_A_programMemory
#endif
#ifdef ROM_FlashCtl_A_setProgramVerification
#define MAP_FlashCtl_A_setProgramVerification \
ROM_FlashCtl_A_setProgramVerification
#else
#define MAP_FlashCtl_A_setProgramVerification \
FlashCtl_A_setProgramVerification
#endif
#ifdef ROM_FlashCtl_A_clearProgramVerification
#define MAP_FlashCtl_A_clearProgramVerification \
ROM_FlashCtl_A_clearProgramVerification
#else
#define MAP_FlashCtl_A_clearProgramVerification \
FlashCtl_A_clearProgramVerification
#endif
#ifdef ROM_FlashCtl_A_enableWordProgramming
#define MAP_FlashCtl_A_enableWordProgramming \
ROM_FlashCtl_A_enableWordProgramming
#else
#define MAP_FlashCtl_A_enableWordProgramming \
FlashCtl_A_enableWordProgramming
#endif
#ifdef ROM_FlashCtl_A_disableWordProgramming
#define MAP_FlashCtl_A_disableWordProgramming \
ROM_FlashCtl_A_disableWordProgramming
#else
#define MAP_FlashCtl_A_disableWordProgramming \
FlashCtl_A_disableWordProgramming
#endif
#ifdef ROM_FlashCtl_A_isWordProgrammingEnabled
#define MAP_FlashCtl_A_isWordProgrammingEnabled \
ROM_FlashCtl_A_isWordProgrammingEnabled
#else
#define MAP_FlashCtl_A_isWordProgrammingEnabled \
FlashCtl_A_isWordProgrammingEnabled
#endif
#ifdef ROM_FlashCtl_A_enableInterrupt
#define MAP_FlashCtl_A_enableInterrupt \
ROM_FlashCtl_A_enableInterrupt
#else
#define MAP_FlashCtl_A_enableInterrupt \
FlashCtl_A_enableInterrupt
#endif
#ifdef ROM_FlashCtl_A_disableInterrupt
#define MAP_FlashCtl_A_disableInterrupt \
ROM_FlashCtl_A_disableInterrupt
#else
#define MAP_FlashCtl_A_disableInterrupt \
FlashCtl_A_disableInterrupt
#endif
#ifdef ROM_FlashCtl_A_getEnabledInterruptStatus
#define MAP_FlashCtl_A_getEnabledInterruptStatus \
ROM_FlashCtl_A_getEnabledInterruptStatus
#else
#define MAP_FlashCtl_A_getEnabledInterruptStatus \
FlashCtl_A_getEnabledInterruptStatus
#endif
#ifdef ROM_FlashCtl_A_getInterruptStatus
#define MAP_FlashCtl_A_getInterruptStatus \
ROM_FlashCtl_A_getInterruptStatus
#else
#define MAP_FlashCtl_A_getInterruptStatus \
FlashCtl_A_getInterruptStatus
#endif
#ifdef ROM_FlashCtl_A_clearInterruptFlag
#define MAP_FlashCtl_A_clearInterruptFlag \
ROM_FlashCtl_A_clearInterruptFlag
#else
#define MAP_FlashCtl_A_clearInterruptFlag \
FlashCtl_A_clearInterruptFlag
#endif
#ifdef ROM_FlashCtl_A_setWaitState
#define MAP_FlashCtl_A_setWaitState \
ROM_FlashCtl_A_setWaitState
#else
#define MAP_FlashCtl_A_setWaitState \
FlashCtl_A_setWaitState
#endif
#ifdef ROM_FlashCtl_A_getWaitState
#define MAP_FlashCtl_A_getWaitState \
ROM_FlashCtl_A_getWaitState
#else
#define MAP_FlashCtl_A_getWaitState \
FlashCtl_A_getWaitState
#endif
#ifdef ROM_FlashCtl_A_setReadMode
#define MAP_FlashCtl_A_setReadMode \
ROM_FlashCtl_A_setReadMode
#else
#define MAP_FlashCtl_A_setReadMode \
FlashCtl_A_setReadMode
#endif
#ifdef ROM_FlashCtl_A_getReadMode
#define MAP_FlashCtl_A_getReadMode \
ROM_FlashCtl_A_getReadMode
#else
#define MAP_FlashCtl_A_getReadMode \
FlashCtl_A_getReadMode
#endif
#ifdef ROM_FlashCtl_A_registerInterrupt
#define MAP_FlashCtl_A_registerInterrupt \
ROM_FlashCtl_A_registerInterrupt
#else
#define MAP_FlashCtl_A_registerInterrupt \
FlashCtl_A_registerInterrupt
#endif
#ifdef ROM_FlashCtl_A_unregisterInterrupt
#define MAP_FlashCtl_A_unregisterInterrupt \
ROM_FlashCtl_A_unregisterInterrupt
#else
#define MAP_FlashCtl_A_unregisterInterrupt \
FlashCtl_A_unregisterInterrupt
#endif
#ifdef ROM___FlashCtl_A_remaskData8Post
#define MAP___FlashCtl_A_remaskData8Post \
ROM___FlashCtl_A_remaskData8Post
#else
#define MAP___FlashCtl_A_remaskData8Post \
__FlashCtl_A_remaskData8Post
#endif
#ifdef ROM___FlashCtl_A_remaskData8Pre
#define MAP___FlashCtl_A_remaskData8Pre \
ROM___FlashCtl_A_remaskData8Pre
#else
#define MAP___FlashCtl_A_remaskData8Pre \
__FlashCtl_A_remaskData8Pre
#endif
#ifdef ROM___FlashCtl_A_remaskData32Pre
#define MAP___FlashCtl_A_remaskData32Pre \
ROM___FlashCtl_A_remaskData32Pre
#else
#define MAP___FlashCtl_A_remaskData32Pre \
__FlashCtl_A_remaskData32Pre
#endif
#ifdef ROM___FlashCtl_A_remaskData32Post
#define MAP___FlashCtl_A_remaskData32Post \
ROM___FlashCtl_A_remaskData32Post
#else
#define MAP___FlashCtl_A_remaskData32Post \
__FlashCtl_A_remaskData32Post
#endif
#ifdef ROM___FlashCtl_A_remaskBurstDataPre
#define MAP___FlashCtl_A_remaskBurstDataPre \
ROM___FlashCtl_A_remaskBurstDataPre
#else
#define MAP___FlashCtl_A_remaskBurstDataPre \
__FlashCtl_A_remaskBurstDataPre
#endif
#ifdef ROM___FlashCtl_A_remaskBurstDataPost
#define MAP___FlashCtl_A_remaskBurstDataPost \
ROM___FlashCtl_A_remaskBurstDataPost
#else
#define MAP___FlashCtl_A_remaskBurstDataPost \
__FlashCtl_A_remaskBurstDataPost
#endif
#ifdef ROM_FlashCtl_A_initiateSectorErase
#define MAP_FlashCtl_A_initiateSectorErase \
ROM_FlashCtl_A_initiateSectorErase
#else
#define MAP_FlashCtl_A_initiateSectorErase \
FlashCtl_A_initiateSectorErase
#endif
#ifdef ROM_FlashCtl_A_initiateMassErase
#define MAP_FlashCtl_A_initiateMassErase \
ROM_FlashCtl_A_initiateMassErase
#else
#define MAP_FlashCtl_A_initiateMassErase \
FlashCtl_A_initiateMassErase
#endif
#ifdef ROM_FlashCtl_A_isMemoryProtected
#define MAP_FlashCtl_A_isMemoryProtected \
ROM_FlashCtl_A_isMemoryProtected
#else
#define MAP_FlashCtl_A_isMemoryProtected \
FlashCtl_A_isMemoryProtected
#endif
#ifdef ROM_FlashCtl_A_getMemoryInfo
#define MAP_FlashCtl_A_getMemoryInfo \
ROM_FlashCtl_A_getMemoryInfo
#else
#define MAP_FlashCtl_A_getMemoryInfo \
FlashCtl_A_getMemoryInfo
#endif
//*****************************************************************************
//
// Macros for the LCD_F API.
//
//*****************************************************************************
#ifdef ROM_LCD_F_initModule
#define MAP_LCD_F_initModule \
ROM_LCD_F_initModule
#else
#define MAP_LCD_F_initModule \
LCD_F_initModule
#endif
#ifdef ROM_LCD_F_turnOn
#define MAP_LCD_F_turnOn \
ROM_LCD_F_turnOn
#else
#define MAP_LCD_F_turnOn \
LCD_F_turnOn
#endif
#ifdef ROM_LCD_F_turnOff
#define MAP_LCD_F_turnOff \
ROM_LCD_F_turnOff
#else
#define MAP_LCD_F_turnOff \
LCD_F_turnOff
#endif
#ifdef ROM_LCD_F_clearAllMemory
#define MAP_LCD_F_clearAllMemory \
ROM_LCD_F_clearAllMemory
#else
#define MAP_LCD_F_clearAllMemory \
LCD_F_clearAllMemory
#endif
#ifdef ROM_LCD_F_clearAllBlinkingMemory
#define MAP_LCD_F_clearAllBlinkingMemory \
ROM_LCD_F_clearAllBlinkingMemory
#else
#define MAP_LCD_F_clearAllBlinkingMemory \
LCD_F_clearAllBlinkingMemory
#endif
#ifdef ROM_LCD_F_selectDisplayMemory
#define MAP_LCD_F_selectDisplayMemory \
ROM_LCD_F_selectDisplayMemory
#else
#define MAP_LCD_F_selectDisplayMemory \
LCD_F_selectDisplayMemory
#endif
#ifdef ROM_LCD_F_setBlinkingControl
#define MAP_LCD_F_setBlinkingControl \
ROM_LCD_F_setBlinkingControl
#else
#define MAP_LCD_F_setBlinkingControl \
LCD_F_setBlinkingControl
#endif
#ifdef ROM_LCD_F_setAnimationControl
#define MAP_LCD_F_setAnimationControl \
ROM_LCD_F_setAnimationControl
#else
#define MAP_LCD_F_setAnimationControl \
LCD_F_setAnimationControl
#endif
#ifdef ROM_LCD_F_clearAllAnimationMemory
#define MAP_LCD_F_clearAllAnimationMemory \
ROM_LCD_F_clearAllAnimationMemory
#else
#define MAP_LCD_F_clearAllAnimationMemory \
LCD_F_clearAllAnimationMemory
#endif
#ifdef ROM_LCD_F_setPinAsLCDFunction
#define MAP_LCD_F_setPinAsLCDFunction \
ROM_LCD_F_setPinAsLCDFunction
#else
#define MAP_LCD_F_setPinAsLCDFunction \
LCD_F_setPinAsLCDFunction
#endif
#ifdef ROM_LCD_F_setPinAsPortFunction
#define MAP_LCD_F_setPinAsPortFunction \
ROM_LCD_F_setPinAsPortFunction
#else
#define MAP_LCD_F_setPinAsPortFunction \
LCD_F_setPinAsPortFunction
#endif
#ifdef ROM_LCD_F_setPinsAsLCDFunction
#define MAP_LCD_F_setPinsAsLCDFunction \
ROM_LCD_F_setPinsAsLCDFunction
#else
#define MAP_LCD_F_setPinsAsLCDFunction \
LCD_F_setPinsAsLCDFunction
#endif
#ifdef ROM_LCD_F_setPinAsCOM
#define MAP_LCD_F_setPinAsCOM \
ROM_LCD_F_setPinAsCOM
#else
#define MAP_LCD_F_setPinAsCOM \
LCD_F_setPinAsCOM
#endif
#ifdef ROM_LCD_F_setPinAsSEG
#define MAP_LCD_F_setPinAsSEG \
ROM_LCD_F_setPinAsSEG
#else
#define MAP_LCD_F_setPinAsSEG \
LCD_F_setPinAsSEG
#endif
#ifdef ROM_LCD_F_selectBias
#define MAP_LCD_F_selectBias \
ROM_LCD_F_selectBias
#else
#define MAP_LCD_F_selectBias \
LCD_F_selectBias
#endif
#ifdef ROM_LCD_F_setVLCDSource
#define MAP_LCD_F_setVLCDSource \
ROM_LCD_F_setVLCDSource
#else
#define MAP_LCD_F_setVLCDSource \
LCD_F_setVLCDSource
#endif
#ifdef ROM_LCD_F_clearInterrupt
#define MAP_LCD_F_clearInterrupt \
ROM_LCD_F_clearInterrupt
#else
#define MAP_LCD_F_clearInterrupt \
LCD_F_clearInterrupt
#endif
#ifdef ROM_LCD_F_getInterruptStatus
#define MAP_LCD_F_getInterruptStatus \
ROM_LCD_F_getInterruptStatus
#else
#define MAP_LCD_F_getInterruptStatus \
LCD_F_getInterruptStatus
#endif
#ifdef ROM_LCD_F_getEnabledInterruptStatus
#define MAP_LCD_F_getEnabledInterruptStatus \
ROM_LCD_F_getEnabledInterruptStatus
#else
#define MAP_LCD_F_getEnabledInterruptStatus \
LCD_F_getEnabledInterruptStatus
#endif
#ifdef ROM_LCD_F_enableInterrupt
#define MAP_LCD_F_enableInterrupt \
ROM_LCD_F_enableInterrupt
#else
#define MAP_LCD_F_enableInterrupt \
LCD_F_enableInterrupt
#endif
#ifdef ROM_LCD_F_disableInterrupt
#define MAP_LCD_F_disableInterrupt \
ROM_LCD_F_disableInterrupt
#else
#define MAP_LCD_F_disableInterrupt \
LCD_F_disableInterrupt
#endif
#ifdef ROM_LCD_F_registerInterrupt
#define MAP_LCD_F_registerInterrupt \
ROM_LCD_F_registerInterrupt
#else
#define MAP_LCD_F_registerInterrupt \
LCD_F_registerInterrupt
#endif
#ifdef ROM_LCD_F_unregisterInterrupt
#define MAP_LCD_F_unregisterInterrupt \
ROM_LCD_F_unregisterInterrupt
#else
#define MAP_LCD_F_unregisterInterrupt \
LCD_F_unregisterInterrupt
#endif
#endif // __ROM_MAP_H__

109
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/rtc_c.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/rtc_c.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,28 +29,28 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <rtc_c.h>
#include <interrupt.h>
#include <debug.h>
#include <hw_memmap.h>
#include <ti/devices/msp432p4xx/driverlib/rtc_c.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
void RTC_C_startClock(void)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 0;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_holdClock(void)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_CALF_3)) | frequencySelect;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
@ -63,7 +58,7 @@ void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
uint_fast8_t offsetValue)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->OCAL = offsetValue + offsetDirection;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
@ -85,7 +80,7 @@ bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
uint_fast16_t formatSelect)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
@ -94,14 +89,18 @@ void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
else
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 0;
RTC_C->TIM0 = (calendarTime->minutes<<RTC_C_TIM0_MIN_OFS) | calendarTime->seconds;
RTC_C->TIM1 = (calendarTime->dayOfWeek<<RTC_C_TIM1_DOW_OFS) | calendarTime->hours;
RTC_C->DATE = (calendarTime->month<<RTC_C_DATE_MON_OFS) | calendarTime->dayOfmonth;
RTC_C->TIM0 = (calendarTime->minutes << RTC_C_TIM0_MIN_OFS)
| calendarTime->seconds;
RTC_C->TIM1 = (calendarTime->dayOfWeek << RTC_C_TIM1_DOW_OFS)
| calendarTime->hours;
RTC_C->DATE = (calendarTime->month << RTC_C_DATE_MON_OFS)
| calendarTime->dayOfmonth;
RTC_C->YEAR = calendarTime->year;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
RTC_C_Calendar RTC_C_getCalendarTime(void)
{
RTC_C_Calendar tempCal;
@ -109,17 +108,25 @@ RTC_C_Calendar RTC_C_getCalendarTime(void)
while (!(BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_RDY_OFS)))
;
tempCal.seconds = RTC_C->TIM0 & RTC_C_TIM0_SEC_MASK;
tempCal.minutes = (RTC_C->TIM0 & RTC_C_TIM0_MIN_MASK)>>RTC_C_TIM0_MIN_OFS;
tempCal.hours = RTC_C->TIM1 & RTC_C_TIM1_HOUR_MASK;
tempCal.dayOfWeek = (RTC_C->TIM1 & RTC_C_TIM1_DOW_MASK)>>RTC_C_TIM1_DOW_OFS;
tempCal.dayOfmonth = RTC_C->DATE & RTC_C_DATE_DAY_MASK;
tempCal.month = (RTC_C->DATE & RTC_C_DATE_MON_MASK)>>RTC_C_DATE_MON_OFS;
tempCal.seconds = RTC_C->TIM0
& (RTC_C_TIM0_SEC_LD_MASK | RTC_C_TIM0_SEC_HD_MASK);
tempCal.minutes = (RTC_C->TIM0
& (RTC_C_TIM0_MIN_LD_MASK | RTC_C_TIM0_MIN_HD_MASK))
>> RTC_C_TIM0_MIN_OFS;
tempCal.hours = RTC_C->TIM1
& (RTC_C_TIM1_HOUR_LD_MASK | RTC_C_TIM1_HOUR_HD_MASK);
tempCal.dayOfWeek = (RTC_C->TIM1
& (RTC_C_TIM1_DOW_MASK)) >> RTC_C_TIM1_DOW_OFS;
tempCal.dayOfmonth = RTC_C->DATE
& (RTC_C_DATE_DAY_LD_MASK | RTC_C_DATE_DAY_HD_MASK);
tempCal.month = (RTC_C->DATE & (RTC_C_DATE_MON_LD_MASK | RTC_C_DATE_MON_HD))
>> RTC_C_DATE_MON_OFS;
tempCal.year = RTC_C->YEAR;
return (tempCal);
}
void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm,
uint_fast8_t dayOfWeekAlarm, uint_fast8_t dayOfmonthAlarm)
{
@ -131,17 +138,24 @@ void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm,
void RTC_C_setCalendarEvent(uint_fast16_t eventSelect)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_TEV_3)) | eventSelect;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleEventDivider)
{
HWREG8(&RTC_C->PS0CTL + prescaleSelect) &= ~(RTC_C_PS0CTL_RT0IP_7);
HWREG8(&RTC_C->PS0CTL + prescaleSelect) |=
prescaleEventDivider;
{
if(prescaleSelect == RTC_C_PRESCALE_0)
{
HWREG8(&RTC_C->PS0CTL) &= ~(RTC_C_PS0CTL_RT0IP_7);
HWREG8(&RTC_C->PS0CTL) |= prescaleEventDivider;
}
else if(prescaleSelect == RTC_C_PRESCALE_1)
{
HWREG8(&RTC_C->PS1CTL) &= ~(RTC_C_PS0CTL_RT0IP_7);
HWREG8(&RTC_C->PS1CTL) |= prescaleEventDivider;
}
}
uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
@ -161,15 +175,15 @@ uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleCounterValue)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT0PS_MASK) | prescaleCounterValue;
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT1PS_MASK)
| (prescaleCounterValue << RTC_C_PS_RT1PS_OFS);
RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT1PS_MASK)
| (prescaleCounterValue << RTC_C_PS_RT1PS_OFS);
}
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
@ -189,12 +203,15 @@ uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert)
void RTC_C_enableInterrupt(uint8_t interruptMask)
{
if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE))
if (interruptMask
& (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE))
{
RTC_C->CTL0 = RTC_C_KEY | (interruptMask
& (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE));
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK)
| (RTC_C_KEY
| (interruptMask
& (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE
+ RTC_C_CTL0_AIE + RTC_C_CTL0_RDYIE)));
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
@ -211,13 +228,15 @@ void RTC_C_enableInterrupt(uint8_t interruptMask)
void RTC_C_disableInterrupt(uint8_t interruptMask)
{
if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE))
uint16_t allIntMask = (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE);
if (interruptMask & allIntMask)
{
RTC_C->CTL0 = RTC_C_KEY
| (RTC_C->CTL0 & ~((interruptMask | RTC_C_CTL0_KEY_MASK)
& (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE)));
RTC_C->CTL0 = (RTC_C->CTL0
& ~((interruptMask & allIntMask) | RTC_C_CTL0_KEY_MASK))
| RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
@ -266,7 +285,7 @@ uint_fast8_t RTC_C_getInterruptStatus(void)
uint_fast8_t RTC_C_getEnabledInterruptStatus(void)
{
uint32_t intStatus = RTC_C_getInterruptStatus();
uint16_t intStatus = RTC_C_getInterruptStatus();
if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_OFIE_OFS))
{

32
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/rtc_c.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/rtc_c.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -58,7 +53,7 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
@ -266,15 +261,16 @@ extern bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
//! following members and corresponding values:
//! - \b seconds between 0-59
//! - \b minutes between 0-59
//! - \b hours between 0-24
//! - \b hours between 0-23
//! - \b dayOfWeek between 0-6
//! - \b dayOfmonth between 0-31
//! - \b dayOfmonth between 1-31
//! - \b month between 1-12
//! - \b year between 0-4095
//! \note Values beyond the ones specified may result in eradic behavior.
//! \note Values beyond the ones specified may result in erratic behavior.
//! \param formatSelect is the format for the Calendar registers to use.
//! Valid values are
//! - \b RTC_FORMAT_BINARY [Default]
//! - \b RTC_FORMAT_BCD
//! - \b RTC_C_FORMAT_BINARY [Default]
//! - \b RTC_C_FORMAT_BCD
//!
//! This function initializes the Calendar mode of the RTC module.
//!
@ -458,7 +454,7 @@ extern uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert);
//! Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! setCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
@ -487,7 +483,7 @@ extern void RTC_C_enableInterrupt(uint8_t interruptMask);
//! Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! setCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
@ -516,7 +512,7 @@ extern void RTC_C_disableInterrupt(uint8_t interruptMask);
//! Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! setCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
@ -542,7 +538,7 @@ extern uint_fast8_t RTC_C_getInterruptStatus(void);
//! Mask Value is the logical OR of any of the following
//! - \b RTC_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! setCalendarEvent() is met.
//! - \b RTC_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
@ -565,7 +561,7 @@ extern uint_fast8_t RTC_C_getEnabledInterruptStatus(void);
//! cleared. Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! setCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar

62
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/spi.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/spi.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,10 +29,10 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <spi.h>
#include <interrupt.h>
#include <debug.h>
#include <eusci.h>
#include <ti/devices/msp432p4xx/driverlib/spi.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/eusci.h>
static bool is_A_Module(uint32_t module)
{
@ -56,13 +51,6 @@ static bool is_A_Module(uint32_t module)
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
/* Returning false if we are not divisible */
if((config->clockSourceFrequency
% config->desiredSpiClock) != 0)
{
return false;
}
if (is_A_Module(moduleInstance))
{
ASSERT(
@ -92,7 +80,7 @@ bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *confi
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
@ -110,7 +98,7 @@ bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *confi
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
@ -383,7 +371,7 @@ uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
}
void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
{
if (is_A_Module(moduleInstance))
{
@ -395,7 +383,7 @@ void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
}
void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
{
if (is_A_Module(moduleInstance))
{
@ -424,19 +412,19 @@ uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
if (is_A_Module(moduleInstance))
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
EUSCI_A_SPI_TRANSMIT_INTERRUPT | EUSCI_A_SPI_RECEIVE_INTERRUPT)
& EUSCI_A_CMSIS(moduleInstance)->IE;
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
EUSCI_B_SPI_TRANSMIT_INTERRUPT | EUSCI_B_SPI_RECEIVE_INTERRUPT)
& EUSCI_B_CMSIS(moduleInstance)->IE;
}
}
void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
{
if (is_A_Module(moduleInstance))
{
@ -639,7 +627,7 @@ void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
//! \return true
//
//*****************************************************************************
bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
@ -777,7 +765,7 @@ uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
//! \return None
//
//*****************************************************************************
void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint16_t mask)
{
ASSERT(
!(mask
@ -806,7 +794,7 @@ void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
//! \return None
//
//*****************************************************************************
void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint16_t mask)
{
ASSERT(
!(mask
@ -860,7 +848,7 @@ uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
//! \return None
//
//*****************************************************************************
void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint16_t mask)
{
ASSERT(
!(mask
@ -947,7 +935,7 @@ uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
//! \brief Indicates whether or not the SPI bus is busy.
//!
//! This function returns an indication of whether or not the SPI bus is
//! busy.This function checks the status of the bus via UCBBUSY bit
//! busy.This function checks the status of the bus via UCBUSY bit
//!
//! \param baseAddress is the base address of the EUSCI_B_SPI module.
//!
@ -957,7 +945,7 @@ uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_SPI_BUSY_OFS );
}
//*****************************************************************************
@ -1050,7 +1038,7 @@ void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
//! \return true
//
//*****************************************************************************
bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
@ -1188,7 +1176,7 @@ uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint16_t mask)
{
ASSERT(
!(mask
@ -1217,7 +1205,7 @@ void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint16_t mask)
{
ASSERT(
!(mask
@ -1271,7 +1259,7 @@ uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint16_t mask)
{
ASSERT(
!(mask
@ -1358,7 +1346,7 @@ uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
//! \brief Indicates whether or not the SPI bus is busy.
//!
//! This function returns an indication of whether or not the SPI bus is
//! busy.This function checks the status of the bus via UCBBUSY bit
//! busy.This function checks the status of the bus via UCBUSY bit
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//!
@ -1367,5 +1355,5 @@ uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_A_STATW_SPI_BUSY_OFS);
}

83
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/spi.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/spi.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,8 +52,8 @@ extern "C"
#include <stdbool.h>
#include <stdint.h>
#include <msp.h>
#include "eusci.h"
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <ti/devices/msp432p4xx/driverlib/eusci.h>
/* Configuration Defines */
#define EUSCI_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK
@ -80,8 +75,8 @@ extern "C"
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_SPI_TRANSMIT_INTERRUPT EUSCI_B__TXIE
#define EUSCI_SPI_RECEIVE_INTERRUPT EUSCI_B__RXIE
#define EUSCI_SPI_TRANSMIT_INTERRUPT EUSCI_B_IE_TXIE
#define EUSCI_SPI_RECEIVE_INTERRUPT EUSCI_B_IE_RXIE
#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM
#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
@ -527,7 +522,7 @@ extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance);
//! \return None.
//
//*****************************************************************************
extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask);
//*****************************************************************************
//
@ -560,7 +555,7 @@ extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//! \return None.
//
//*****************************************************************************
extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask);
//*****************************************************************************
//
@ -644,7 +639,7 @@ extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance);
//! \return None
//
//*****************************************************************************
extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask);
//*****************************************************************************
//
@ -708,53 +703,53 @@ extern void SPI_unregisterInterrupt(uint32_t moduleInstance);
/* Backwards Compatibility Layer */
#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH
#define EUSCI_B_SPI_MSB_FIRST UCMSB
#define EUSCI_B_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB
#define EUSCI_B_SPI_LSB_FIRST 0x00
#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL
#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_B_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK
#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK
#define EUSCI_B_SPI_3PIN UCMODE_0
#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
#define EUSCI_B_SPI_3PIN EUSCI_B_CTLW0_MODE_0
#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1
#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2
#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM
#define EUSCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_B_SPI_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_B_SPI_TRANSMIT_INTERRUPT EUSCI_B_IE_TXIE0
#define EUSCI_B_SPI_RECEIVE_INTERRUPT EUSCI_B_IE_RXIE0
#define EUSCI_B_SPI_BUSY UCBUSY
#define EUSCI_B_SPI_BUSY EUSCI_B_STATW_BBUSY
#define EUSCI_B_SPI_NOT_BUSY 0x00
#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_A_CTLW0_CKPH
#define EUSCI_A_SPI_MSB_FIRST UCMSB
#define EUSCI_A_SPI_MSB_FIRST EUSCI_A_CTLW0_MSB
#define EUSCI_A_SPI_LSB_FIRST 0x00
#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_A_CTLW0_CKPL
#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_A_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_A_SPI_CLOCKSOURCE_ACLK EUSCI_A_CTLW0_SSEL__ACLK
#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK EUSCI_A_CTLW0_SSEL__SMCLK
#define EUSCI_A_SPI_3PIN UCMODE_0
#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
#define EUSCI_A_SPI_3PIN EUSCI_A_CTLW0_MODE_0
#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_A_CTLW0_MODE_1
#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_A_CTLW0_MODE_2
#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_A_CTLW0_STEM
#define EUSCI_A_SPI_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_A_SPI_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_A_SPI_TRANSMIT_INTERRUPT EUSCI_A_IE_TXIE
#define EUSCI_A_SPI_RECEIVE_INTERRUPT EUSCI_A_IE_RXIE
#define EUSCI_A_SPI_BUSY UCBUSY
#define EUSCI_A_SPI_BUSY EUSCI_B_STATW_BBUSY
#define EUSCI_A_SPI_NOT_BUSY 0x00
extern void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
@ -768,11 +763,11 @@ extern void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
extern void EUSCI_A_SPI_transmitData(uint32_t baseAddress,
uint8_t transmitData);
extern uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress);
extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint16_t mask);
extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint16_t mask);
extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress,
uint8_t mask);
extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint16_t mask);
extern void EUSCI_A_SPI_enable(uint32_t baseAddress);
extern void EUSCI_A_SPI_disable(uint32_t baseAddress);
extern uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
@ -790,11 +785,11 @@ extern void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
extern void EUSCI_B_SPI_transmitData(uint32_t baseAddress,
uint8_t transmitData);
extern uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress);
extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint16_t mask);
extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint16_t mask);
extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress,
uint8_t mask);
extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint16_t mask);
extern void EUSCI_B_SPI_enable(uint32_t baseAddress);
extern void EUSCI_B_SPI_disable(uint32_t baseAddress);
extern uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);

32
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/sysctl.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/sysctl.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -39,8 +34,12 @@
#include <stdbool.h>
/* DriverLib Includes */
#include <sysctl.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/sysctl.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
/* Define to ensure that our current MSP432 has the SYSCTL module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_SYSCTL__
#ifdef DEBUG
@ -146,7 +145,10 @@ void SysCtl_enableNMISource(uint_fast8_t flags)
uint_fast8_t SysCtl_getNMISourceStatus(void)
{
return SYSCTL->NMI_CTLSTAT;
return SYSCTL->NMI_CTLSTAT & (SYSCTL_NMI_CTLSTAT_CS_FLG |
SYSCTL_NMI_CTLSTAT_PSS_FLG |
SYSCTL_NMI_CTLSTAT_PCM_FLG |
SYSCTL_NMI_CTLSTAT_PIN_FLG);
}
void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
@ -172,20 +174,20 @@ void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
{
case SYSCTL_SRAM_BANK7:
sramBank = SYSCTL_SRAM_BANK6 + SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK6:
sramBank = SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK5:
sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3
sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3
+ SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK4:
sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK3:
@ -278,3 +280,5 @@ uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
{
return HWREG16(TLV_BASE + refVoltage + temperature);
}
#endif /* __MCU_HAS_SYSCTL__ */

25
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/sysctl.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/sysctl.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,6 +32,13 @@
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
#include <stdint.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/* Define to ensure that our current MSP432 has the SYSCTL module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_SYSCTL__
//*****************************************************************************
//
//! \addtogroup sysctl_api
@ -55,12 +57,9 @@ extern "C"
{
#endif
#include <stdint.h>
#include <msp.h>
//*****************************************************************************
//
// Control specific variables
// Control specific variables
//
//*****************************************************************************
#define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
@ -127,7 +126,7 @@ extern "C"
//*****************************************************************************
//
// Structures for TLV definitions
//
//
//*****************************************************************************
typedef struct
{
@ -541,4 +540,6 @@ extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
//
//*****************************************************************************
#endif /* __MCU_HAS_SYSCTL__ */
#endif // __SYSCTL_H__

413
port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/sysctl_a.c Normal file
View File

@ -0,0 +1,413 @@
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
#include <stdbool.h>
/* DriverLib Includes */
#include <ti/devices/msp432p4xx/driverlib/sysctl_a.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
/* Define to ensure that our current MSP432 has the SYSCTL_A module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_SYSCTL_A__
void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
uint_fast8_t *length, uint32_t **data_address)
{
/* TLV Structure Start Address */
uint32_t *TLV_address = (uint32_t *) TLV_START;
if(*TLV_address == 0xFFFFFFFF)
{
*length = 0;
// Return 0 for TAG not found
*data_address = 0;
return;
}
while (((*TLV_address != tag)) // check for tag and instance
&& (*TLV_address != TLV_TAGEND)) // do range check first
{
if (*TLV_address == tag)
{
if (instance == 0)
{
break;
}
/* Repeat until requested instance is reached */
instance--;
}
TLV_address += (*(TLV_address + 1)) + 2;
}
/* Check if Tag match happened... */
if (*TLV_address == tag)
{
/* Return length = Address + 1 */
*length = (*(TLV_address + 1)) * 4;
/* Return address of first data/value info = Address + 2 */
*data_address = (uint32_t *) (TLV_address + 2);
}
// If there was no tag match and the end of TLV structure was reached..
else
{
// Return 0 for TAG not found
*length = 0;
// Return 0 for TAG not found
*data_address = 0;
}
}
uint_least32_t SysCtl_A_getSRAMSize(void)
{
return SYSCTL_A->SRAM_SIZE;
}
uint_least32_t SysCtl_A_getFlashSize(void)
{
return SYSCTL_A->MAINFLASH_SIZE;
}
uint_least32_t SysCtl_A_getInfoFlashSize(void)
{
return SYSCTL_A->INFOFLASH_SIZE;
}
void SysCtl_A_disableNMISource(uint_fast8_t flags)
{
SYSCTL_A->NMI_CTLSTAT &= ~(flags);
}
void SysCtl_A_enableNMISource(uint_fast8_t flags)
{
SYSCTL_A->NMI_CTLSTAT |= flags;
}
uint_fast8_t SysCtl_A_getNMISourceStatus(void)
{
return SYSCTL_A->NMI_CTLSTAT & (SYSCTL_A_NMI_CTLSTAT_CS_FLG |
SYSCTL_A_NMI_CTLSTAT_PSS_FLG |
SYSCTL_A_NMI_CTLSTAT_PCM_FLG |
SYSCTL_A_NMI_CTLSTAT_PIN_FLG);
}
void SysCtl_A_rebootDevice(void)
{
SYSCTL_A->REBOOT_CTL = (SYSCTL_A_REBOOT_CTL_REBOOT | SYSCTL_A_REBOOT_KEY);
}
void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices)
{
SYSCTL_A->PERIHALT_CTL &= ~devices;
}
void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices)
{
SYSCTL_A->PERIHALT_CTL |= devices;
}
void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType)
{
if (resetType)
SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_TIMEOUT;
else
SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_TIMEOUT;
}
void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType)
{
if (resetType)
SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_VIOLATION;
else
SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_VIOLATION;
}
void SysCtl_A_enableGlitchFilter(void)
{
SYSCTL_A->DIO_GLTFLT_CTL |= SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN;
}
void SysCtl_A_disableGlitchFilter(void)
{
SYSCTL_A->DIO_GLTFLT_CTL &= ~SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN;
}
uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage,
uint32_t temperature)
{
return HWREG16(TLV_BASE + refVoltage + temperature);
}
bool SysCtl_A_enableSRAM(uint32_t addr)
{
uint32_t bankSize, bankBit;
/* If SRAM is busy, return false */
if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY))
return false;
/* Grabbing the bank size */
bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS;
bankBit = (addr - SRAM_BASE) / bankSize;
if (bankBit < 32)
{
SYSCTL_A->SRAM_BANKEN_CTL0 |= (1 << bankBit);
} else if (bankBit < 64)
{
SYSCTL_A->SRAM_BANKEN_CTL1 |= (1 << (bankBit - 32));
} else if (bankBit < 96)
{
SYSCTL_A->SRAM_BANKEN_CTL2 |= (1 << (bankBit - 64));
} else
{
SYSCTL_A->SRAM_BANKEN_CTL3 |= (1 << (bankBit - 96));
}
return true;
}
bool SysCtl_A_disableSRAM(uint32_t addr)
{
uint32_t bankSize, bankBit;
/* If SRAM is busy, return false */
if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY))
return false;
/* Grabbing the bank size */
bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS;
bankBit = (addr - SRAM_BASE) / bankSize;
if (bankBit < 32)
{
SYSCTL_A->SRAM_BANKEN_CTL0 &= ~(0xFFFFFFFF << bankBit);
} else if (bankBit < 64)
{
SYSCTL_A->SRAM_BANKEN_CTL1 &= ~(0xFFFFFFFF << (bankBit - 32));
} else if (bankBit < 96)
{
SYSCTL_A->SRAM_BANKEN_CTL2 &= ~(0xFFFFFFFF << (bankBit - 64));
} else
{
SYSCTL_A->SRAM_BANKEN_CTL3 &= ~(0xFFFFFFFF << (bankBit - 96));
}
return true;
}
bool SysCtl_A_enableSRAMRetention(uint32_t startAddr,
uint32_t endAddr)
{
uint32_t blockSize, blockBitStart, blockBitEnd;
if (startAddr > endAddr)
return false;
/* If SRAM is busy, return false */
if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY))
return false;
/* Getting how big each bank is and how many blocks we have per bank */
blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS;
blockBitStart = (startAddr - SRAM_BASE) / blockSize;
blockBitEnd = (endAddr - SRAM_BASE) / blockSize;
if (blockBitStart < 32)
{
if (blockBitEnd < 32)
{
SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF >> (31 - blockBitEnd))
& (0xFFFFFFFF << blockBitStart);
return true;
} else if (blockBitEnd < 64)
{
SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
SYSCTL_A->SRAM_BLKRET_CTL1 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 32)));
} else if (blockBitEnd < 96)
{
SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF;
SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 64)));
} else
{
SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF;
SYSCTL_A->SRAM_BLKRET_CTL2 = 0xFFFFFFFF;
SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 96)));
}
} else if (blockBitStart < 64)
{
if (blockBitEnd < 64)
{
SYSCTL_A->SRAM_BLKRET_CTL1 |= ((0xFFFFFFFF
>> (31 - (blockBitEnd - 32)))
& (0xFFFFFFFF << (blockBitStart - 32)));
return true;
}
SYSCTL_A->SRAM_BLKRET_CTL1 = (0xFFFFFFFF << (blockBitStart - 32));
if (blockBitEnd < 96)
{
SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 64)));
} else
{
SYSCTL_A->SRAM_BLKRET_CTL2 |= 0xFFFFFFFF;
SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 96)));
}
} else if (blockBitStart < 96)
{
if (blockBitEnd < 96)
{
SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 64)))
& (0xFFFFFFFF << (blockBitStart - 64));
return true;
} else
{
SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF << (blockBitStart - 64));
SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
>> (31 - (blockBitEnd - 96)));
}
} else
{
SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF >> (31 - (blockBitEnd - 96)))
& (0xFFFFFFFF << (blockBitStart - 96));
}
return true;
}
bool SysCtl_A_disableSRAMRetention(uint32_t startAddr,
uint32_t endAddr)
{
uint32_t blockSize, blockBitStart, blockBitEnd;
if (startAddr > endAddr)
return false;
/* If SRAM is busy, return false */
if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY))
return false;
/* Getting how big each bank is and how many blocks we have per bank */
blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS;
blockBitStart = (startAddr - SRAM_BASE) / blockSize;
blockBitEnd = (endAddr - SRAM_BASE) / blockSize;
if (blockBitStart < 32)
{
if (blockBitEnd < 32)
{
SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF >> (31 - blockBitEnd))
& (0xFFFFFFFF << blockBitStart));
return true;
}
SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF << blockBitStart));
if (blockBitEnd < 64)
{
SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF
>> (31 - (blockBitEnd - 32))));
} else if (blockBitEnd < 96)
{
SYSCTL_A->SRAM_BLKRET_CTL1 = 0;
SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF
>> (31 - (blockBitEnd - 64)));
} else
{
SYSCTL_A->SRAM_BLKRET_CTL1 = 0;
SYSCTL_A->SRAM_BLKRET_CTL2 = 0;
SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
>> (31 - (blockBitEnd - 96)));
}
} else if (blockBitStart < 64)
{
if (blockBitEnd < 64)
{
SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF
>> (31 - (blockBitEnd - 32)))
& (0xFFFFFFFF << (blockBitStart - 32)));
return true;
}
SYSCTL_A->SRAM_BLKRET_CTL1 &= ~(0xFFFFFFFF << (blockBitStart - 32));
if (blockBitEnd < 96)
{
SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF
>> (31 - (blockBitEnd - 64)));
} else
{
SYSCTL_A->SRAM_BLKRET_CTL2 = 0;
SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
>> (31 - (blockBitEnd - 96)));
}
} else if (blockBitStart < 96)
{
if (blockBitEnd < 96)
{
SYSCTL_A->SRAM_BLKRET_CTL2 &= ~((0xFFFFFFFF
>> (31 - (blockBitEnd - 64)))
& (0xFFFFFFFF << (blockBitStart - 64)));
} else
{
SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF << (blockBitStart - 64));
SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
>> (31 - (blockBitEnd - 96)));
}
} else
{
SYSCTL_A->SRAM_BLKRET_CTL3 &= ~((0xFFFFFFFF >> (31 - (blockBitEnd - 96)))
& (0xFFFFFFFF << (blockBitStart - 96)));
}
return true;
}
#endif /* __MCU_HAS_SYSCTL_A__ */

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/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __SYSCTL_A_H__
#define __SYSCTL_A_H__
#include <stdint.h>
#include <stdbool.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
/* Define to ensure that our current MSP432 has the SYSCTL_A module. This
definition is included in the device specific header file */
#ifdef __MCU_HAS_SYSCTL_A__
//*****************************************************************************
//
//! \addtogroup sysctl_a_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define SYSCTL_A_HARD_RESET 1
#define SYSCTL_A_SOFT_RESET 0
#define SYSCTL_A_PERIPH_LCD SYSCTL_A_PERIHALT_CTL_HALT_LCD
#define SYSCTL_A_PERIPH_DMA SYSCTL_A_PERIHALT_CTL_HALT_DMA
#define SYSCTL_A_PERIPH_WDT SYSCTL_A_PERIHALT_CTL_HALT_WDT
#define SYSCTL_A_PERIPH_ADC SYSCTL_A_PERIHALT_CTL_HALT_ADC
#define SYSCTL_A_PERIPH_EUSCIB3 SYSCTL_A_PERIHALT_CTL_HALT_EUB3
#define SYSCTL_A_PERIPH_EUSCIB2 SYSCTL_A_PERIHALT_CTL_HALT_EUB2
#define SYSCTL_A_PERIPH_EUSCIB1 SYSCTL_A_PERIHALT_CTL_HALT_EUB1
#define SYSCTL_A_PERIPH_EUSCIB0 SYSCTL_A_PERIHALT_CTL_HALT_EUB0
#define SYSCTL_A_PERIPH_EUSCIA3 SYSCTL_A_PERIHALT_CTL_HALT_EUA3
#define SYSCTL_A_PERIPH_EUSCIA2 SYSCTL_A_PERIHALT_CTL_HALT_EUA2
#define SYSCTL_A_PERIPH_EUSCIA1 SYSCTL_A_PERIHALT_CTL_HALT_EUA1
#define SYSCTL_A_PERIPH_EUSCIA0 SYSCTL_A_PERIHALT_CTL_HALT_EUA0
#define SYSCTL_A_PERIPH_TIMER32_0_MODULE SYSCTL_A_PERIHALT_CTL_HALT_T32_0
#define SYSCTL_A_PERIPH_TIMER16_3 SYSCTL_A_PERIHALT_CTL_HALT_T16_3
#define SYSCTL_A_PERIPH_TIMER16_2 SYSCTL_A_PERIHALT_CTL_HALT_T16_2
#define SYSCTL_A_PERIPH_TIMER16_1 SYSCTL_A_PERIHALT_CTL_HALT_T16_1
#define SYSCTL_A_PERIPH_TIMER16_0 SYSCTL_A_PERIHALT_CTL_HALT_T16_0
#define SYSCTL_A_NMIPIN_SRC SYSCTL_A_NMI_CTLSTAT_PIN_SRC
#define SYSCTL_A_PCM_SRC SYSCTL_A_NMI_CTLSTAT_PCM_SRC
#define SYSCTL_A_PSS_SRC SYSCTL_A_NMI_CTLSTAT_PSS_SRC
#define SYSCTL_A_CS_SRC SYSCTL_A_NMI_CTLSTAT_CS_SRC
#define SYSCTL_A_REBOOT_KEY 0x6900
#define SYSCTL_A_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
#define SYSCTL_A_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
#define SYSCTL_A_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
#define SYSCTL_A_85_DEGREES_C 4
#define SYSCTL_A_30_DEGREES_C 0
#define SYSCTL_A_BANKMASK 0x80000000
#define SRAMCTL_CTL0_BANK 0x10000000
#define SRAMCTL_CTL1_BANK 0x20000000
#define SRAMCTL_CTL2_BANK 0x30000000
#define SRAMCTL_CTL3_BANK 0x40000000
#define TLV_START 0x00201004
#define TLV_TAG_RESERVED1 1
#define TLV_TAG_RESERVED2 2
#define TLV_TAG_CS 3
#define TLV_TAG_FLASHCTL 4
#define TLV_TAG_ADC14 5
#define TLV_TAG_RESERVED6 6
#define TLV_TAG_RESERVED7 7
#define TLV_TAG_REF 8
#define TLV_TAG_RESERVED9 9
#define TLV_TAG_RESERVED10 10
#define TLV_TAG_DEVINFO 11
#define TLV_TAG_DIEREC 12
#define TLV_TAG_RANDNUM 13
#define TLV_TAG_RESERVED14 14
#define TLV_TAG_BSL 15
#define TLV_TAGEND 0x0BD0E11D
//*****************************************************************************
//
// Structures for TLV definitions
//
//*****************************************************************************
typedef struct
{
uint32_t maxProgramPulses;
uint32_t maxErasePulses;
} SysCtl_A_FlashTLV_Info;
typedef struct
{
uint32_t rDCOIR_FCAL_RSEL04;
uint32_t rDCOIR_FCAL_RSEL5;
uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
uint32_t rDCOIR_CONSTK_RSEL04;
uint32_t rDCOIR_CONSTK_RSEL5;
uint32_t rDCOER_FCAL_RSEL04;
uint32_t rDCOER_FCAL_RSEL5;
uint32_t rDCOER_MAXPOSTUNE_RSEL04;
uint32_t rDCOER_MAXNEGTUNE_RSEL04;
uint32_t rDCOER_MAXPOSTUNE_RSEL5;
uint32_t rDCOER_MAXNEGTUNE_RSEL5;
uint32_t rDCOER_CONSTK_RSEL04;
uint32_t rDCOER_CONSTK_RSEL5;
} SysCtl_A_CSCalTLV_Info;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Gets the size of the SRAM.
//!
//! \return The total number of bytes of SRAM.
//
//*****************************************************************************
extern uint_least32_t SysCtl_A_getSRAMSize(void);
//*****************************************************************************
//
//! Gets the size of the flash.
//!
//! \return The total number of bytes of main flash memory.
//!
//! \note This returns the total amount of main memory flash. To find how much
//! INFO memory is available, use the \link SysCtl_A_getInfoFlashSize
//! \endlink function.
//
//*****************************************************************************
extern uint_least32_t SysCtl_A_getFlashSize(void);
//*****************************************************************************
//
//! Gets the size of the flash.
//!
//! \return The total number of bytes of flash of INFO flash memory.
//!
//! \note This returns the total amount of INFO memory flash. To find how much
//! main memory is available, use the \link SysCtl_A_getFlashSize
//! \endlink function.
//
//*****************************************************************************
extern uint_least32_t SysCtl_A_getInfoFlashSize(void);
//*****************************************************************************
//
//! Reboots the device and causes the device to re-initialize itself.
//!
//! \return This function does not return.
//
//*****************************************************************************
extern void SysCtl_A_rebootDevice(void);
//*****************************************************************************
//
//! The TLV structure uses a tag or base address to identify segments of the
//! table where information is stored. Some examples of TLV tags are Peripheral
//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
//! the value of a tag and the length of the tag.
//!
//! \param tag represents the tag for which the information needs to be
//! retrieved.
//! Valid values are:
//! - \b TLV_TAG_RESERVED1
//! - \b TLV_TAG_RESERVED2
//! - \b TLV_TAG_CS
//! - \b TLV_TAG_FLASHCTL
//! - \b TLV_TAG_ADC14
//! - \b TLV_TAG_RESERVED6
//! - \b TLV_TAG_RESERVED7
//! - \b TLV_TAG_REF
//! - \b TLV_TAG_RESERVED9
//! - \b TLV_TAG_RESERVED10
//! - \b TLV_TAG_DEVINFO
//! - \b TLV_TAG_DIEREC
//! - \b TLV_TAG_RANDNUM
//! - \b TLV_TAG_RESERVED14
//! \param instance In some cases a specific tag may have more than one
//! instance. For example there may be multiple instances of timer
//! calibration data present under a single Timer Cal tag. This variable
//! specifies the instance for which information is to be retrieved (0,
//! 1, etc.). When only one instance exists; 0 is passed.
//! \param length Acts as a return through indirect reference. The function
//! retrieves the value of the TLV tag length. This value is pointed to
//! by *length and can be used by the application level once the
//! function is called. If the specified tag is not found then the
//! pointer is null 0.
//! \param data_address acts as a return through indirect reference. Once the
//! function is called data_address points to the pointer that holds the
//! value retrieved from the specified TLV tag. If the specified tag is
//! not found then the pointer is null 0.
//!
//! \return None
//
//*****************************************************************************
extern void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
uint_fast8_t *length, uint32_t **data_address);
//*****************************************************************************
//
//! Enables areas of SRAM memory. This can be used to optimize power
//! consumption when every SRAM bank isn't needed.
//! This function takes in a 32-bit address to the area in SRAM to to enable.
//! It will convert this address into the corresponding register settings and
//! set them in the register accordingly. Note that passing an address to an
//! area other than SRAM will result in unreliable behavior. Addresses should
//! be given with reference to the SRAM_DATA area of SRAM (usually starting at
//! 0x20000000).
//!
//! \param addr Break address of SRAM to enable. All SRAM below this address
//! will also be enabled. If an unaligned address is given the appropriate
//! aligned address will be calculated.
//!
//! \note The first bank of SRAM is reserved and always enabled.
//!
//! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is
//! not set in the STAT register, this function will return false.
//
//*****************************************************************************
extern bool SysCtl_A_enableSRAM(uint32_t addr);
//*****************************************************************************
//
//! Disables areas of SRAM memory. This can be used to optimize power
//! consumption when every SRAM bank isn't needed. It is important to note
//! that when a higher bank is disabled, all of the SRAM banks above that bank
//! are also disabled. For example, if the address of 0x2001FA0 is given, all
//! SRAM banks from 0x2001FA0 to the top of SRAM will be disabled.
//! This function takes in a 32-bit address to the area in SRAM to to disable.
//! It will convert this address into the corresponding register settings and
//! set them in the register accordingly. Note that passing an address to an
//! area other than SRAM will result in unreliable behavior. Addresses should
//! be given with reference to the SRAM_DATA area of SRAM (usually starting at
//! 0x20000000).
//!
//! \param addr Break address of SRAM to disable. All SRAM above this address
//! will also be disabled. If an unaligned address is given the appropriate
//! aligned address will be calculated.
//!
//! \note The first bank of SRAM is reserved and always enabled.
//!
//! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is
//! not set in the STAT register, this function will return false.
//
//*****************************************************************************
extern bool SysCtl_A_disableSRAM(uint32_t addr);
//*****************************************************************************
//
//! Enables retention of the specified SRAM block address range when the device
//! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
//! banks specified with this function will be placed into retention mode.
//! Retention of individual blocks can be set without the restrictions of the
//! enable/disable functions. Note that any memory range given outside of SRAM
//! will result in unreliable behavior. Also note that any unaligned addresses
//! will be truncated to the closest aligned address before the address given.
//! Addresses should be given with reference to the SRAM_DATA area of SRAM
//! (usually starting at 0x20000000).
//!
//! \param startAddr Start address to enable retention
//!
//! \param endtAddr End address to enable retention
//!
//! \note Block 0 is reserved and retention is always enabled.
//!
//! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is
//! not set in the STAT register, this function will return false.
//
//*****************************************************************************
extern bool SysCtl_A_enableSRAMRetention(uint32_t startAddr,
uint32_t endAddr);
//*****************************************************************************
//
//! Disables retention of the specified SRAM block address range when the device
//! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
//! banks specified with this function will be placed into retention mode.
//! Retention of individual blocks can be set without the restrictions of the
//! enable/disable functions. Note that any memory range given outside of SRAM
//! will result in unreliable behavior. Also note that any unaligned addresses
//! will be truncated to the closest aligned address before the address given.
//! Addresses should be given with reference to the SRAM_DATA area of SRAM
//! (usually starting at 0x20000000).
//!
//! \param startAddr Start address to disable retention
//!
//! \param endtAddr End address to disable retention
//!
//! \note Block 0 is reserved and retention is always enabled.
//!
//! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is
//! not set in the STAT register, this function will return false.
//
//*****************************************************************************
extern bool SysCtl_A_disableSRAMRetention(uint32_t startAddr,
uint32_t endAddr);
//*****************************************************************************
//
//! Makes it so that the provided peripherals will either halt execution after
//! a CPU HALT. Parameters in this function can be combined to account for
//! multiple peripherals. By default, all peripherals keep running after a
//! CPU HALT.
//!
//! \param devices The peripherals to continue running after a CPU HALT
//! This can be a bitwise OR of the following values:
//! - \b SYSCTL_A_PERIPH_LCD,
//! - \b SYSCTL_A_PERIPH_DMA,
//! - \b SYSCTL_A_PERIPH_WDT,
//! - \b SYSCTL_A_PERIPH_ADC,
//! - \b SYSCTL_A_PERIPH_EUSCIB3,
//! - \b SYSCTL_A_PERIPH_EUSCIB2,
//! - \b SYSCTL_A_PERIPH_EUSCIB1
//! - \b SYSCTL_A_PERIPH_EUSCIB0,
//! - \b SYSCTL_A_PERIPH_EUSCIA3,
//! - \b SYSCTL_A_PERIPH_EUSCIA2
//! - \b SYSCTL_A_PERIPH_EUSCIA1,
//! - \b SYSCTL_A_PERIPH_EUSCIA0,
//! - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE,
//! - \b SYSCTL_A_PERIPH_TIMER16_3,
//! - \b SYSCTL_A_PERIPH_TIMER16_2,
//! - \b SYSCTL_A_PERIPH_TIMER16_1,
//! - \b SYSCTL_A_PERIPH_TIMER16_0
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices);
//*****************************************************************************
//
//! Makes it so that the provided peripherals will either halt execution after
//! a CPU HALT. Parameters in this function can be combined to account for
//! multiple peripherals. By default, all peripherals keep running after a
//! CPU HALT.
//!
//! \param devices The peripherals to disable after a CPU HALT
//!
//! The \e devices parameter can be a bitwise OR of the following values:
//! This can be a bitwise OR of the following values:
//! - \b SYSCTL_A_PERIPH_LCD,
//! - \b SYSCTL_A_PERIPH_DMA,
//! - \b SYSCTL_A_PERIPH_WDT,
//! - \b SYSCTL_A_PERIPH_ADC,
//! - \b SYSCTL_A_PERIPH_EUSCIB3,
//! - \b SYSCTL_A_PERIPH_EUSCIB2,
//! - \b SYSCTL_A_PERIPH_EUSCIB1
//! - \b SYSCTL_A_PERIPH_EUSCIB0,
//! - \b SYSCTL_A_PERIPH_EUSCIA3,
//! - \b SYSCTL_A_PERIPH_EUSCIA2
//! - \b SYSCTL_A_PERIPH_EUSCIA1,
//! - \b SYSCTL_A_PERIPH_EUSCIA0,
//! - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE,
//! - \b SYSCTL_A_PERIPH_TIMER16_3,
//! - \b SYSCTL_A_PERIPH_TIMER16_2,
//! - \b SYSCTL_A_PERIPH_TIMER16_1,
//! - \b SYSCTL_A_PERIPH_TIMER16_0
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices);
//*****************************************************************************
//
//! Sets the type of RESET that happens when a watchdog timeout occurs.
//!
//! \param resetType The type of reset to set
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b SYSCTL_A_HARD_RESET,
//! - \b SYSCTL_A_SOFT_RESET
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType);
//*****************************************************************************
//
//! Sets the type of RESET that happens when a watchdog password violation
//! occurs.
//!
//! \param resetType The type of reset to set
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b SYSCTL_A_HARD_RESET,
//! - \b SYSCTL_A_SOFT_RESET
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType);
//*****************************************************************************
//
//! Disables NMIs for the provided modules. When disabled, a NMI flag will not
//! occur when a fault condition comes from the corresponding modules.
//!
//! \param flags The NMI sources to disable
//! Can be a bitwise OR of the following parameters:
//! - \b SYSCTL_A_NMIPIN_SRC,
//! - \b SYSCTL_A_PCM_SRC,
//! - \b SYSCTL_A_PSS_SRC,
//! - \b SYSCTL_A_CS_SRC
//!
//
//*****************************************************************************
extern void SysCtl_A_disableNMISource(uint_fast8_t flags);
//*****************************************************************************
//
//! Enables NMIs for the provided modules. When enabled, a NMI flag will
//! occur when a fault condition comes from the corresponding modules.
//!
//! \param flags The NMI sources to enable
//! Can be a bitwise OR of the following parameters:
//! - \b SYSCTL_A_NMIPIN_SRC,
//! - \b SYSCTL_A_PCM_SRC,
//! - \b SYSCTL_A_PSS_SRC,
//! - \b SYSCTL_A_CS_SRC
//!
//
//*****************************************************************************
extern void SysCtl_A_enableNMISource(uint_fast8_t flags);
//*****************************************************************************
//
//! Returns the current sources of NMIs that are enabled
//!
//! \return NMI source status
//
//*****************************************************************************
extern uint_fast8_t SysCtl_A_getNMISourceStatus(void);
//*****************************************************************************
//
//! Enables glitch suppression on the reset pin of the device. Refer to the
//! device data sheet for specific information about glitch suppression
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_A_enableGlitchFilter(void);
//*****************************************************************************
//
//! Disables glitch suppression on the reset pin of the device. Refer to the
//! device data sheet for specific information about glitch suppression
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_A_disableGlitchFilter(void);
//*****************************************************************************
//
//! Retrieves the calibration constant of the temperature sensor to be used
//! in temperature calculation.
//!
//! \param refVoltage Reference voltage being used.
//!
//! The \e refVoltage parameter must be only one of the following values:
//! - \b SYSCTL_A_1_2V_REF
//! - \b SYSCTL_A_1_45V_REF
//! - \b SYSCTL_A_2_5V_REF
//!
//! \param temperature is the calibration temperature that the user wants to be
//! returned.
//!
//! The \e temperature parameter must be only one of the following values:
//! - \b SYSCTL_A_30_DEGREES_C
//! - \b SYSCTL_A_85_DEGREES_C
//!
//! \return None.
//
//
//*****************************************************************************
extern uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage,
uint32_t temperature);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* __MCU_HAS_SYSCTL_A__ */
#endif // __SYSCTL_A_H__

15
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/systick.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/systick.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,9 +29,9 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <debug.h>
#include <interrupt.h>
#include <systick.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/systick.h>
void SysTick_enableModule(void)
{

9
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/systick.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/systick.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

47
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/timer32.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/timer32.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,30 +29,30 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <timer32.h>
#include <interrupt.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/timer32.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
uint32_t mode)
{
/* Setting up one shot or continuous mode */
if (mode == TIMER32_PERIODIC_MODE)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
= 1;
else if (mode == TIMER32_FREE_RUN_MODE)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
= 0;
else
ASSERT(false);
/* Setting the resolution of the timer */
if (resolution == TIMER32_1_MODULE6BIT)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 0;
if (resolution == TIMER32_16BIT)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 0;
else if (resolution == TIMER32_32BIT)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 1;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 1;
else
ASSERT(false);
@ -67,27 +62,27 @@ void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
|| resolution == TIMER32_PRESCALER_16
|| resolution == TIMER32_PRESCALER_256);
TIMER32_CMSIS(timer)->CONTROL = TIMER32_CMSIS(timer)->CONTROL
& (~TIMER32_CONTROL_PRESCALE_MASK) | preScaler;
TIMER32_CMSIS(timer)->CONTROL = (TIMER32_CMSIS(timer)->CONTROL
& (~TIMER32_CONTROL_PRESCALE_MASK)) | preScaler;
}
void Timer32_setCount(uint32_t timer, uint32_t count)
{
if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
&& (count > UINT16_MAX))
TIMER32_CMSIS(timer)->LOAD = UINT16_MAX;
&& (count > UINT16_MAX))
TIMER32_CMSIS(timer)->LOAD = UINT16_MAX;
else
TIMER32_CMSIS(timer)->LOAD = count;
TIMER32_CMSIS(timer)->LOAD = count;
}
void Timer32_setCountInBackground(uint32_t timer, uint32_t count)
{
if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
&& (count > UINT16_MAX))
&& (count > UINT16_MAX))
TIMER32_CMSIS(timer)->BGLOAD = UINT16_MAX;
else
TIMER32_CMSIS(timer)->BGLOAD = count;
TIMER32_CMSIS(timer)->BGLOAD = count;
}
uint32_t Timer32_getValue(uint32_t timer)
@ -97,7 +92,7 @@ uint32_t Timer32_getValue(uint32_t timer)
void Timer32_startTimer(uint32_t timer, bool oneShot)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
ASSERT(timer == TIMER32_0_BASE || timer == TIMER32_1_BASE);
if (oneShot)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
@ -111,7 +106,7 @@ void Timer32_startTimer(uint32_t timer, bool oneShot)
void Timer32_haltTimer(uint32_t timer)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
ASSERT(timer == TIMER32_0_BASE || timer == TIMER32_1_BASE);
TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_ENABLE;
}

21
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/timer32.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/timer32.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -56,7 +51,7 @@ extern "C"
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
//*****************************************************************************
//
@ -67,15 +62,15 @@ extern "C"
#define TIMER_OFFSET 0x020
#define TIMER32_0_BASE TIMER32_1
#define TIMER32_1_BASE TIMER32_2
#define TIMER32_0_BASE (uint32_t)TIMER32_1
#define TIMER32_1_BASE (uint32_t)TIMER32_2
#define TIMER32_0_INTERRUPT INT_T32_INT1
#define TIMER32_1_INTERRUPT INT_T32_INT2
#define TIMER32_COMBINED_INTERRUPT INT_T32_INTC
#define TIMER32_1_MODULE6BIT 0x00
#define TIMER32_32BIT 0x01
#define TIMER32_16BIT 0x00
#define TIMER32_32BIT 0x01
#define TIMER32_PRESCALER_1 0x00
#define TIMER32_PRESCALER_16 0x04
@ -107,7 +102,7 @@ extern "C"
//! - \b TIMER32_PRESCALER_256
//! \param resolution is the bit resolution of the Timer32 module.
//! Valid values are
//! - \b TIMER32_1_MODULE6BIT [DEFAULT]
//! - \b TIMER32_16BIT [DEFAULT]
//! - \b TIMER32_32BIT
//! \param mode selects between free run and periodic mode. In free run
//! mode, the value of the timer is reset to UINT16_MAX (for 16-bit mode) or

29
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/timer_a.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/timer_a.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,9 +29,9 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <timer_a.h>
#include <interrupt.h>
#include <debug.h>
#include <ti/devices/msp432p4xx/driverlib/timer_a.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
uint16_t clockSourceDivider)
@ -314,7 +309,7 @@ void Timer_A_initCapture(uint32_t timer,
}
uint8_t idx = (config->captureRegister>>1)-1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
(TIMER_A_CMSIS(timer)->CCTL[idx]
(TIMER_A_CMSIS(timer)->CCTL[idx]
& ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
| TIMER_A_CAPTURE_INPUTSELECT_Vcc
| TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
@ -379,7 +374,7 @@ void Timer_A_initCompare(uint32_t timer,
uint8_t idx = (config->compareRegister>>1)-1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
(TIMER_A_CMSIS(timer)->CCTL[idx]
& ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
& ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
| TIMER_A_OUTPUTMODE_RESET_SET | TIMER_A_CCTLN_CAP))
| (config->compareInterruptEnable + config->compareOutputMode);
@ -497,9 +492,9 @@ void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
uint_fast16_t captureCompareRegister,
uint_fast8_t outputModeOutBitValue)
{
uint8_t idx = (captureCompareRegister>>1) - 1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
((TIMER_A_CMSIS(timer)->CCTL[idx])
uint8_t idx = (captureCompareRegister>>1) - 1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
((TIMER_A_CMSIS(timer)->CCTL[idx])
& ~(TIMER_A_OUTPUTMODE_RESET_SET))
| (outputModeOutBitValue);
}
@ -663,7 +658,7 @@ void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
uint8_t idx = (captureCompareRegister>>1) - 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 0;
@ -693,7 +688,7 @@ uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
{
uint8_t idx = (captureCompareRegister>>1) - 1;
if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS))
return Timer_A_getCaptureCompareInterruptStatus(timer,
return Timer_A_getCaptureCompareInterruptStatus(timer,
captureCompareRegister,
TIMER_A_CAPTURE_OVERFLOW |
TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);

11
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/timer_a.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/timer_a.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -55,7 +50,7 @@ extern "C"
{
#endif
#include <stdint.h>
#include <msp.h>
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdbool.h>
//*****************************************************************************

50
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/uart.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/uart.c Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,12 +29,12 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <uart.h>
#include <interrupt.h>
#include <debug.h>
#include <eusci.h>
#include <ti/devices/msp432p4xx/driverlib/uart.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#include <ti/devices/msp432p4xx/driverlib/eusci.h>
bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_ConfigV1 *config)
{
bool retVal = true;
@ -69,6 +64,9 @@ bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
(EUSCI_A_UART_NO_PARITY == config->parity)
|| (EUSCI_A_UART_ODD_PARITY == config->parity)
|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
ASSERT(
(EUSCI_A_UART_8_BIT_LEN == config->dataLength)
|| (EUSCI_A_UART_7_BIT_LEN == config->dataLength));
/* Disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
@ -106,6 +104,12 @@ bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
break;
}
/* UC7BIT = 0(8 bit) OR 1(7 bit) */
if (config->dataLength)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SEVENBIT_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SEVENBIT_OFS) = 0;
/* BaudRate Control Register */
EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
@ -114,7 +118,7 @@ bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
/* Asynchronous mode & 8 bit character select & clear mode */
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
& ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
| EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
return retVal;
@ -123,7 +127,7 @@ bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
@ -133,7 +137,7 @@ void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_RXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
;
@ -201,7 +205,7 @@ void UART_transmitBreak(uint32_t moduleInstance)
EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
}
@ -296,29 +300,33 @@ uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
{
uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG);
uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
intStatus &= ((uint_fast8_t)~EUSCI_A_UART_RECEIVE_INTERRUPT);
}
if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
intStatus &= ((uint_fast8_t)~EUSCI_A_UART_TRANSMIT_INTERRUPT);
}
if(!(intEnabled & EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT))
{
intStatus &= ((uint_fast8_t)~EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT);
}
intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
intStatus &= ((uint_fast8_t)~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT);
}
if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
intStatus &= ((uint_fast8_t)~EUSCI_A_UART_BREAKCHAR_INTERRUPT);
}
return intStatus;

38
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/uart.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/uart.h Executable file → Normal file
View File

@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -58,21 +53,23 @@ extern "C"
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include "eusci.h"
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <ti/devices/msp432p4xx/driverlib/eusci.h>
#define DEFAULT_SYNC 0x00
#define DEFAULT_SYNC 0x00
#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
#define EUSCI_A_UART_NO_PARITY 0x00
#define EUSCI_A_UART_ODD_PARITY 0x01
#define EUSCI_A_UART_EVEN_PARITY 0x02
#define EUSCI_A_UART_8_BIT_LEN 0x00
#define EUSCI_A_UART_7_BIT_LEN 0x01
#define EUSCI_A_UART_MSB_FIRST EUSCI_A_CTLW0_MSB
#define EUSCI_A_UART_LSB_FIRST 0x00
#define EUSCI_A_UART_MODE EUSCI_A_CTLW0_MODE_0
#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_1
#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_1
#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_2
#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE EUSCI_A_CTLW0_MODE_3
@ -114,17 +111,17 @@ extern "C"
//*****************************************************************************
//
//! ypedef eUSCI_eUSCI_UART_Config
//! ypedef eUSCI_eUSCI_UART_ConfigV1
//! \brief Type definition for \link _eUSCI_UART_Config \endlink
//! structure
//!
//! \struct _eUSCI_eUSCI_UART_Config
//! \struct _eUSCI_eUSCI_UART_ConfigV1
//! \brief Configuration structure for compare mode in the \b UART module. See
//! \link UART_initModule \endlink for parameter
//! documentation.
//
//*****************************************************************************
typedef struct _eUSCI_eUSCI_UART_Config
typedef struct _eUSCI_eUSCI_UART_ConfigV1
{
uint_fast8_t selectClockSource;
uint_fast16_t clockPrescalar;
@ -135,7 +132,8 @@ typedef struct _eUSCI_eUSCI_UART_Config
uint_fast16_t numberofStopBits;
uint_fast16_t uartMode;
uint_fast8_t overSampling;
} eUSCI_UART_Config;
uint_fast16_t dataLength;
} eUSCI_UART_ConfigV1;
//*****************************************************************************
//
@ -152,7 +150,7 @@ typedef struct _eUSCI_eUSCI_UART_Config
//! \param config Configuration structure for the UART module
//!
//! <hr>
//! <b>Configuration options for \link eUSCI_UART_Config \endlink
//! <b>Configuration options for \link eUSCI_UART_ConfigV1 \endlink
//! structure.</b>
//! <hr>
//! <br> It is important to note that for eUSCI modules, only "A" modules such
@ -192,6 +190,10 @@ typedef struct _eUSCI_eUSCI_UART_Config
//! Valid values are
//! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION
//! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION
//! \param dataLength indicates Character length. Selects 7-bit or 8-bit character length.
//! Valid values are
//! - \b EUSCI_A_UART_8_BIT_LEN
//! - \b EUSCI_A_UART_7_BIT_LEN
//!
//! Upon successful initialization of the UART block, this function
//! will have initialized the module, but the UART block still remains
@ -206,11 +208,11 @@ typedef struct _eUSCI_eUSCI_UART_Config
//! \b UCSWRST bits of \b UCAxCTL1
//!
//! \return true or
//! STATUS_FAIL of the initialization process
//! false of the initialization process
//
//*****************************************************************************
extern bool UART_initModule(uint32_t moduleInstance,
const eUSCI_UART_Config *config);
const eUSCI_UART_ConfigV1 *config);
//*****************************************************************************
//

30
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/wdt_a.c → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/wdt_a.c Executable file → Normal file
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@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -38,9 +33,16 @@
#include <stdint.h>
/* DriverLib Includes */
#include <wdt_a.h>
#include <debug.h>
#include <interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/wdt_a.h>
#include <ti/devices/msp432p4xx/driverlib/interrupt.h>
#include <ti/devices/msp432p4xx/driverlib/debug.h>
#ifdef __MCU_HAS_SYSCTL_A__
#include <ti/devices/msp432p4xx/driverlib/sysctl_a.h>
#else
#include <ti/devices/msp432p4xx/driverlib/sysctl.h>
#endif
void WDT_A_holdTimer(void)
{
@ -83,12 +85,20 @@ void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
void WDT_A_setPasswordViolationReset(uint_fast8_t resetType)
{
#ifdef __MCU_HAS_SYSCTL_A__
SysCtl_A_setWDTPasswordViolationResetType(resetType);
#else
SysCtl_setWDTPasswordViolationResetType(resetType);
#endif
}
void WDT_A_setTimeoutReset(uint_fast8_t resetType)
{
#ifdef __MCU_HAS_SYSCTL_A__
SysCtl_A_setWDTTimeoutResetType(resetType);
#else
SysCtl_setWDTTimeoutResetType(resetType);
#endif
}
void WDT_A_registerInterrupt(void (*intHandler)(void))

25
port/msp432p401lp-cc256x/MSP432_DriverLib_3_10_00_09/driverlib/MSP432P4xx/wdt_a.h → port/msp432p401lp-cc256x/ti/devices/msp432p4xx/driverlib/wdt_a.h Executable file → Normal file
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@ -1,10 +1,5 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
/* --COPYRIGHT--,BSD
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -55,13 +50,22 @@ extern "C"
{
#endif
#include <msp.h>
/* Includes */
#include <ti/devices/msp432p4xx/inc/msp.h>
#include <stdint.h>
#include "sysctl.h"
#ifdef __MCU_HAS_SYSCTL_A__
#define WDT_A_HARD_RESET SYSCTL_A_HARD_RESET
#define WDT_A_SOFT_RESET SYSCTL_A_SOFT_RESET
#else
#define WDT_A_HARD_RESET SYSCTL_HARD_RESET
#define WDT_A_SOFT_RESET SYSCTL_SOFT_RESET
#endif
//*****************************************************************************
//
// The following are values that can be passed to the clockSelect parameter for
@ -71,8 +75,7 @@ extern "C"
#define WDT_A_CLOCKSOURCE_SMCLK (WDT_A_CTL_SSEL_0)
#define WDT_A_CLOCKSOURCE_ACLK (WDT_A_CTL_SSEL_1)
#define WDT_A_CLOCKSOURCE_VLOCLK (WDT_A_CTL_SSEL_2)
#define WDT_A_CLOCKSOURCE_XCLK (WDT_A_CTL_SSEL_3)
#define WDT_A_CLOCKSOURCE_BCLK (WDT_A_CTL_SSEL_4)
#define WDT_A_CLOCKSOURCE_BCLK (WDT_A_CTL_SSEL_3)
//*****************************************************************************
//

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@ -0,0 +1,80 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* MSP432 Family Generic Include File
*
* File creation date: 01/26/18
*
******************************************************************************/
#ifndef __MSP432_H__
#define __MSP432_H__
/******************************************************************************
* MSP432 devices *
******************************************************************************/
#if defined (__MSP432P401R__)
#include "msp432p401r.h"
#elif defined (__MSP432P401M__)
#include "msp432p401m.h"
#elif defined (__MSP432P401Y__)
#include "msp432p401y.h"
#elif defined (__MSP432P401V__)
#include "msp432p401v.h"
#elif defined (__MSP432P411V__)
#include "msp432p411v.h"
#elif defined (__MSP432P4011__)
#include "msp432p4011.h"
#elif defined (__MSP432P4111__)
#include "msp432p4111.h"
#elif defined (__MSP432P4XX__)
#include "msp432p4xx.h"
#elif defined (__MSP432P411Y__)
#include "msp432p411y.h"
/******************************************************************************
* Failed to match a default include file *
******************************************************************************/
#else
#error "Failed to match a default include file"
#endif
#endif /* __MSP432_H__ */

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@ -0,0 +1,80 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* MSP432 Family Generic Include File
*
* File creation date: 01/26/18
*
******************************************************************************/
#ifndef __MSP432_H__
#define __MSP432_H__
/******************************************************************************
* MSP432 devices *
******************************************************************************/
#if defined (__MSP432P401R__)
#include "msp432p401r.h"
#elif defined (__MSP432P401M__)
#include "msp432p401m.h"
#elif defined (__MSP432P401Y__)
#include "msp432p401y.h"
#elif defined (__MSP432P401V__)
#include "msp432p401v.h"
#elif defined (__MSP432P411V__)
#include "msp432p411v.h"
#elif defined (__MSP432P4011__)
#include "msp432p4011.h"
#elif defined (__MSP432P4111__)
#include "msp432p4111.h"
#elif defined (__MSP432P4XX__)
#include "msp432p4xx.h"
#elif defined (__MSP432P411Y__)
#include "msp432p411y.h"
/******************************************************************************
* Failed to match a default include file *
******************************************************************************/
#else
#error "Failed to match a default include file"
#endif
#endif /* __MSP432_H__ */

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