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shader: Add XMAD multiplication folding optimization
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@ -9,6 +9,7 @@
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#include "common/bit_cast.h"
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#include "common/bit_util.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/microinstruction.h"
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#include "shader_recompiler/ir_opt/passes.h"
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@ -99,8 +100,71 @@ void FoldGetPred(IR::Inst& inst) {
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}
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}
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/// Replaces the pattern generated by two XMAD multiplications
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bool FoldXmadMultiply(IR::Block& block, IR::Inst& inst) {
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/*
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* We are looking for this pattern:
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* %rhs_bfe = BitFieldUExtract %factor_a, #0, #16 (uses: 1)
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* %rhs_mul = IMul32 %rhs_bfe, %factor_b (uses: 1)
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* %lhs_bfe = BitFieldUExtract %factor_a, #16, #16 (uses: 1)
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* %rhs_mul = IMul32 %lhs_bfe, %factor_b (uses: 1)
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* %lhs_shl = ShiftLeftLogical32 %rhs_mul, #16 (uses: 1)
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* %result = IAdd32 %lhs_shl, %rhs_mul (uses: 10)
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*
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* And replacing it with
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* %result = IMul32 %factor_a, %factor_b
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*
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* This optimization has been proven safe by LLVM and MSVC.
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*/
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const IR::Value lhs_arg{inst.Arg(0)};
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const IR::Value rhs_arg{inst.Arg(1)};
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if (lhs_arg.IsImmediate() || rhs_arg.IsImmediate()) {
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return false;
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}
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IR::Inst* const lhs_shl{lhs_arg.InstRecursive()};
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if (lhs_shl->Opcode() != IR::Opcode::ShiftLeftLogical32 || lhs_shl->Arg(1) != IR::Value{16U}) {
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return false;
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}
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if (lhs_shl->Arg(0).IsImmediate()) {
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return false;
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}
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IR::Inst* const lhs_mul{lhs_shl->Arg(0).InstRecursive()};
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IR::Inst* const rhs_mul{rhs_arg.InstRecursive()};
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if (lhs_mul->Opcode() != IR::Opcode::IMul32 || rhs_mul->Opcode() != IR::Opcode::IMul32) {
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return false;
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}
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if (lhs_mul->Arg(1).Resolve() != rhs_mul->Arg(1).Resolve()) {
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return false;
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}
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const IR::U32 factor_b{lhs_mul->Arg(1)};
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if (lhs_mul->Arg(0).IsImmediate() || rhs_mul->Arg(0).IsImmediate()) {
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return false;
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}
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IR::Inst* const lhs_bfe{lhs_mul->Arg(0).InstRecursive()};
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IR::Inst* const rhs_bfe{rhs_mul->Arg(0).InstRecursive()};
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if (lhs_bfe->Opcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (rhs_bfe->Opcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (lhs_bfe->Arg(1) != IR::Value{16U} || lhs_bfe->Arg(2) != IR::Value{16U}) {
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return false;
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}
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if (rhs_bfe->Arg(1) != IR::Value{0U} || rhs_bfe->Arg(2) != IR::Value{16U}) {
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return false;
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}
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if (lhs_bfe->Arg(0).Resolve() != rhs_bfe->Arg(0).Resolve()) {
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return false;
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}
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const IR::U32 factor_a{lhs_bfe->Arg(0)};
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.ReplaceUsesWith(ir.IMul(factor_a, factor_b));
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return true;
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}
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template <typename T>
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void FoldAdd(IR::Inst& inst) {
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void FoldAdd(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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return;
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}
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@ -110,6 +174,12 @@ void FoldAdd(IR::Inst& inst) {
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const IR::Value rhs{inst.Arg(1)};
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if (rhs.IsImmediate() && Arg<T>(rhs) == 0) {
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inst.ReplaceUsesWith(inst.Arg(0));
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return;
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}
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if constexpr (std::is_same_v<T, u32>) {
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if (FoldXmadMultiply(block, inst)) {
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return;
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}
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}
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}
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@ -244,14 +314,14 @@ void FoldBranchConditional(IR::Inst& inst) {
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}
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}
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void ConstantPropagation(IR::Inst& inst) {
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void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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switch (inst.Opcode()) {
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case IR::Opcode::GetRegister:
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return FoldGetRegister(inst);
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case IR::Opcode::GetPred:
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return FoldGetPred(inst);
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case IR::Opcode::IAdd32:
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return FoldAdd<u32>(inst);
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return FoldAdd<u32>(block, inst);
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case IR::Opcode::ISub32:
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return FoldISub32(inst);
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case IR::Opcode::BitCastF32U32:
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@ -259,7 +329,7 @@ void ConstantPropagation(IR::Inst& inst) {
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case IR::Opcode::BitCastU32F32:
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return FoldBitCast<u32, f32>(inst, IR::Opcode::BitCastF32U32);
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case IR::Opcode::IAdd64:
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return FoldAdd<u64>(inst);
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return FoldAdd<u64>(block, inst);
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case IR::Opcode::Select32:
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return FoldSelect<u32>(inst);
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case IR::Opcode::LogicalAnd:
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@ -292,7 +362,9 @@ void ConstantPropagation(IR::Inst& inst) {
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} // Anonymous namespace
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void ConstantPropagationPass(IR::Block& block) {
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std::ranges::for_each(block, ConstantPropagation);
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for (IR::Inst& inst : block) {
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ConstantPropagation(block, inst);
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}
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}
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} // namespace Shader::Optimization
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