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fix lpc43xx isr issue, fix control status response for usbd
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d6dc1aa2e9
commit
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@ -242,33 +242,24 @@ bool tusb_dcd_control_xfer(uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uin
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LPC_USB0_Type* const lpc_usb = LPC_USB[port];
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dcd_data_t* const p_dcd = dcd_data_ptr[port];
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// determine Endpoint where Data & Status phase occurred (IN or OUT)
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uint8_t const ep_data = (dir == TUSB_DIR_IN) ? 1 : 0;
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uint8_t const ep_status = 1 - ep_data;
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uint8_t const ep_phy = (dir == TUSB_DIR_IN) ? 1 : 0;
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while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {} // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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// while(p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active) {}; // wait until previous device request is completed TODO add timeout
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dcd_qhd_t* qhd = &p_dcd->qhd[ep_phy];
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VERIFY( !(p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active) );
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// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {}
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//------------- Data Phase -------------//
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if (length > 0)
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{
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dcd_qtd_t* p_qtd_data = &p_dcd->qtd[0];
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qtd_init(p_qtd_data, p_buffer, length);
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p_dcd->qhd[ep_data].qtd_overlay.next = (uint32_t) p_qtd_data;
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VERIFY( !qhd->qtd_overlay.active );
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lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_data));
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}
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dcd_qtd_t* qtd = &p_dcd->qtd[0];
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qtd_init(qtd, p_buffer, length);
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//------------- Status Phase -------------//
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dcd_qtd_t* p_qtd_status = &p_dcd->qtd[1];
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qtd_init(p_qtd_status, NULL, 0); // zero length xfer
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p_qtd_status->int_on_complete = int_on_complete ? 1 : 0;
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// skip xfer complete for Status
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qtd->int_on_complete = (length > 0 ? 1 : 0);
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p_dcd->qhd[ep_status].qtd_overlay.next = (uint32_t) p_qtd_status;
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qhd->qtd_overlay.next = (uint32_t) qtd;
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lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_status));
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lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_phy));
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return true;
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}
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@ -465,13 +456,14 @@ void hal_dcd_isr(uint8_t port)
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//------------- Set up Received -------------//
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if (lpc_usb->ENDPTSETUPSTAT)
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{ // 23.10.10.2 Operational model for setup transfers
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{
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// 23.10.10.2 Operational model for setup transfers
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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tusb_dcd_setup_received(port, (uint8_t*) &p_dcd->qhd[0].setup_request);
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}
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//------------- Control Request Completed -------------//
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else if ( edpt_complete & 0x03 )
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else if ( edpt_complete & ( BIT_(0) | BIT_(16)) )
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{
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for(uint8_t ep_idx = 0; ep_idx < 2; ep_idx++)
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{
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@ -490,7 +482,7 @@ void hal_dcd_isr(uint8_t port)
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}
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//------------- Transfer Complete -------------//
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if ( edpt_complete & ~(0x03UL) )
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if ( edpt_complete & ~(BIT_(0) | BIT_(16)) )
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{
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xfer_complete_isr(port, edpt_complete);
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}
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@ -317,10 +317,10 @@ tusb_error_t usbd_control_request_subtask(uint8_t port, tusb_control_request_t c
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error = TUSB_ERROR_NONE;
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//------------- Standard Control e.g in enumeration -------------//
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if( TUSB_REQ_RCPT_DEVICE == p_request->bmRequestType_bit.recipient &&
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TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type )
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if( TUSB_REQ_RCPT_DEVICE == p_request->bmRequestType_bit.recipient &&
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TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type )
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{
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if ( TUSB_REQUEST_GET_DESCRIPTOR == p_request->bRequest )
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if ( TUSB_REQ_GET_DESCRIPTOR == p_request->bRequest )
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{
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uint8_t const * p_buffer = NULL;
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uint16_t length = 0;
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@ -329,18 +329,20 @@ tusb_error_t usbd_control_request_subtask(uint8_t port, tusb_control_request_t c
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if ( TUSB_ERROR_NONE == error )
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{
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OSAL_SUBTASK_INVOKED ( usbd_control_xfer_substak(port, (tusb_dir_t) p_request->bmRequestType_bit.direction, (uint8_t*) p_buffer, length ), error );;
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OSAL_SUBTASK_INVOKED ( usbd_control_xfer_substak(port, (tusb_dir_t) p_request->bmRequestType_bit.direction, (uint8_t*) p_buffer, length ), error );
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}
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}
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else if ( TUSB_REQUEST_SET_ADDRESS == p_request->bRequest )
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else if ( TUSB_REQ_SET_ADDRESS == p_request->bRequest )
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{
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tusb_dcd_set_address(port, (uint8_t) p_request->wValue);
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usbd_devices[port].state = TUSB_DEVICE_STATE_ADDRESSED;
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// TODO hack nrf52 auto handle set address
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#ifdef NRF52840_XXAA
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// nrf52 auto handle set address, no need to return status
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SUBTASK_RETURN(TUSB_ERROR_NONE);
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#endif
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}
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else if ( TUSB_REQUEST_SET_CONFIGURATION == p_request->bRequest )
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else if ( TUSB_REQ_SET_CONFIGURATION == p_request->bRequest )
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{
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usbd_set_configure_received(port, (uint8_t) p_request->wValue);
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}else
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@ -368,8 +370,8 @@ tusb_error_t usbd_control_request_subtask(uint8_t port, tusb_control_request_t c
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//------------- Endpoint Request -------------//
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else if ( TUSB_REQ_RCPT_ENDPOINT == p_request->bmRequestType_bit.recipient &&
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TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type &&
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TUSB_REQUEST_CLEAR_FEATURE == p_request->bRequest )
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TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type &&
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TUSB_REQ_CLEAR_FEATURE == p_request->bRequest )
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{
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tusb_dcd_edpt_clear_stall(port, u16_low_u8(p_request->wIndex) );
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} else
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@ -383,7 +385,7 @@ tusb_error_t usbd_control_request_subtask(uint8_t port, tusb_control_request_t c
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tusb_dcd_control_stall(port);
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}else if (p_request->wLength == 0)
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{
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usbd_control_status(port, (tusb_dir_t) p_request->bmRequestType_bit.direction);
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usbd_control_status(port, 1-p_request->bmRequestType_bit.direction);
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}
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OSAL_SUBTASK_END
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