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able to compile dcd 18/43 with rt1064

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hathach 2019-11-22 12:34:41 +07:00
parent 2ead26a12d
commit fca4653b95
1 changed files with 6 additions and 4 deletions
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10
src/portable/nxp/lpc18_43/dcd_lpc18_43.c
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@ -38,11 +38,13 @@
#if CFG_TUSB_MCU == OPT_MCU_RT10XX #if CFG_TUSB_MCU == OPT_MCU_RT10XX
#include "fsl_device_registers.h" #include "fsl_device_registers.h"
#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE } #define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
#else #else
#include "chip.h" #include "chip.h"
#define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE } #define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
IRQn_Type DCD_IRQn[] = { USB0_IRQn, USB1_IRQn };
#endif #endif
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
@ -270,12 +272,12 @@ void dcd_init(uint8_t rhport)
void dcd_int_enable(uint8_t rhport) void dcd_int_enable(uint8_t rhport)
{ {
NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn); NVIC_EnableIRQ(DCD_IRQn[rhport]);
} }
void dcd_int_disable(uint8_t rhport) void dcd_int_disable(uint8_t rhport)
{ {
NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn); NVIC_DisableIRQ(DCD_IRQn[rhport]);
} }
void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_set_address(uint8_t rhport, uint8_t dev_addr)