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add uf2 linker for metro m7 1011

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hathach 2023-02-13 12:29:31 +07:00
parent 49c621d510
commit fb5fd22c73
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3 changed files with 9 additions and 6 deletions
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5
hw/bsp/imxrt/boards/metro_m7_1011/board.mk
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@ -1,6 +1,9 @@
CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
MCU_VARIANT = MIMXRT1011
# LD file with uf2
LD_FILE = $(BOARD_PATH)/$(BOARD).ld
# For flash-jlink target
JLINK_DEVICE = MIMXRT1011DAE5A
@ -8,7 +11,7 @@ JLINK_DEVICE = MIMXRT1011DAE5A
PYOCD_TARGET = mimxrt1010
# flash using pyocd
flash: flash-pyocd
flash: flash-uf2
flash-uf2: $(BUILD)/$(PROJECT).uf2
@echo copying $<
@$(CP) $< /media/$(USER)/METROM7BOOT

3
hw/bsp/imxrt/family.c
View File

@ -57,8 +57,7 @@ void board_init(void)
{
// make sure the dcache is on.
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR))
SCB_EnableDCache();
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache();
#endif
// Init clock

7
hw/bsp/imxrt/family.mk
View File

@ -28,7 +28,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough -Wno-error
MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
# All source paths should be relative to the top level.
LD_FILE = $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
# TODO for net_lwip_webserver example, but may not needed !!
LDFLAGS += \
@ -62,7 +62,8 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
FREERTOS_PORT = ARM_CM7/r0p1
# UF2 generation, iMXRT need to strip to text only before conversion
APPLICATION_ADDR = 0x6000C000
$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
@echo CREATE $@
@$(OBJCOPY) -O ihex -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.hex
$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $(BUILD)/$(PROJECT)-textonly.hex
@$(OBJCOPY) -O binary -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.bin
$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b $(APPLICATION_ADDR) -c -o $@ $(BUILD)/$(PROJECT)-textonly.bin