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update ci build

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hathach 2021-04-18 15:44:50 +07:00
parent 0517377dcb
commit faae19f560
2 changed files with 2 additions and 0 deletions
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.github/workflows/build.yml vendored
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@ -49,6 +49,7 @@ jobs:
- 'samd21'
- 'samd51'
- 'saml22'
- 'stm32f0'
- 'stm32f4'
- 'stm32f7'
- 'stm32h7'

1
hw/bsp/stm32h7/family.c
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@ -72,6 +72,7 @@ void board_init(void)
__HAL_RCC_GPIOI_CLK_ENABLE(); // USB ULPI NXT
__HAL_RCC_GPIOJ_CLK_ENABLE();
// Enable UART Clock
UART_CLK_EN();
// 1ms tick timer