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stm32 update fifo in comment
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@ -82,7 +82,7 @@ static void bus_reset(void) {
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// Peripheral FIFO architecture (Rev18 RM 29.11)
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//
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// --------------- 312.5 ( 1250 bytes )
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// --------------- 320 ( 1280 bytes )
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// | IN FIFO 3 |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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@ -100,15 +100,11 @@ static void bus_reset(void) {
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// * 10 locations in hardware for setup packets + setup control words
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// (up to 3 setup packets).
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// * 2 locations for OUT endpoint control words.
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// * 16 + 1 (data + info) for largest packet size of 64 bytes.
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// * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
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// * 1 location for global NAK (not required/used here).
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//
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// However, for OUT FIFO, 10 + 2 + 16 = 28 doesn't seem to work (TODO: why?).
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// Minimum that works in practice is 35, so allocate 40 32-bit locations
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// as a buffer.
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//
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// It is recommended to allocate 2 times the largest packet size, therefore
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// Recommended value = 10 + 1 + 2 x (16+1) = 45 --> Let's make it 50
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// Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50
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USB_OTG_FS->GRXFSIZ = 50;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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@ -252,7 +248,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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} else {
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// Peripheral FIFO architecture (Rev18 RM 29.11)
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//
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// --------------- 312.5 ( 1250 bytes )
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// --------------- 320 ( 1280 bytes )
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// | IN FIFO 3 |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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@ -265,7 +261,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// | ( Shared ) |
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// --------------- 0
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//
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// Since OUT FIFO = 50, FIFO0 = 16, average of FIFOx = (312-50-16) / 3 = 82 ~ 80
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// Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (312-50-16) / 3 = 82 ~ 80
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | \
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(epnum - 1) << USB_OTG_DIEPCTL_TXFNUM_Pos | \
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