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bsp lpc17
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parent
934baae9b8
commit
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2
.github/workflows/build_arm.yml
vendored
2
.github/workflows/build_arm.yml
vendored
@ -35,7 +35,7 @@ jobs:
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- 'broadcom_32bit'
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- 'imxrt'
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- 'kinetis_k32 kinetis_kl'
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- 'lpc11 lpc13 lpc15 lpc18'
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- 'lpc11 lpc13 lpc15 lpc17 lpc18'
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- 'lpc51 lpc54 lpc55'
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- 'mm32 msp432e4'
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- 'nrf'
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8
hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
Normal file
8
hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
Normal file
@ -0,0 +1,8 @@
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/lpc1769.ld
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# For flash-jlink target
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JLINK_DEVICE = LPC1769
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# flash using jlink
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flash: flash-jlink
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9
hw/bsp/lpc17/boards/mbed1768/board.mk
Normal file
9
hw/bsp/lpc17/boards/mbed1768/board.mk
Normal file
@ -0,0 +1,9 @@
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/lpc1768.ld
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# For flash-jlink target
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JLINK_DEVICE = LPC1768
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PYOCD_TARGET = lpc1768
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# flash using pyocd
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flash: flash-pyocd
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@ -1,5 +1,8 @@
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DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
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MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
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include $(TOP)/$(BOARD_PATH)/board.mk
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CFLAGS += \
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-flto \
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-mthumb \
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@ -14,10 +17,10 @@ CFLAGS += \
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# lpc_types.h cause following errors
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CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
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MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
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# caused by freeRTOS port !!
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CFLAGS += -Wno-error=maybe-uninitialized
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/$(BOARD)/lpc1769.ld
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MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
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SRC_C += \
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src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
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@ -35,9 +38,3 @@ INC += \
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# For freeRTOS port source
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FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
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# For flash-jlink target
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JLINK_DEVICE = LPC1769
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# flash using jlink
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flash: flash-jlink
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@ -4,32 +4,6 @@ CFLAGS += \
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-DCPU_LPC51U68JBD64 \
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))'
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SRC_C += \
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src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
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$(MCU_DIR)/system_LPC51U68.c \
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$(MCU_DIR)/drivers/fsl_clock.c \
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$(MCU_DIR)/drivers/fsl_power.c \
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$(MCU_DIR)/drivers/fsl_reset.c \
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$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
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$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
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$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
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INC += \
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$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
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$(TOP)/$(MCU_DIR) \
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$(TOP)/$(MCU_DIR)/drivers \
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$(TOP)/$(SDK_DIR)/drivers/common \
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$(TOP)/$(SDK_DIR)/drivers/flexcomm \
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$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
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$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
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SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
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LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
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# For freeRTOS port source
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FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
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JLINK_DEVICE = LPC51U68
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PYOCD_TARGET = LPC51U68
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@ -1,44 +0,0 @@
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DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
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CFLAGS += \
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-flto \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m3 \
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-nostdlib \
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-DCORE_M3 \
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-D__USE_LPCOPEN \
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-DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
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-DRTC_EV_SUPPORT=0
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# startup.c and lpc_types.h cause following errors
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CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
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MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/$(BOARD)/lpc1768.ld
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SRC_C += \
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src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
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$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
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$(MCU_DIR)/src/chip_17xx_40xx.c \
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$(MCU_DIR)/src/clock_17xx_40xx.c \
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$(MCU_DIR)/src/gpio_17xx_40xx.c \
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$(MCU_DIR)/src/iocon_17xx_40xx.c \
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$(MCU_DIR)/src/sysctl_17xx_40xx.c \
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$(MCU_DIR)/src/sysinit_17xx_40xx.c \
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$(MCU_DIR)/src/uart_17xx_40xx.c
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INC += \
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$(TOP)/$(MCU_DIR)/inc
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# For freeRTOS port source
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FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
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# For flash-jlink target
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JLINK_DEVICE = LPC1768
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# flash using pyocd
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flash: $(BUILD)/$(PROJECT).hex
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pyocd flash -t lpc1768 $<
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