update all dwc2 ports to support new dynamic controller support

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -34,6 +34,13 @@
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
+// Following symbols must be defined by port header
+// - _dwc2_controller[]: array of controllers
+// - DWC2_EP_MAX: largest EP counts of all controllers
+// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
+// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
+// - dwc2_remote_wakeup_delay
+
 #if defined(TUP_USBIP_DWC2_STM32)
   #include "dwc2_stm32.h"
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
@@ -50,8 +57,6 @@
   #error "Unsupported MCUs"
 #endif
 
-// Note _dwc2_controller[] must be defined by port header
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -467,6 +472,7 @@ static bool check_dwc2(dwc2_regs_t * dwc2)
 #endif
 
   // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+  (void) dwc2;
 #if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
   uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
   TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);

src/portable/synopsys/dwc2/dwc2_bcm.h

@@ -35,9 +35,12 @@
 #include "broadcom/interrupts.h"
 #include "broadcom/caches.h"
 
-#define DWC2_REG_BASE       USB_OTG_GLOBAL_BASE
 #define DWC2_EP_MAX         8
-#define DWC2_EP_FIFO_SIZE   4096
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 }
+};
 
 #define dcache_clean(_addr, _size)              data_clean(_addr, _size)
 #define dcache_invalidate(_addr, _size)         data_invalidate(_addr, _size)
@@ -46,15 +49,13 @@
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
+  BP_EnableIRQ(_dwc2_controller[rhport].irqnum);
-  BP_EnableIRQ(USB_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
+  BP_DisableIRQ(_dwc2_controller[rhport].irqnum);
-  BP_DisableIRQ(USB_IRQn);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)

src/portable/synopsys/dwc2/dwc2_efm32.h

@@ -37,20 +37,22 @@
 // EFM32 has custom control register before DWC registers
 #define DWC2_REG_BASE       (USB_BASE + offsetof(USB_TypeDef, GOTGCTL))
 #define DWC2_EP_MAX         7
-#define DWC2_EP_FIFO_SIZE   2048
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = DWC2_REG_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+};
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
+  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
-  NVIC_EnableIRQ(USB_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
+  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
-  NVIC_DisableIRQ(USB_IRQn);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -37,10 +37,12 @@
 //#include "soc/usb_periph.h"
 
 #define DWC2_REG_BASE       0x60080000UL
-#define DWC2_EP_MAX         5             // USB_OUT_EP_NUM
+#define DWC2_EP_MAX         6             // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
-#define DWC2_EP_FIFO_SIZE   1024
 
-// #define EP_FIFO_NUM 5
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
+};
 
 static intr_handle_t usb_ih;
 

src/portable/synopsys/dwc2/dwc2_gd32.h

@@ -34,8 +34,11 @@
 
 #define DWC2_REG_BASE       0x50000000UL
 #define DWC2_EP_MAX         4
-#define DWC2_EP_FIFO_SIZE   1280
+
-#define RHPORT_IRQn         86
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = DWC2_REG_BASE, .irqnum = 86, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1280 }
+};
 
 extern uint32_t SystemCoreClock;
 
@@ -57,15 +60,13 @@ static inline void __eclic_disable_interrupt (uint32_t irq){
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
+  __eclic_enable_interrupt(_dwc2_controller[rhport].irqnum);
-  __eclic_enable_interrupt(RHPORT_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
+  __eclic_disable_interrupt(_dwc2_controller[rhport].irqnum);
-  __eclic_disable_interrupt(RHPORT_IRQn);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)

src/portable/synopsys/dwc2/dwc2_stm32.h

@@ -83,31 +83,16 @@
   #define DWC2_EP_MAX   EP_MAX_FS
 #endif
 
-// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
-//#if TUD_OPT_RHPORT == 0
-//  #define DWC2_REG_BASE       USB_OTG_FS_PERIPH_BASE
-//  #define DWC2_EP_MAX         EP_MAX_FS
-//  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_FS
-//  #define RHPORT_IRQn         OTG_FS_IRQn
-//
-//#else
-//  #define DWC2_REG_BASE       USB_OTG_HS_PERIPH_BASE
-//  #define DWC2_EP_MAX         EP_MAX_HS
-//  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_HS
-//  #define RHPORT_IRQn         OTG_HS_IRQn
-//
-//#endif
-
 // On STM32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] =
 {
 #ifdef USB_OTG_FS_PERIPH_BASE
-  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS},
+  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
 #endif
 
 #ifdef USB_OTG_HS_PERIPH_BASE
-  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS},
+  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
 #endif
 };
 

src/portable/synopsys/dwc2/dwc2_type.h

@@ -26,10 +26,10 @@
 // Controller
 typedef struct
 {
-  uint32_t reg_base;
+  uintptr_t reg_base;
-  uint32_t irqnum;
+  uint32_t  irqnum;
-  uint8_t  ep_count;
+  uint8_t   ep_count;
-  uint32_t ep_fifo_size;
+  uint32_t  ep_fifo_size;
 }dwc2_controller_t;
 
 /* DWC OTG HW Release versions */

src/portable/synopsys/dwc2/dwc2_xmc.h

@@ -34,23 +34,24 @@
 
 #include "xmc_device.h"
 
-// XMC has custom control register before DWC registers
-#define DWC2_REG_BASE       USB0_BASE
 #define DWC2_EP_MAX         7
-#define DWC2_EP_FIFO_SIZE   2048
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  // Note: XMC has some custom control registers before DWC registers
+  { .reg_base = USB0_BASE, .irqnum = USB0_0_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+};
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
+  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
-  NVIC_EnableIRQ(USB0_0_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
+  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
-  NVIC_DisableIRQ(USB0_0_IRQn);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)