diff --git a/hw/bsp/ea4357/emac.c b/hw/bsp/ea4357/emac.c deleted file mode 100644 index fce042259..000000000 --- a/hw/bsp/ea4357/emac.c +++ /dev/null @@ -1,480 +0,0 @@ -/****************************************************************** - ***** ***** - ***** Name: cs8900.c ***** - ***** Ver.: 1.0 ***** - ***** Date: 07/05/2001 ***** - ***** Auth: Andreas Dannenberg ***** - ***** HTWK Leipzig ***** - ***** university of applied sciences ***** - ***** Germany ***** - ***** Func: ethernet packet-driver for use with LAN- ***** - ***** controller CS8900 from Crystal/Cirrus Logic ***** - ***** ***** - ***** NXP: Module modified for use with NXP ***** - ***** lpc43xx EMAC Ethernet controller ***** - ***** ***** - ******************************************************************/ - -#include "../board.h" - -#if BOARD == BOARD_EA4357 - -#include "emac.h" -//#include "tcpip.h" -#include "LPC43xx.h" -#include "lpc43xx_scu.h" -#include "lpc43xx_rgu.h" - -#define TIMEOUT 100000 - -static unsigned short *rptr; -static unsigned short *tptr; - -static unsigned int TxDescIndex = 0; -static unsigned int RxDescIndex = 0; - -// Keil: function added to write PHY -static void write_PHY (unsigned int PhyReg, unsigned short Value) { - - unsigned int tout; - - /* Write a data 'Value' to PHY register 'PhyReg'. */ - while(LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY); // Check GMII busy bit - LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | GMII_WRITE; - LPC_ETHERNET->MAC_MII_DATA = Value; - LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; // Start PHY Write Cycle - - /* Wait utill operation completed */ - for (tout = 0; tout < MII_WR_TOUT; tout++) { - if ((LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY) == 0) { - break; - } - } - if (tout == MII_WR_TOUT) // Trap the timeout - while(1); -} - - -// Keil: function added to read PHY -static unsigned short read_PHY (unsigned int PhyReg) { - - unsigned int tout, val; - - /* Read a PHY register 'PhyReg'. */ - while(LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY); // Check GMII busy bit - LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | GMII_READ; - LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; // Start PHY Read Cycle - - /* Wait until operation completed */ - for (tout = 0; tout < MII_RD_TOUT; tout++) { - if ((LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY) == 0) { - break; - } - } - if (tout == MII_RD_TOUT) // Trap the timeout - while(1); - val = LPC_ETHERNET->MAC_MII_DATA; - return (val); -} - - -// Keil: function added to initialize Rx Descriptors -void rx_descr_init (void) -{ - unsigned int i; - - for (i = 0; i < NUM_RX_DESC; i++) { - RX_DESC_STAT(i) = OWN_BIT; - RX_DESC_CTRL(i) = ETH_FRAG_SIZE; - RX_BUFADDR(i) = RX_BUF(i); - if (i == (NUM_RX_DESC-1)) // Last Descriptor? - RX_DESC_CTRL(i) |= RX_END_RING; - } - - /* Set Starting address of RX Descriptor list */ - LPC_ETHERNET->DMA_REC_DES_ADDR = RX_DESC_BASE; -} - - -// Keil: function added to initialize Tx Descriptors -void tx_descr_init (void) -{ - unsigned int i; - - for (i = 0; i < NUM_TX_DESC; i++) { // Take it out!!!! - TX_DESC_STAT(i) = 0; - TX_DESC_CTRL(i) = 0; - TX_BUFADDR(i) = 0; - } - - for (i = 0; i < NUM_TX_DESC; i++) { - TX_DESC_STAT(i) = TX_LAST_SEGM | TX_FIRST_SEGM; - TX_DESC_CTRL(i) = 0; - TX_BUFADDR(i) = TX_BUF(i); - if (i == (NUM_TX_DESC-1)) // Last Descriptor? - TX_DESC_STAT(i) |= TX_END_RING; - } - - /* Set Starting address of RX Descriptor list */ - LPC_ETHERNET->DMA_TRANS_DES_ADDR = TX_DESC_BASE; -} - - - -// configure port-pins for use with LAN-controller, -// reset it and send the configuration-sequence - -void Init_EMAC(void) -{ - int id1, id2, tout, regv; - unsigned phy_in_use = 0; - - /* Ethernet pins configuration */ -#if MII - scu_pinmux(0xC ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDC: PC_1 -> FUNC3 - scu_pinmux(0x1 ,17 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDIO: P1_17 -> FUNC3 - scu_pinmux(0x1 ,18 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD0: P1_18 -> FUNC3 - scu_pinmux(0x1 ,20 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD1: P1_20 -> FUNC3 - scu_pinmux(0x1 ,19 , (MD_PLN | MD_EZI | MD_ZI), FUNC0); // ENET_REF: P1_19 -> FUNC0 (default) - -// scu_pinmux(0xC ,4 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_EN: PC_4 -> FUNC3 - scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC6); // ENET_TX_EN: P0_1 -> FUNC6 - - scu_pinmux(0x1 ,15 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD0: P1_15 -> FUNC3 - scu_pinmux(0x0 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_RXD1: P0_0 -> FUNC2 - -// scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_CRS: P1_16 -> FUNC3 - scu_pinmux(0x9 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_CRS: P9_0 -> FUNC5 - -// scu_pinmux(0xC ,9 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RX_ER: PC_9 -> FUNC3 - scu_pinmux(0x9 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RX_ER: P9_1 -> FUNC5 - -// scu_pinmux(0xC ,8 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXDV: PC_8 -> FUNC3 - scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC7); // ENET_RXDV: P1_16 -> FUNC7 - -#else - scu_pinmux(0xC ,1 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDC: PC_1 -> FUNC3 - scu_pinmux(0x1 ,17 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDIO: P1_17 -> FUNC3 - scu_pinmux(0x1 ,18 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD0: P1_18 -> FUNC3 - scu_pinmux(0x1 ,20 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD1: P1_20 -> FUNC3 - scu_pinmux(0x1 ,19 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0); // ENET_REF: P1_19 -> FUNC0 (default) -// scu_pinmux(0xC ,4 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_EN: PC_4 -> FUNC3 - scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC6); // ENET_TX_EN: P0_1 -> FUNC6 - scu_pinmux(0x1 ,15 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD0: P1_15 -> FUNC3 - scu_pinmux(0x0 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_RXD1: P0_0 -> FUNC2 -// scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_CRS: P1_16 -> FUNC3 -// scu_pinmux(0x9 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_CRS: P9_0 -> FUNC5 -// scu_pinmux(0xC ,9 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RX_ER: PC_9 -> FUNC3 -// scu_pinmux(0x9 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RX_ER: P9_1 -> FUNC5 -// scu_pinmux(0xC ,8 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXDV: PC_8 -> FUNC3 - scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC7); // ENET_RXDV: P1_16 -> FUNC7 -#endif - - -#if MII /* Select MII interface */ // check MUXING for new Eagle... -// scu_pinmux(0xC ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD2: PC_6 -> FUNC3 - scu_pinmux(0x9 ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RXD2: P9_3 -> FUNC5 - -// scu_pinmux(0xC ,7 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD3: PC_7 -> FUNC3 - scu_pinmux(0x9 ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RXD3: P9_2 -> FUNC5 - - scu_pinmux(0xC ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXLK: PC_0 -> FUNC3 - -// scu_pinmux(0xC ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD2: PC_2 -> FUNC3 - scu_pinmux(0x9 ,4 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_TXD2: P9_4 -> FUNC5 - -// scu_pinmux(0xC ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD3: PC_3 -> FUNC3 - scu_pinmux(0x9 ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_TXD3: P9_5 -> FUNC5 - -// scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3 - scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3 - -// scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_COL: P0_1 -> FUNC2 - scu_pinmux(0x9 ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_COL: P9_6 -> FUNC5 -#else /* Select RMII interface */ - LPC_CREG->CREG6 |= RMII_SELECT; -#endif - - - RGU_SoftReset(RGU_SIG_ETHERNET); - while(1){ // Confirm the reset happened - if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1<DMA_BUS_MODE |= DMA_SOFT_RESET; // Reset all GMAC Subsystem internal registers and logic - while(LPC_ETHERNET->DMA_BUS_MODE & DMA_SOFT_RESET); // Wait for software reset completion - - /* Put the DP83848C in reset mode */ - write_PHY (PHY_REG_BMCR, PHY_BMCR_RESET); - - /* Wait for hardware reset to end. */ - for (tout = 0; tout < TIMEOUT; tout++) { - regv = read_PHY (PHY_REG_BMCR); - if (!(regv & PHY_BMCR_RESET)) { - /* Reset complete */ - break; - } - } - - /* Check if this is a DP83848C PHY. */ - id1 = read_PHY (PHY_REG_IDR1); - id2 = read_PHY (PHY_REG_IDR2); - if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) { - phy_in_use = DP83848C_ID; - } - else if (((id1 << 16) | (id2 & 0xFFF0)) == LAN8720_ID) { - phy_in_use = LAN8720_ID; - } - - if (phy_in_use != 0) { - /* Configure the PHY device */ -#if !MII - write_PHY (PHY_REG_RBR, 0x20); -#endif - - /* Use autonegotiation about the link speed. */ - write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); - /* Wait to complete Auto_Negotiation. */ - for (tout = 0; tout < TIMEOUT; tout++) { - regv = read_PHY (PHY_REG_BMSR); - if (regv & PHY_AUTO_NEG_DONE) { - /* Autonegotiation Complete. */ - break; - } - } - } - - - - /* Check the link status. */ - for (tout = 0; tout < TIMEOUT; tout++) { - regv = read_PHY (PHY_REG_STS); - if (regv & LINK_VALID_STS) { - /* Link is on. */ - break; - } - } - - // Configure the EMAC with the established parameters - switch (phy_in_use) { - case DP83848C_ID: - - /* Configure Full/Half Duplex mode. */ - if (regv & FULL_DUP_STS) { - /* Full duplex is enabled. */ - LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE; - } - - /* Configure 100MBit/10MBit mode. */ - if (~(regv & SPEED_10M_STS)) { - /* 100MBit mode. */ - LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS; - } - -// value = ReadFromPHY (PHY_REG_STS); /* PHY Extended Status Register */ -// // Now configure for full/half duplex mode -// if (value & 0x0004) { -// // We are in full duplex is enabled mode -// LPC_ETHERNET->MAC2 |= MAC2_FULL_DUP; -// LPC_ETHERNET->Command |= CR_FULL_DUP; -// LPC_ETHERNET->IPGT = IPGT_FULL_DUP; -// } -// else { -// // Otherwise we are in half duplex mode -// LPC_ETHERNET->IPGT = IPGT_HALF_DUP; -// } - -// // Now configure 100MBit or 10MBit mode -// if (value & 0x0002) { -// // 10MBit mode -// LPC_ETHERNET->SUPP = 0; -// } -// else { -// // 100MBit mode -// LPC_ETHERNET->SUPP = SUPP_SPEED; -// } - break; - - case LAN8720_ID: - - regv = read_PHY (PHY_REG_SCSR); /* PHY Extended Status Register */ - // Now configure for full/half duplex mode - if (regv & (1<<4)) { /* bit 4: 1 = Full Duplex, 0 = Half Duplex */ - // We are in full duplex is enabled mode - LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE; - } - - // Now configure 100MBit or 10MBit mode - if (regv & (1<<3)) { /* bit 3: 1 = 100Mbps, 0 = 10Mbps */ - // 100MBit mode - LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS; - } - - - break; - - } - - /* Set the Ethernet MAC Address registers */ - LPC_ETHERNET->MAC_ADDR0_HIGH = (MYMAC_6 << 8) | MYMAC_5; - LPC_ETHERNET->MAC_ADDR0_LOW = (MYMAC_4 << 24) | (MYMAC_3 << 16) | (MYMAC_2 << 8) | MYMAC_1; - - /* Initialize Descriptor Lists */ - rx_descr_init(); - tx_descr_init(); - - /* Configure Filter */ - LPC_ETHERNET->MAC_FRAME_FILTER = MAC_PROMISCUOUS | MAC_RECEIVEALL; - - /* Enable Receiver and Transmitter */ - LPC_ETHERNET->MAC_CONFIG |= (MAC_TX_ENABLE | MAC_RX_ENABLE); - - /* Enable interrupts */ - //LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE | DMA_INT_TRANSMIT; - - /* Start Transmission & Receive processes */ - LPC_ETHERNET->DMA_OP_MODE |= (DMA_SS_TRANSMIT | DMA_SS_RECEIVE ); - -} - - -// reads a word in little-endian byte order from RX_BUFFER - -unsigned short ReadFrame_EMAC(void) -{ - return (*rptr++); -} - - -// easyWEB internal function -// help function to swap the byte order of a WORD - -unsigned short SwapBytes(unsigned short Data) -{ - return (Data >> 8) | (Data << 8); -} - -// reads a word in big-endian byte order from RX_FRAME_PORT -// (useful to avoid permanent byte-swapping while reading -// TCP/IP-data) - -unsigned short ReadFrameBE_EMAC(void) -{ - unsigned short ReturnValue; - - ReturnValue = SwapBytes (*rptr++); - return (ReturnValue); -} - - -// copies bytes from frame port to MCU-memory -// NOTES: * an odd number of byte may only be transfered -// if the frame is read to the end! -// * MCU-memory MUST start at word-boundary - -void CopyFromFrame_EMAC(void *Dest, unsigned short Size) -{ - unsigned short * piDest; // Keil: Pointer added to correct expression - - piDest = Dest; // Keil: Line added - while (Size > 1) { - *piDest++ = ReadFrame_EMAC(); - Size -= 2; - } - - if (Size) { // check for leftover byte... - *(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0 - } // for the highbyte -} - -// does a dummy read on frame-I/O-port -// NOTE: only an even number of bytes is read! - -void DummyReadFrame_EMAC(unsigned short Size) // discards an EVEN number of bytes -{ // from RX-fifo - while (Size > 1) { - ReadFrame_EMAC(); - Size -= 2; - } -} - -// Reads the length of the received ethernet frame and checks if the -// destination address is a broadcast message or not -// returns the frame length -unsigned short StartReadFrame(void) { - unsigned short RxLen; - - if ((RX_DESC_STAT(RxDescIndex) & OWN_BIT) == 0) { - RxLen = (RX_DESC_STAT(RxDescIndex) >> 16) & 0x03FFF; - rptr = (unsigned short *)RX_BUFADDR(RxDescIndex); - return(RxLen); - } - return 0; - -} - -void EndReadFrame(void) { - - RX_DESC_STAT(RxDescIndex) = OWN_BIT; - RxDescIndex++; - if (RxDescIndex == NUM_RX_DESC) - RxDescIndex = 0; -} - -unsigned int CheckFrameReceived(void) { // Packet received ? - - if ((RX_DESC_STAT(RxDescIndex) & OWN_BIT) == 0) - return(1); - else - return(0); -} - -// requests space in EMAC memory for storing an outgoing frame - -void RequestSend(unsigned short FrameSize) -{ - tptr = (unsigned short *)TX_BUFADDR(TxDescIndex); - TX_DESC_CTRL(TxDescIndex) = FrameSize; -} - -// check if ethernet controller is ready to accept the -// frame we want to send - -unsigned int Rdy4Tx(void) -{ - return (1); // the ethernet controller transmits much faster -} // than the CPU can load its buffers - - -// writes a word in little-endian byte order to TX_BUFFER -void WriteFrame_EMAC(unsigned short Data) -{ - *tptr++ = Data; -} - -// copies bytes from MCU-memory to frame port -// NOTES: * an odd number of byte may only be transfered -// if the frame is written to the end! -// * MCU-memory MUST start at word-boundary - -void CopyToFrame_EMAC(void *Source, unsigned int Size) -{ - unsigned short * piSource; -// unsigned int idx; - - piSource = Source; - Size = (Size + 1) & 0xFFFE; // round Size up to next even number - while (Size > 0) { - WriteFrame_EMAC(*piSource++); - Size -= 2; - } - TX_DESC_STAT(TxDescIndex) |= OWN_BIT; - LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode - TxDescIndex++; - if (TxDescIndex == NUM_TX_DESC) - TxDescIndex = 0; -} - -#endif - diff --git a/hw/bsp/ea4357/emac.h b/hw/bsp/ea4357/emac.h deleted file mode 100644 index b9f0c3baa..000000000 --- a/hw/bsp/ea4357/emac.h +++ /dev/null @@ -1,157 +0,0 @@ -#ifndef __EMAC_H -#define __EMAC_H - - -/* Configuration */ - -/* Interface Selection */ -#define MII 0 // =0 RMII - =1 MII - -/* MAC Configuration */ -#define MYMAC_1 0x1EU /* our ethernet (MAC) address */ -#define MYMAC_2 0x30U /* (MUST be unique in LAN!) */ -#define MYMAC_3 0x6cU -#define MYMAC_4 0xa2U -#define MYMAC_5 0x45U -#define MYMAC_6 0x5eU - - -#define ETH_FRAG_SIZE 1536 -#define NUM_RX_DESC 3 -#define NUM_TX_DESC 3 - -/* End of Configuration */ - - -/* EMAC Descriptors and Buffers located in 16K SRAM */ -/* Rx Descriptors */ -#define RX_DESC_BASE 0x20008000 -#define RX_STAT_BASE RX_DESC_BASE -#define RX_CTRL_BASE (RX_STAT_BASE + 4) -#define RX_BUFADDR_BASE (RX_CTRL_BASE + 4) -#define RX_NEXTDESC_BASE (RX_BUFADDR_BASE + 4) -#define RX_BUF_BASE (RX_DESC_BASE + NUM_RX_DESC*16) - -#define RX_DESC_STAT(i) (*(unsigned int *)(RX_STAT_BASE + 16*i)) -#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_CTRL_BASE + 16*i)) -#define RX_BUFADDR(i) (*(unsigned int *)(RX_BUFADDR_BASE + 16*i)) -#define RX_NEXTDESC(i) (*(unsigned int *)(RX_NEXTDESC_BASE + 16*i)) -#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) - -/* Tx Descriptors */ -#define TX_DESC_BASE RX_BUF_BASE + (ETH_FRAG_SIZE * NUM_RX_DESC) -#define TX_STAT_BASE TX_DESC_BASE -#define TX_CTRL_BASE (TX_STAT_BASE + 4) -#define TX_BUFADDR_BASE (TX_CTRL_BASE + 4) -#define TX_NEXTDESC_BASE (TX_BUFADDR_BASE + 4) -#define TX_BUF_BASE (TX_DESC_BASE + NUM_TX_DESC*16) - -#define TX_DESC_STAT(i) (*(unsigned int *)(TX_STAT_BASE + 16*i)) -#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_CTRL_BASE + 16*i)) -#define TX_BUFADDR(i) (*(unsigned int *)(TX_BUFADDR_BASE + 16*i)) -#define TX_NEXTDESC(i) (*(unsigned int *)(TX_NEXTDESC_BASE + 16*i)) -#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) - -/* Descriptors Fields bits */ -#define OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */ -#define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */ -#define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */ -#define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */ -#define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */ -#define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */ -#define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */ - - - - - -/* EMAC Control and Status bits */ -#define MAC_RX_ENABLE (1<<2) /* Receiver Enable in MAC_CONFIG reg */ -#define MAC_TX_ENABLE (1<<3) /* Transmitter Enable in MAC_CONFIG reg */ -#define MAC_PADCRC_STRIP (1<<7) /* Automatic Pad-CRC Stripping in MAC_CONFIG reg */ -#define MAC_DUPMODE (1<<11) /* Duplex Mode in MAC_CONFIG reg */ -#define MAC_100MPS (1<<14) /* Speed is 100Mbps in MAC_CONFIG reg */ -#define MAC_PROMISCUOUS (1U<<0) /* Promiscuous Mode bit in MAC_FRAME_FILTER reg */ -#define MAC_DIS_BROAD (1U<<5) /* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */ -#define MAC_RECEIVEALL (1U<<31) /* Receive All bit in MAC_FRAME_FILTER reg */ -#define DMA_SOFT_RESET 0x01 /* Software Reset bit in DMA_BUS_MODE reg */ -#define DMA_SS_RECEIVE (1<<1) /* Start/Stop Receive bit in DMA_OP_MODE reg */ -#define DMA_SS_TRANSMIT (1<<13) /* Start/Stop Transmission bit in DMA_OP_MODE reg */ -#define DMA_INT_TRANSMIT (1<<0) /* Transmit Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_OVERFLOW (1<<4) /* Overflow Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_UNDERFLW (1<<5) /* Underflow Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_RECEIVE (1<<6) /* Receive Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_ABN_SUM (1<<15) /* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */ -#define DMA_INT_NOR_SUM (1<<16) /* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */ - -/* MII Management Command Register */ -#define GMII_READ (0<<1) /* GMII Read PHY */ -#define GMII_WRITE (1<<1) /* GMII Write PHY */ -#define GMII_BUSY 0x00000001 /* GMII is Busy / Start Read/Write */ -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -/* PHY Control and Status bits */ -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */ -#define PHY_AUTO_NEG_DONE 0x0020 /* AutoNegotiation Complete in BMSR PHY reg */ -#define PHY_BMCR_RESET 0x8000 /* Reset bit at BMCR PHY reg */ -#define LINK_VALID_STS 0x0001 /* Link Valid Status at REG_STS PHY reg */ -#define FULL_DUP_STS 0x0004 /* Full Duplex Status at REG_STS PHY reg */ -#define SPEED_10M_STS 0x0002 /* 10Mbps Status at REG_STS PHY reg */ - -#define DP83848C_DEF_ADR 0x01 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier (without Rev. info */ - -#define LAN8720_ID 0x0007C0F0 /* PHY Identifier */ -#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ - -/* Misc */ -#define ETHERNET_RST 22 /* Reset Output for EMAC at RGU */ -#define RMII_SELECT 0x04 /* Select RMII in EMACCFG */ - - -/* Prototypes */ -void Init_EMAC(void); -unsigned short ReadFrameBE_EMAC(void); -void CopyToFrame_EMAC(void *Source, unsigned int Size); -void CopyFromFrame_EMAC(void *Dest, unsigned short Size); -void DummyReadFrame_EMAC(unsigned short Size); -unsigned short StartReadFrame(void); -void EndReadFrame(void); -unsigned int CheckFrameReceived(void); -void RequestSend(unsigned short FrameSize); -unsigned int Rdy4Tx(void); - - -#endif diff --git a/hw/bsp/ea4357/nand.c b/hw/bsp/ea4357/nand.c deleted file mode 100644 index 21ec14fbe..000000000 --- a/hw/bsp/ea4357/nand.c +++ /dev/null @@ -1,546 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ - - -/****************************************************************************** - * Includes - *****************************************************************************/ -#include "../board.h" - -#if BOARD == BOARD_EA4357 - -#include "lpc_types.h" -#include "lpc43xx_scu.h" -#include "lpc43xx_timer.h" -#include "nand.h" - - -/****************************************************************************** - * Defines and typedefs - *****************************************************************************/ - -#define K9F1G_CLE ((volatile uint8_t *)0x1D100000) -#define K9F1G_ALE ((volatile uint8_t *)0x1D080000) -#define K9F1G_DATA ((volatile uint8_t *)0x1D000000) - -#define K9FXX_WAIT() - -#define K9FXX_READ_1 0x00 -#define K9FXX_READ_2 0x30 - -#define K9FXX_SET_ADDR_A 0x00 -#define K9FXX_SET_ADDR_B 0x01 -#define K9FXX_SET_ADDR_C 0x50 -#define K9FXX_READ_ID 0x90 -#define K9FXX_RESET 0xff -#define K9FXX_BLOCK_PROGRAM_1 0x80 -#define K9FXX_BLOCK_PROGRAM_2 0x10 -#define K9FXX_BLOCK_ERASE_1 0x60 -#define K9FXX_BLOCK_ERASE_2 0xd0 -#define K9FXX_READ_STATUS 0x70 -#define K9FXX_BUSY (1 << 6) -#define K9FXX_OK (1 << 0) - -#define ID_MARKER_CODE (0xEC) -#define ID_SAMSUNG (0xF1) - -#define ID_PAGE_SZ_1KB (0x00) -#define ID_PAGE_SZ_2KB (0x01) -#define ID_PAGE_SZ_4KB (0x02) -#define ID_PAGE_SZ_8KB (0x03) - -#define ID_BLOCK_SZ_64KB (0x00) -#define ID_BLOCK_SZ_128KB (0x01) -#define ID_BLOCK_SZ_256KB (0x02) -#define ID_BLOCK_SZ_512KB (0x03) - -#define ID_PAGE_SZ_1KB (0x00) -#define ID_PAGE_SZ_2KB (0x01) -#define ID_PAGE_SZ_4KB (0x02) -#define ID_PAGE_SZ_8KB (0x03) - -#define ID_REDUND_SZ_8 (0x00) -#define ID_REDUND_SZ_16 (0x01) - - - -/* This macro could be changed to check the ready pin */ -#define WAIT_READY() (TIM_Waitus(25)) - - -/****************************************************************************** - * External global variables - *****************************************************************************/ - -/****************************************************************************** - * Local variables - *****************************************************************************/ - -static uint32_t pageSize = 0; -static uint32_t blockSize = 0; -static uint32_t reduntSize = 0; - - -/****************************************************************************** - * Local Functions - *****************************************************************************/ - -static void pinConfig(void) -{ - /* Set up EMC pin */ - scu_pinmux( 2 , 9 , MD_PLN_FAST , 3 );//A0 - scu_pinmux( 2 , 10 , MD_PLN_FAST , 3 );//A1 - scu_pinmux( 2 , 11 , MD_PLN_FAST , 3 );//A2 - scu_pinmux( 2 , 12 , MD_PLN_FAST , 3 );//A3 - scu_pinmux( 2 , 13 , MD_PLN_FAST , 3 );//A4 - scu_pinmux( 1 , 0 , MD_PLN_FAST , 2 );//A5 - scu_pinmux( 1 , 1 , MD_PLN_FAST , 2 );//A6 - scu_pinmux( 1 , 2 , MD_PLN_FAST , 2 );//A7 - scu_pinmux( 2 , 8 , MD_PLN_FAST , 3 );//A8 - scu_pinmux( 2 , 7 , MD_PLN_FAST , 3 );//A9 - scu_pinmux( 2 , 6 , MD_PLN_FAST , 2 );//A10 - scu_pinmux( 2 , 2 , MD_PLN_FAST , 2 );//A11 - scu_pinmux( 2 , 1 , MD_PLN_FAST , 2 );//A12 - scu_pinmux( 2 , 0 , MD_PLN_FAST , 2 );//A13 - scu_pinmux( 6 , 8 , MD_PLN_FAST , 1 );//A14 - scu_pinmux( 6 , 7 , MD_PLN_FAST , 1 );//A15 - scu_pinmux( 13 , 16 , MD_PLN_FAST , 2 );//A16 - scu_pinmux( 13 , 15 , MD_PLN_FAST , 2 );//A17 - scu_pinmux( 14 , 0 , MD_PLN_FAST , 3 );//A18 - scu_pinmux( 14 , 1 , MD_PLN_FAST , 3 );//A19 - scu_pinmux( 14 , 2 , MD_PLN_FAST , 3 );//A20 - scu_pinmux( 14 , 3 , MD_PLN_FAST , 3 );//A21 - scu_pinmux( 14 , 4 , MD_PLN_FAST , 3 );//A22 - scu_pinmux( 10 , 4 , MD_PLN_FAST , 3 );//A23 - - scu_pinmux( 1 , 7 , MD_PLN_FAST , 3 );//D0 - scu_pinmux( 1 , 8 , MD_PLN_FAST , 3 );//D1 - scu_pinmux( 1 , 9 , MD_PLN_FAST , 3 );//D2 - scu_pinmux( 1 , 10 , MD_PLN_FAST , 3 );//D3 - scu_pinmux( 1 , 11 , MD_PLN_FAST , 3 );//D4 - scu_pinmux( 1 , 12 , MD_PLN_FAST , 3 );//D5 - scu_pinmux( 1 , 13 , MD_PLN_FAST , 3 );//D6 - scu_pinmux( 1 , 14 , MD_PLN_FAST , 3 );//D7 - scu_pinmux( 5 , 4 , MD_PLN_FAST , 2 );//D8 - scu_pinmux( 5 , 5 , MD_PLN_FAST , 2 );//D9 - scu_pinmux( 5 , 6 , MD_PLN_FAST , 2 );//D10 - scu_pinmux( 5 , 7 , MD_PLN_FAST , 2 );//D11 - scu_pinmux( 5 , 0 , MD_PLN_FAST , 2 );//D12 - scu_pinmux( 5 , 1 , MD_PLN_FAST , 2 );//D13 - scu_pinmux( 5 , 2 , MD_PLN_FAST , 2 );//D14 - scu_pinmux( 5 , 3 , MD_PLN_FAST , 2 );//D15 - scu_pinmux( 13 , 2 , MD_PLN_FAST , 2 );//D16 - scu_pinmux( 13 , 3 , MD_PLN_FAST , 2 );//D17 - scu_pinmux( 13 , 4 , MD_PLN_FAST , 2 );//D18 - scu_pinmux( 13 , 5 , MD_PLN_FAST , 2 );//D19 - scu_pinmux( 13 , 6 , MD_PLN_FAST , 2 );//D20 - scu_pinmux( 13 , 7 , MD_PLN_FAST , 2 );//D21 - scu_pinmux( 13 , 8 , MD_PLN_FAST , 2 );//D22 - scu_pinmux( 13 , 9 , MD_PLN_FAST , 2 );//D23 - scu_pinmux( 14 , 5 , MD_PLN_FAST , 3 );//D24 - scu_pinmux( 14 , 6 , MD_PLN_FAST , 3 );//D25 - scu_pinmux( 14 , 7 , MD_PLN_FAST , 3 );//D26 - scu_pinmux( 14 , 8 , MD_PLN_FAST , 3 );//D27 - scu_pinmux( 14 , 9 , MD_PLN_FAST , 3 );//D28 - scu_pinmux( 14 , 10 , MD_PLN_FAST , 3 );//D29 - scu_pinmux( 14 , 11 , MD_PLN_FAST , 3 );//D30 - scu_pinmux( 14 , 12 , MD_PLN_FAST , 3 );//D31 - - scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 );//OE - scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 );//WE - - scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 );//BLS0 - scu_pinmux( 6 , 6 , MD_PLN_FAST , 1 );//BLS1 - scu_pinmux( 13 , 13 , MD_PLN_FAST , 2 );//BLS2 - scu_pinmux( 13 , 10 , MD_PLN_FAST , 2 );//BLS3 - - scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 );//CS0 - scu_pinmux( 6 , 3 , MD_PLN_FAST , 3 );//CS1 - scu_pinmux( 13 , 12 , MD_PLN_FAST , 2 );//CS2 - scu_pinmux( 13 , 11 , MD_PLN_FAST , 2 );//CS3 -} - - -static uint32_t nandReadId(void) -{ - uint8_t a, b, c, d; - volatile uint8_t *pCLE; - volatile uint8_t *pALE; - volatile uint8_t *pData; - - pCLE = K9F1G_CLE; - pALE = K9F1G_ALE; - pData = K9F1G_DATA; - - *pCLE = K9FXX_READ_ID; - *pALE = 0; - - a = *pData; - b = *pData; - c = *pData; - d = *pData; - - - return (a << 24) | (b << 16) | (c << 8) | d; -} - -static uint8_t nandStatus(void) -{ - uint8_t status = 0; - volatile uint8_t *pCLE; - volatile uint8_t *pALE; - volatile uint8_t *pData; - - pCLE = K9F1G_CLE; - pALE = K9F1G_ALE; - pData = K9F1G_DATA; - - *pCLE = K9FXX_READ_STATUS; - *pALE = 0; - - status = *pData; - - /* remove bits not used */ - return (status & 0xC1); -} - -static void nandWaitReady(void) -{ - while( !(nandStatus() & (1<<6)) ); -} - -/****************************************************************************** - * Public Functions - *****************************************************************************/ - - - -/****************************************************************************** - * - * Description: - * Initialize the NAND Flash - * - * Returns: - * TRUE if initialization successful; otherwise FALSE - * - *****************************************************************************/ -uint32_t nand_init (void) -{ - uint32_t nandId = 0; - TIM_TIMERCFG_Type timerCfg; - -// LPC_SC->PCONP |= 0x00000800; - LPC_EMC->CONTROL = 0x00000001; - LPC_EMC->CONFIG = 0x00000000; - - pinConfig(); - - TIM_ConfigStructInit(TIM_TIMER_MODE, &timerCfg); - TIM_Init(LPC_TIMER0, TIM_TIMER_MODE, &timerCfg); - - LPC_EMC->STATICCONFIG1 = 0x00000080; - - LPC_EMC->STATICWAITWEN1 = 0x00000002; - LPC_EMC->STATICWAITOEN1 = 0x00000002; - LPC_EMC->STATICWAITRD1 = 0x00000008; - LPC_EMC->STATICWAITPAG1 = 0x0000001f; - LPC_EMC->STATICWAITWR1 = 0x00000008; - LPC_EMC->STATICWAITTURN1 = 0x0000000f; - - nandId = nandReadId(); - - if ((nandId & 0xffff0000) != - (((uint32_t)(ID_MARKER_CODE) << 24) | ID_SAMSUNG << 16)) { - /* unknown NAND chip */ - return FALSE; - } - - pageSize = 1024 * (1 << (nandId & 0x03)); - blockSize = 64*1024 * (1 << ((nandId>>4) & 0x03)); - reduntSize = 8 * (1 << ((nandId >> 1) & 0x1)); - - - return TRUE; -} - -/****************************************************************************** - * - * Description: - * Get the page size of the NAND flash - * - * Returns: - * page size in bytes - * - *****************************************************************************/ -uint32_t nand_getPageSize(void) -{ - return pageSize; -} - -/****************************************************************************** - * - * Description: - * Get the block size of the NAND flash - * - * Returns: - * block size in bytes - * - *****************************************************************************/ -uint32_t nand_getBlockSize(void) -{ - return blockSize; -} - -/****************************************************************************** - * - * Description: - * Get the redundant (spare) size per page - * - * Returns: - * redundant/spare size in bytes - * - *****************************************************************************/ -uint32_t nand_getRedundantSize(void) -{ - return reduntSize * (pageSize/512); -} - -/****************************************************************************** - * - * Description: - * Check if a block is valid - * - * Returns: - * TRUE if the block is valid; otherwise FALSE - * - *****************************************************************************/ -uint32_t nand_isBlockValid(uint32_t block) -{ - uint32_t addr = 0; - uint32_t page = 0; - - volatile uint8_t *pCLE; - volatile uint8_t *pALE; - volatile uint8_t *pData; - - - pCLE = K9F1G_CLE; - pALE = K9F1G_ALE; - pData = K9F1G_DATA; - - if (block >= NAND_NUM_BLOCKS) { - return FALSE; - } - - addr = block * (blockSize/pageSize); - - /* - * Check page 0 and page 1 in each block. If the first byte - * in the spare area (of either page 0 or page 1) is != 0xFF - * the block is invalid. - */ - - nandWaitReady(); - - for (page = 0; page < 2; page++) { - addr += page; - - *pCLE = K9FXX_READ_1; - *pALE = (uint8_t) (pageSize & 0x00FF); - *pALE = (uint8_t)((pageSize & 0xFF00) >> 8); - *pALE = (uint8_t)((addr & 0x00FF)); - *pALE = (uint8_t)((addr & 0xFF00) >> 8); - *pCLE = K9FXX_READ_2; - - WAIT_READY(); - - if (*pData != 0xFF) { - return FALSE; - } - - } - - return TRUE; -} - - -/****************************************************************************** - * - * Description: - * Read a page from the NAND memory - * - * Params: - * block - block number to read from - * page - page with�n block to read from - * pageBuf - data is copied to this buffer. The size must be at least - * pageSize. - * - * Returns: - * TRUE if read successful; otherwise FALSE - * - *****************************************************************************/ -uint32_t nand_readPage(uint32_t block, uint32_t page, uint8_t* pageBuf) -{ - uint32_t i = 0; - uint32_t addr = 0; - - volatile uint8_t *pCLE; - volatile uint8_t *pALE; - volatile uint8_t *pData; - - - pCLE = K9F1G_CLE; - pALE = K9F1G_ALE; - pData = K9F1G_DATA; - - if (block >= NAND_NUM_BLOCKS) { - return FALSE; - } - - if (page >= blockSize/pageSize) { - return FALSE; - } - - addr = block * (blockSize/pageSize) + page; - - /* - * Always reading from start of a page address. - * This means that the column address is always 0. - */ - - *pCLE = K9FXX_READ_1; - *pALE = 0; - *pALE = 0; - *pALE = (uint8_t)((addr & 0x00FF)); - *pALE = (uint8_t)((addr & 0xFF00) >> 8); - *pCLE = K9FXX_READ_2; - - WAIT_READY(); - - - for (i = 0; i < pageSize; i++) { - *pageBuf++ = *pData; - } - - - return TRUE; -} - -/****************************************************************************** - * - * Description: - * Write a page of data to the NAND memory - * - * Params: - * block - block number to write to - * page - page within block to write to - * pageBuf - data is copied from this buffer. The size must be at least - * pageSize. - * - * Returns: - * TRUE if write successful; otherwise FALSE - * - *****************************************************************************/ -uint32_t nand_writePage(uint32_t block, uint32_t page, uint8_t* pageBuf) -{ - uint32_t i = 0; - uint32_t addr = 0; - - volatile uint8_t *pCLE; - volatile uint8_t *pALE; - volatile uint8_t *pData; - - - pCLE = K9F1G_CLE; - pALE = K9F1G_ALE; - pData = K9F1G_DATA; - - if (block >= NAND_NUM_BLOCKS) { - return FALSE; - } - - if (page >= blockSize/pageSize) { - return FALSE; - } - - addr = block * (blockSize/pageSize) + page; - - /* - * Always writing to start of a page address. - * This means that the column address is always 0. - */ - - *pCLE = K9FXX_BLOCK_PROGRAM_1; - *pALE = 0; - *pALE = 0; - *pALE = (uint8_t)((addr & 0x00FF)); - *pALE = (uint8_t)((addr & 0xFF00) >> 8); - - - for (i = 0; i < pageSize; i++) { - *pData = *pageBuf++; - } - - *pCLE = K9FXX_BLOCK_PROGRAM_2; - - TIM_Waitus(700); - nandWaitReady(); - - return ((nandStatus() & 0x01) != 0x01); -} - -/****************************************************************************** - * - * Description: - * Erase a block - * - * Params: - * block - block number to erase - * - * Returns: - * TRUE if eras successful; otherwise FALSE - * - *****************************************************************************/ -uint32_t nand_eraseBlock(uint32_t block) -{ - uint32_t addr = 0; - - volatile uint8_t *pCLE; - volatile uint8_t *pALE; - - pCLE = K9F1G_CLE; - pALE = K9F1G_ALE; - - if (block >= NAND_NUM_BLOCKS) { - return FALSE; - } - - addr = block * (blockSize/pageSize); - - *pCLE = K9FXX_BLOCK_ERASE_1; - *pALE = (uint8_t)(addr & 0x00FF); - *pALE = (uint8_t)((addr & 0xFF00) >> 8); - *pCLE = K9FXX_BLOCK_ERASE_2; - - TIM_Waitus(700); - nandWaitReady(); - - return ((nandStatus() & 0x01) != 0x01); -} - -#endif diff --git a/hw/bsp/ea4357/nand.h b/hw/bsp/ea4357/nand.h deleted file mode 100644 index 693c67478..000000000 --- a/hw/bsp/ea4357/nand.h +++ /dev/null @@ -1,36 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ -#ifndef __NAND_H -#define __NAND_H - -#define NAND_NUM_BLOCKS (1024) - -extern uint32_t nand_init (void); -extern uint32_t nand_getPageSize(void); -extern uint32_t nand_getBlockSize(void); -extern uint32_t nand_getRedundantSize(void); -extern uint32_t nand_isBlockValid(uint32_t blockNum); -uint32_t nand_readPage(uint32_t block, uint32_t page, uint8_t* pageBuf); -uint32_t nand_writePage(uint32_t block, uint32_t page, uint8_t* pageBuf); -uint32_t nand_eraseBlock(uint32_t block); - - -#endif /* end __NAND_H */ -/**************************************************************************** -** End Of File -*****************************************************************************/ diff --git a/hw/bsp/ea4357/sdram.c b/hw/bsp/ea4357/sdram.c deleted file mode 100644 index 68c67cf52..000000000 --- a/hw/bsp/ea4357/sdram.c +++ /dev/null @@ -1,272 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ - - - -/****************************************************************************** - * Includes - *****************************************************************************/ -#include "../board.h" - -#if BOARD == BOARD_EA4357 - -#include "LPC43xx.h" -#include "lpc_types.h" -#include "lpc43xx_scu.h" -#include "lpc43xx_timer.h" -#include "lpc43xx_cgu.h" -#include "sdram.h" -#include - -/****************************************************************************** - * Defines and typedefs - *****************************************************************************/ - -/* SDRAM refresh time to 16 clock num */ -#define EMC_SDRAM_REFRESH(freq,time) \ - (((uint64_t)((uint64_t)time * freq)/16000000000ull)+1) - -/****************************************************************************** - * External global variables - *****************************************************************************/ - -/****************************************************************************** - * Local variables - *****************************************************************************/ - -/****************************************************************************** - * Local Functions - *****************************************************************************/ - - -/*-------------------------PRIVATE FUNCTIONS------------------------------*/ -/********************************************************************* - * @brief Calculate EMC Clock from nano second - * @param[in] freq - frequency of EMC Clk - * @param[in] time - nano second - * @return None - **********************************************************************/ -uint32_t NS2CLK(uint32_t freq, uint32_t time){ - return (((uint64_t)time*freq/1000000000)); -} - -static void pinConfig(void) -{ - /* Set up EMC pin */ - scu_pinmux( 2 , 9 , MD_PLN_FAST , 3 );//A0 - scu_pinmux( 2 , 10 , MD_PLN_FAST , 3 );//A1 - scu_pinmux( 2 , 11 , MD_PLN_FAST , 3 );//A2 - scu_pinmux( 2 , 12 , MD_PLN_FAST , 3 );//A3 - scu_pinmux( 2 , 13 , MD_PLN_FAST , 3 );//A4 - scu_pinmux( 1 , 0 , MD_PLN_FAST , 2 );//A5 - scu_pinmux( 1 , 1 , MD_PLN_FAST , 2 );//A6 - scu_pinmux( 1 , 2 , MD_PLN_FAST , 2 );//A7 - scu_pinmux( 2 , 8 , MD_PLN_FAST , 3 );//A8 - scu_pinmux( 2 , 7 , MD_PLN_FAST , 3 );//A9 - scu_pinmux( 2 , 6 , MD_PLN_FAST , 2 );//A10 - scu_pinmux( 2 , 2 , MD_PLN_FAST , 2 );//A11 - scu_pinmux( 2 , 1 , MD_PLN_FAST , 2 );//A12 - scu_pinmux( 2 , 0 , MD_PLN_FAST , 2 );//A13 - scu_pinmux( 6 , 8 , MD_PLN_FAST , 1 );//A14 - scu_pinmux( 6 , 7 , MD_PLN_FAST , 1 );//A15 - scu_pinmux( 13 , 16 , MD_PLN_FAST , 2 );//A16 - scu_pinmux( 13 , 15 , MD_PLN_FAST , 2 );//A17 - scu_pinmux( 14 , 0 , MD_PLN_FAST , 3 );//A18 - scu_pinmux( 14 , 1 , MD_PLN_FAST , 3 );//A19 - scu_pinmux( 14 , 2 , MD_PLN_FAST , 3 );//A20 - scu_pinmux( 14 , 3 , MD_PLN_FAST , 3 );//A21 - scu_pinmux( 14 , 4 , MD_PLN_FAST , 3 );//A22 - scu_pinmux( 10 , 4 , MD_PLN_FAST , 3 );//A23 - - scu_pinmux( 1 , 7 , MD_PLN_FAST , 3 );//D0 - scu_pinmux( 1 , 8 , MD_PLN_FAST , 3 );//D1 - scu_pinmux( 1 , 9 , MD_PLN_FAST , 3 );//D2 - scu_pinmux( 1 , 10 , MD_PLN_FAST , 3 );//D3 - scu_pinmux( 1 , 11 , MD_PLN_FAST , 3 );//D4 - scu_pinmux( 1 , 12 , MD_PLN_FAST , 3 );//D5 - scu_pinmux( 1 , 13 , MD_PLN_FAST , 3 );//D6 - scu_pinmux( 1 , 14 , MD_PLN_FAST , 3 );//D7 - scu_pinmux( 5 , 4 , MD_PLN_FAST , 2 );//D8 - scu_pinmux( 5 , 5 , MD_PLN_FAST , 2 );//D9 - scu_pinmux( 5 , 6 , MD_PLN_FAST , 2 );//D10 - scu_pinmux( 5 , 7 , MD_PLN_FAST , 2 );//D11 - scu_pinmux( 5 , 0 , MD_PLN_FAST , 2 );//D12 - scu_pinmux( 5 , 1 , MD_PLN_FAST , 2 );//D13 - scu_pinmux( 5 , 2 , MD_PLN_FAST , 2 );//D14 - scu_pinmux( 5 , 3 , MD_PLN_FAST , 2 );//D15 - scu_pinmux( 13 , 2 , MD_PLN_FAST , 2 );//D16 - scu_pinmux( 13 , 3 , MD_PLN_FAST , 2 );//D17 - scu_pinmux( 13 , 4 , MD_PLN_FAST , 2 );//D18 - scu_pinmux( 13 , 5 , MD_PLN_FAST , 2 );//D19 - scu_pinmux( 13 , 6 , MD_PLN_FAST , 2 );//D20 - scu_pinmux( 13 , 7 , MD_PLN_FAST , 2 );//D21 - scu_pinmux( 13 , 8 , MD_PLN_FAST , 2 );//D22 - scu_pinmux( 13 , 9 , MD_PLN_FAST , 2 );//D23 - scu_pinmux( 14 , 5 , MD_PLN_FAST , 3 );//D24 - scu_pinmux( 14 , 6 , MD_PLN_FAST , 3 );//D25 - scu_pinmux( 14 , 7 , MD_PLN_FAST , 3 );//D26 - scu_pinmux( 14 , 8 , MD_PLN_FAST , 3 );//D27 - scu_pinmux( 14 , 9 , MD_PLN_FAST , 3 );//D28 - scu_pinmux( 14 , 10 , MD_PLN_FAST , 3 );//D29 - scu_pinmux( 14 , 11 , MD_PLN_FAST , 3 );//D30 - scu_pinmux( 14 , 12 , MD_PLN_FAST , 3 );//D31 - - scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 );//OE - scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 );//WE - - scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 );//BLS0 - scu_pinmux( 6 , 6 , MD_PLN_FAST , 1 );//BLS1 - scu_pinmux( 13 , 13 , MD_PLN_FAST , 2 );//BLS2 - scu_pinmux( 13 , 10 , MD_PLN_FAST , 2 );//BLS3 - - scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 );//CS0 - scu_pinmux( 6 , 3 , MD_PLN_FAST , 3 );//CS1 - scu_pinmux( 13 , 12 , MD_PLN_FAST , 2 );//CS2 - scu_pinmux( 13 , 11 , MD_PLN_FAST , 2 );//CS3 - - scu_pinmux( 6 , 4 , MD_PLN_FAST , 3 );//CAS - scu_pinmux( 6 , 5 , MD_PLN_FAST , 3 );//RAS - - scu_pinmux( 6 , 9 , MD_PLN_FAST , 3 );//DYCS0 - scu_pinmux( 6 , 1 , MD_PLN_FAST , 1 );//DYCS1 - scu_pinmux( 13 , 14 , MD_PLN_FAST , 2 );//DYCS2 - scu_pinmux( 15 , 14 , MD_PLN_FAST , 3 );//DYCS3 - - scu_pinmux( 6 , 11 , MD_PLN_FAST , 3 );//CKEOUT0 - scu_pinmux( 6 , 2 , MD_PLN_FAST , 1 );//CKEOUT1 - scu_pinmux( 13 , 1 , MD_PLN_FAST , 2 );//CKEOUT2 - scu_pinmux( 14 , 15 , MD_PLN_FAST , 3 );//CKEOUT3 - - scu_pinmux( 6 , 12 , MD_PLN_FAST , 3 );//DQMOUT0 - scu_pinmux( 6 , 10 , MD_PLN_FAST , 3 );//DQMOUT1 - scu_pinmux( 13 , 0 , MD_PLN_FAST , 2 );//DQMOUT2 - scu_pinmux( 14 , 13 , MD_PLN_FAST , 3 );//DQMOUT3 -} - - - -/****************************************************************************** - * Public Functions - *****************************************************************************/ - - -/****************************************************************************** - * - * Description: - * Initialize the SDRAM - * - *****************************************************************************/ -uint32_t sdram_init (void) -{ - uint32_t pclk, temp; - uint64_t tmpclk; - - pinConfig(); //Full 32-bit Data bus, 24-bit Address - - /* Select EMC clock-out */ - LPC_SCU->SFSCLK_0 = MD_PLN_FAST; - LPC_SCU->SFSCLK_1 = MD_PLN_FAST; - LPC_SCU->SFSCLK_2 = MD_PLN_FAST; - LPC_SCU->SFSCLK_3 = MD_PLN_FAST; - - LPC_EMC->CONTROL = 0x00000001; - LPC_EMC->CONFIG = 0x00000000; - LPC_EMC->DYNAMICCONFIG0 = 1<<14 | 0<<12 | 2<<9 | 1<<7; /* 256Mb, 8Mx32, 4 banks, row=12, column=9 */ - - pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE); - - LPC_EMC->DYNAMICRASCAS0 = 0x00000202; /* 2 RAS, 2 CAS latency */ - LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */ - - LPC_EMC->DYNAMICRP = NS2CLK(pclk, 20); - LPC_EMC->DYNAMICRAS = NS2CLK(pclk, 42); - LPC_EMC->DYNAMICSREX = NS2CLK(pclk, 63); - LPC_EMC->DYNAMICAPR = 0x00000005; - LPC_EMC->DYNAMICDAL = 0x00000005; - LPC_EMC->DYNAMICWR = 2; - LPC_EMC->DYNAMICRC = NS2CLK(pclk, 63); - LPC_EMC->DYNAMICRFC = NS2CLK(pclk, 63); - LPC_EMC->DYNAMICXSR = NS2CLK(pclk, 63); - LPC_EMC->DYNAMICRRD = NS2CLK(pclk, 14); - LPC_EMC->DYNAMICMRD = 0x00000002; - - TIM_Waitus(100); /* wait 100ms */ - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - - TIM_Waitus(200); /* wait 200ms */ - LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */ - - LPC_EMC->DYNAMICREFRESH = EMC_SDRAM_REFRESH(pclk,70); /* ( n * 16 ) -> 32 clock cycles */ - - //for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */ - TIM_Waitus(200); /* wait 200ms */ - - tmpclk = (uint64_t)15625*(uint64_t)pclk/1000000000/16; - LPC_EMC->DYNAMICREFRESH = tmpclk; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */ - - LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */ - - //Timing for 48/60/72MHZ Bus - temp = *((volatile uint32_t *)(SDRAM_BASE | (2<<4| 2)<<(9+2+2))); /* 4 burst, 2 CAS latency */ - temp = temp; - LPC_EMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */ - - //[re]enable buffers - LPC_EMC->DYNAMICCONFIG0 |= 1<<19; - - return TRUE; -} - -uint32_t sdram_test( void ) -{ - volatile uint32_t *wr_ptr; - volatile uint16_t *short_wr_ptr; - uint32_t data; - uint32_t i, j; - - wr_ptr = (uint32_t *)SDRAM_BASE; - short_wr_ptr = (uint16_t *)wr_ptr; - - /* 16 bit write */ - for (i = 0; i < SDRAM_SIZE/0x40000; i++) - { - for (j = 0; j < 0x100; j++) - { - *short_wr_ptr++ = (i + j) & 0xFFFF; - *short_wr_ptr++ = ((i + j) + 1) & 0xFFFF; - } - } - - /* Verifying */ - wr_ptr = (uint32_t *)SDRAM_BASE; - for (i = 0; i < SDRAM_SIZE/0x40000; i++) - { - for (j = 0; j < 0x100; j++) - { - data = *wr_ptr; - if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF))) - { - return 0x0; - } - wr_ptr++; - } - } - return 0x1; -} - -#endif diff --git a/hw/bsp/ea4357/sdram.h b/hw/bsp/ea4357/sdram.h deleted file mode 100644 index 82122b9f8..000000000 --- a/hw/bsp/ea4357/sdram.h +++ /dev/null @@ -1,31 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ -#ifndef __SDRAM_H -#define __SDRAM_H - -#define SDRAM_SIZE 0x2000000 /* 256Mbit = 32MB */ - -#define SDRAM_BASE 0x28000000 /*CS0*/ - -extern uint32_t sdram_init(void); -extern uint32_t sdram_test(void); - -#endif /* end __SDRAM_H */ -/**************************************************************************** -** End Of File -*****************************************************************************/